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add network simulation C++ code

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This commit is contained in:
Howard Mao
2017-07-01 19:58:31 -07:00
parent b662854750
commit cb6290539c
4 changed files with 22 additions and 6 deletions
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17
src/main/scala/example/Configs.scala
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@@ -33,7 +33,7 @@ class WithSimBlockDevice extends Config((site, here, up) => {
} }
}) })
class WithSimpleNIC extends Config((site, here, up) => { class WithLoopbackNIC extends Config((site, here, up) => {
case BuildTop => (p: Parameters) => { case BuildTop => (p: Parameters) => {
val top = Module(LazyModule(new ExampleTopWithSimpleNIC()(p)).module) val top = Module(LazyModule(new ExampleTopWithSimpleNIC()(p)).module)
top.connectNicLoopback() top.connectNicLoopback()
@@ -41,6 +41,14 @@ class WithSimpleNIC extends Config((site, here, up) => {
} }
}) })
class WithSimNetwork extends Config((site, here, up) => {
case BuildTop => (p: Parameters) => {
val top = Module(LazyModule(new ExampleTopWithSimpleNIC()(p)).module)
top.connectSimNetwork()
top
}
})
class BaseExampleConfig extends Config( class BaseExampleConfig extends Config(
new WithoutTLMonitors ++ new WithoutTLMonitors ++
new WithSerialAdapter ++ new WithSerialAdapter ++
@@ -60,8 +68,11 @@ class SimBlockDeviceConfig extends Config(
class BlockDeviceModelConfig extends Config( class BlockDeviceModelConfig extends Config(
new WithBlockDevice ++ new WithBlockDeviceModel ++ new BaseExampleConfig) new WithBlockDevice ++ new WithBlockDeviceModel ++ new BaseExampleConfig)
class SimpleNICConfig extends Config( class LoopbackNICConfig extends Config(
new WithSimpleNIC ++ new BaseExampleConfig) new WithLoopbackNIC ++ new BaseExampleConfig)
class SimNetworkConfig extends Config(
new WithSimNetwork ++ new BaseExampleConfig)
class WithTwoTrackers extends WithNBlockDeviceTrackers(2) class WithTwoTrackers extends WithNBlockDeviceTrackers(2)
class WithFourTrackers extends WithNBlockDeviceTrackers(4) class WithFourTrackers extends WithNBlockDeviceTrackers(4)

2
testchipip

Submodule testchipip updated: 0df970e8d1...4e8e50aa4d

6
verisim/Makefile
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@@ -25,14 +25,16 @@ long_name = $(PROJECT).$(MODEL).$(CONFIG)
sim_vsrcs = \ sim_vsrcs = \
$(build_dir)/$(long_name).v \ $(build_dir)/$(long_name).v \
$(base_dir)/rocket-chip/vsrc/AsyncResetReg.v \ $(base_dir)/rocket-chip/vsrc/AsyncResetReg.v \
$(base_dir)/rocket-chip/vsrc/plusarg_reader.v \
$(base_dir)/testchipip/vsrc/SimSerial.v \ $(base_dir)/testchipip/vsrc/SimSerial.v \
$(base_dir)/testchipip/vsrc/SimBlockDevice.v $(base_dir)/testchipip/vsrc/SimBlockDevice.v \
$(base_dir)/testchipip/vsrc/SimNetwork.v
sim_csrcs = \ sim_csrcs = \
$(base_dir)/testchipip/csrc/SimSerial.cc \ $(base_dir)/testchipip/csrc/SimSerial.cc \
$(base_dir)/testchipip/csrc/SimBlockDevice.cc \ $(base_dir)/testchipip/csrc/SimBlockDevice.cc \
$(base_dir)/testchipip/csrc/SimNetwork.cc \
$(base_dir)/testchipip/csrc/blkdev.cc \ $(base_dir)/testchipip/csrc/blkdev.cc \
$(base_dir)/testchipip/csrc/network.cc \
$(base_dir)/testchipip/csrc/verilator-harness.cc $(base_dir)/testchipip/csrc/verilator-harness.cc
model_dir = $(build_dir)/$(long_name) model_dir = $(build_dir)/$(long_name)

3
vsim/Makefile
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@@ -23,11 +23,14 @@ sim_vsrcs = \
$(base_dir)/rocket-chip/vsrc/plusarg_reader.v \ $(base_dir)/rocket-chip/vsrc/plusarg_reader.v \
$(base_dir)/testchipip/vsrc/SimSerial.v \ $(base_dir)/testchipip/vsrc/SimSerial.v \
$(base_dir)/testchipip/vsrc/SimBlockDevice.v \ $(base_dir)/testchipip/vsrc/SimBlockDevice.v \
$(base_dir)/testchipip/vsrc/SimNetwork.v \
sim_csrcs = \ sim_csrcs = \
$(base_dir)/testchipip/csrc/SimSerial.cc \ $(base_dir)/testchipip/csrc/SimSerial.cc \
$(base_dir)/testchipip/csrc/SimBlockDevice.cc \ $(base_dir)/testchipip/csrc/SimBlockDevice.cc \
$(base_dir)/testchipip/csrc/SimNetwork.cc \
$(base_dir)/testchipip/csrc/blkdev.cc \ $(base_dir)/testchipip/csrc/blkdev.cc \
$(base_dir)/testchipip/csrc/network.cc \
VCS = vcs -full64 VCS = vcs -full64