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add network simulation C++ code

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This commit is contained in:
Howard Mao
2017-07-01 19:58:31 -07:00
parent b662854750
commit cb6290539c
4 changed files with 22 additions and 6 deletions
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6
verisim/Makefile
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@@ -25,14 +25,16 @@ long_name = $(PROJECT).$(MODEL).$(CONFIG)
sim_vsrcs = \
$(build_dir)/$(long_name).v \
$(base_dir)/rocket-chip/vsrc/AsyncResetReg.v \
$(base_dir)/rocket-chip/vsrc/plusarg_reader.v \
$(base_dir)/testchipip/vsrc/SimSerial.v \
$(base_dir)/testchipip/vsrc/SimBlockDevice.v
$(base_dir)/testchipip/vsrc/SimBlockDevice.v \
$(base_dir)/testchipip/vsrc/SimNetwork.v
sim_csrcs = \
$(base_dir)/testchipip/csrc/SimSerial.cc \
$(base_dir)/testchipip/csrc/SimBlockDevice.cc \
$(base_dir)/testchipip/csrc/SimNetwork.cc \
$(base_dir)/testchipip/csrc/blkdev.cc \
$(base_dir)/testchipip/csrc/network.cc \
$(base_dir)/testchipip/csrc/verilator-harness.cc
model_dir = $(build_dir)/$(long_name)