Merge branch 'dev' into local-fpga-support

.circleci/check-commit.sh

@@ -48,7 +48,7 @@ search () {
     done
 }
 
-submodules=("ariane" "boom" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor")
+submodules=("cva6" "boom" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor")
 dir="generators"
 if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ]
 then

.circleci/config.yml

@@ -237,12 +237,12 @@ jobs:
             - run-tests:
                 group-key: "group-cores"
                 project-key: "chipyard-boom"
-    chipyard-ariane-run-tests:
+    chipyard-cva6-run-tests:
         executor: main-env
         steps:
             - run-tests:
                 group-key: "group-cores"
-                project-key: "chipyard-ariane"
+                project-key: "chipyard-cva6"
                 timeout: "30m"
     chipyard-sodor-run-tests:
         executor: main-env
@@ -251,6 +251,12 @@ jobs:
                 group-key: "group-cores"
                 project-key: "chipyard-sodor"
                 timeout: "30m"
+    chipyard-multiclock-rocket-run-tests:
+        executor: main-env
+        steps:
+            - run-tests:
+                group-key: "group-cores"
+                project-key: "chipyard-multiclock-rocket"
     chipyard-dmirocket-run-tests:
         executor: main-env
         steps:
@@ -440,7 +446,7 @@ workflows:
             - chipyard-boom-run-tests:
                 requires:
                     - prepare-chipyard-cores
-            - chipyard-ariane-run-tests:
+            - chipyard-cva6-run-tests:
                 requires:
                     - prepare-chipyard-cores
             - chipyard-sodor-run-tests:

.circleci/defaults.sh

@@ -34,8 +34,9 @@ REMOTE_CHIPYARD_DIR=$REMOTE_WORK_DIR/chipyard
 REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator
 REMOTE_FIRESIM_DIR=$REMOTE_CHIPYARD_DIR/sims/firesim/sim
 REMOTE_FPGA_DIR=$REMOTE_CHIPYARD_DIR/fpga
+REMOTE_JAVA_OPTS="-Xmx10G -Xss8M"
 # Disable the supershell to greatly improve the readability of SBT output when captured by Circle CI
-REMOTE_JAVA_ARGS="-Xmx9G -Xss8M -Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot"
+REMOTE_SBT_OPTS="-Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot"
 REMOTE_VERILATOR_DIR=$REMOTE_PREFIX-$CIRCLE_SHA1-verilator-install
 
 # local variables (aka within the docker container)
@@ -48,7 +49,7 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim
 
 # key value store to get the build groups
 declare -A grouping
-grouping["group-cores"]="chipyard-ariane chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop"
+grouping["group-cores"]="chipyard-cva6 chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket"
 grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spiflashread chipyard-spiflashwrite chipyard-mmios chipyard-lbwif"
 grouping["group-accels"]="chipyard-nvdla chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough"
 grouping["group-tracegen"]="tracegen tracegen-boom"
@@ -69,7 +70,7 @@ mapping["chipyard-boom"]=" CONFIG=SmallBoomConfig"
 mapping["chipyard-blkdev"]=" CONFIG=SimBlockDeviceRocketConfig"
 mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig"
 mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig"
-mapping["chipyard-ariane"]=" CONFIG=ArianeConfig"
+mapping["chipyard-cva6"]=" CONFIG=CVA6Config"
 mapping["chipyard-spiflashread"]=" CONFIG=LargeSPIFlashROMRocketConfig"
 mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig"
 mapping["chipyard-mmios"]=" CONFIG=MMIORocketConfig verilog"
@@ -77,6 +78,7 @@ mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config"
 mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig"
 mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig"
 mapping["chipyard-sodor"]=" CONFIG=Sodor5StageConfig"
+mapping["chipyard-multiclock-rocket"]=" CONFIG=MulticlockRocketConfig"
 
 mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests"
 mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Tests"

.circleci/do-rtl-build.sh

@@ -77,7 +77,7 @@ do
          export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \
          export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \
          export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \
-         make -j$REMOTE_MAKE_NPROC -C $REMOTE_MAKE_DIR FIRRTL_LOGLEVEL=info JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$key]}"
+         make -j$REMOTE_MAKE_NPROC -C $REMOTE_MAKE_DIR FIRRTL_LOGLEVEL=info JAVA_OPTS=\"$REMOTE_JAVA_OPTS\" SBT_OPTS=\"$REMOTE_SBT_OPTS\" ${mapping[$key]}"
 done
 
 run "rm -rf $REMOTE_CHIPYARD_DIR/project"

.circleci/run-firesim-scala-tests.sh

@@ -49,4 +49,4 @@ run "export RISCV=\"$TOOLS_DIR\"; \
      export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \
      export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \
      export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \
-     make -C $REMOTE_FIRESIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" testOnly ${mapping[$1]}"
+     make -C $REMOTE_FIRESIM_DIR JAVA_OPTS=\"$REMOTE_JAVA_OPTS\" SBT_OPTS=\"$REMOTE_SBT_OPTS\" testOnly ${mapping[$1]}"

.circleci/run-tests.sh

@@ -91,7 +91,7 @@ case $1 in
     tracegen-boom)
         run_tracegen ${mapping[$1]}
         ;;
-    chipyard-ariane)
+    chipyard-cva6)
         make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/multiply.riscv
         ;;
     chipyard-sodor)

.gitignore

@@ -19,4 +19,4 @@ tags
 *~
 env-riscv-tools.sh
 env-esp-tools.sh
-.bloop/
+.bsp/

.gitmodules

@@ -76,7 +76,7 @@
 	url = https://github.com/ucb-bar/dsptools.git
 [submodule "tools/chisel-testers"]
 	path = tools/chisel-testers
-	url = https://github.com/freechipsproject/chisel-testers.git
+	url = https://github.com/ucb-bar/chisel-testers.git
 [submodule "tools/treadle"]
 	path = tools/treadle
 	url = https://github.com/freechipsproject/treadle.git
@@ -113,9 +113,9 @@
 [submodule "software/firemarshal"]
 	path = software/firemarshal
 	url = https://github.com/firesim/FireMarshal.git
-[submodule "generators/ariane"]
+[submodule "generators/cva6"]
-	path = generators/ariane
+	path = generators/cva6
-	url = https://github.com/ucb-bar/ariane-wrapper.git
+	url = https://github.com/ucb-bar/cva6-wrapper.git
 [submodule "tools/DRAMSim2"]
 	path = tools/DRAMSim2
 	url = https://github.com/firesim/DRAMSim2.git

README.md

@@ -10,7 +10,7 @@ To get started using Chipyard, see the documentation on the Chipyard documentati
 
 Chipyard is an open source framework for agile development of Chisel-based systems-on-chip.
 It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators.
-Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [Ariane][ariane]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC.
+Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [CVA6 (Ariane)][cva6]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC.
 Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation ([FireSim][firesim]), automated VLSI flows ([Hammer][hammer]), and software workload generation for bare-metal and Linux-based systems ([FireMarshal][firemarshal]).
 Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley].
 
@@ -80,6 +80,6 @@ These additional publications cover many of the internal components used in Chip
 [rocket-chip]: https://github.com/freechipsproject/rocket-chip
 [boom]: https://github.com/riscv-boom/riscv-boom
 [firemarshal]: https://github.com/firesim/FireMarshal/
-[ariane]: https://github.com/pulp-platform/ariane/
+[cva6]: https://github.com/openhwgroup/cva6/
 [gemmini]: https://github.com/ucb-bar/gemmini
 [nvdla]: http://nvdla.org/

build.sbt

@@ -1,30 +1,34 @@
 import Tests._
 
-// This gives us a nicer handle  to the root project instead of using the
+// This gives us a nicer handle to the root project instead of using the
 // implicit one
 lazy val chipyardRoot = Project("chipyardRoot", file("."))
 
 lazy val commonSettings = Seq(
   organization := "edu.berkeley.cs",
-  version := "1.0",
+  version := "1.3",
   scalaVersion := "2.12.10",
-  traceLevel := 15,
   test in assembly := {},
   assemblyMergeStrategy in assembly := { _ match {
     case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard
     case _ => MergeStrategy.first}},
   scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"),
-  libraryDependencies += "org.scalatest" %% "scalatest" % "3.0.8" % "test",
+  addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.1" cross CrossVersion.full),
-  libraryDependencies += "org.json4s" %% "json4s-jackson" % "3.6.1",
-  libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value,
-  libraryDependencies += "com.github.scopt" %% "scopt" % "3.7.0",
-  libraryDependencies += "org.scala-lang.modules" % "scala-jline" % "2.12.1",
-  libraryDependencies += "com.typesafe.play" %% "play-json" % "2.6.10",
-  libraryDependencies += "org.typelevel" %% "spire" % "0.16.2",
-  libraryDependencies += "org.scalanlp" %% "breeze" % "1.0",
-  addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full),
   unmanagedBase := (chipyardRoot / unmanagedBase).value,
-  allDependencies := allDependencies.value.filterNot(_.organization == "edu.berkeley.cs"),
+  allDependencies := {
+    // drop specific maven dependencies in subprojects in favor of Chipyard's version
+    val dropDeps = Seq(
+      ("edu.berkeley.cs", "firrtl"),
+      ("edu.berkeley.cs", "chisel3"),
+      ("edu.berkeley.cs", "rocketchip"),
+      ("edu.berkeley.cs", "chisel-iotesters"),
+      ("edu.berkeley.cs", "treadle"),
+      ("edu.berkeley.cs", "firrtl-interpreter"))
+
+    allDependencies.value.filterNot { dep =>
+      dropDeps.contains((dep.organization, dep.name))
+    }
+  },
   exportJars := true,
   resolvers ++= Seq(
     Resolver.sonatypeRepo("snapshots"),
@@ -40,19 +44,6 @@ lazy val firesimDir = if (firesimAsLibrary) {
   file("../../sim")
 }
 
-// Checks for -DROCKET_USE_MAVEN.
-// If it's there, use a maven dependency.
-// Else, depend on subprojects in git submodules.
-def conditionalDependsOn(prj: Project): Project = {
-  if (sys.props.contains("ROCKET_USE_MAVEN")) {
-    prj.settings(Seq(
-      libraryDependencies += "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHOT",
-    ))
-  } else {
-    prj.dependsOn(testchipip)
-  }
-}
-
 /**
   * It has been a struggle for us to override settings in subprojects.
   * An example would be adding a dependency to rocketchip on midas's targetutils library,
@@ -72,149 +63,248 @@ def freshProject(name: String, dir: File): Project = {
 // Fork each scala test for now, to work around persistent mutable state
 // in Rocket-Chip based generators
 def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test =>
-      val options = ForkOptions()
+  val options = ForkOptions()
-      new Group(test.name, Seq(test), SubProcess(options))
+  new Group(test.name, Seq(test), SubProcess(options))
-  } toSeq
+} toSeq
 
 // Subproject definitions begin
-//
+
-// FIRRTL is handled as an unmanaged dependency. Make will build the firrtl jar
+// -- Rocket Chip --
-// before launching sbt if any of the firrtl source files has been updated
+
-// The jar is dropped in chipyard's lib/ directory, which is used as the unmanagedBase
+// This needs to stay in sync with the chisel3 and firrtl git submodules
-// for all subprojects
+val chiselVersion = "3.4.1"
-lazy val chisel  = (project in file("tools/chisel3"))
+lazy val chiselRef = ProjectRef(workspaceDirectory / "chisel3", "chisel")
+lazy val chiselLib = "edu.berkeley.cs" %% "chisel3" % chiselVersion
+lazy val chiselLibDeps = (chiselRef / Keys.libraryDependencies)
+// While not built from source, *must* be in sync with the chisel3 git submodule
+// Building from source requires extending sbt-sriracha or a similar plugin and
+//   keeping scalaVersion in sync with chisel3 to the minor version
+lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full
+
+val firrtlVersion = "1.4.1"
+lazy val firrtlRef = ProjectRef(workspaceDirectory / "firrtl", "firrtl")
+lazy val firrtlLib = "edu.berkeley.cs" %% "firrtl" % firrtlVersion
+val firrtlLibDeps = settingKey[Seq[sbt.librarymanagement.ModuleID]]("FIRRTL Library Dependencies sans antlr4")
+Global / firrtlLibDeps := {
+  // drop antlr4 compile dep. but keep antlr4-runtime dep. (compile needs the plugin to be setup)
+  (firrtlRef / Keys.libraryDependencies).value.filterNot(_.name == "antlr4")
+}
+
+ // Rocket-chip dependencies (subsumes making RC a RootProject)
+lazy val hardfloat  = (project in rocketChipDir / "hardfloat")
+  .sourceDependency(chiselRef, chiselLib)
+  .settings(addCompilerPlugin(chiselPluginLib))
+  .settings(libraryDependencies ++= chiselLibDeps.value)
+  .dependsOn(midasTargetUtils)
+  .settings(commonSettings)
+  .settings(
+    libraryDependencies ++= Seq(
+      "org.scala-lang" % "scala-reflect" % scalaVersion.value,
+      "org.json4s" %% "json4s-jackson" % "3.6.1",
+      "org.scalatest" %% "scalatest" % "3.2.0" % "test"
+    )
+  )
+
+lazy val rocketMacros  = (project in rocketChipDir / "macros")
+  .settings(commonSettings)
+  .settings(
+    libraryDependencies ++= Seq(
+      "org.scala-lang" % "scala-reflect" % scalaVersion.value,
+      "org.json4s" %% "json4s-jackson" % "3.6.1",
+      "org.scalatest" %% "scalatest" % "3.2.0" % "test"
+    )
+  )
+
+lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/build-rules/sbt")
+  .settings(commonSettings)
+  .settings(
+    libraryDependencies ++= Seq(
+      "org.scala-lang" % "scala-reflect" % scalaVersion.value,
+      "org.json4s" %% "json4s-jackson" % "3.6.1",
+      "org.scalatest" %% "scalatest" % "3.2.0" % "test"
+    )
+  )
+
+lazy val rocketchip = freshProject("rocketchip", rocketChipDir)
+  .sourceDependency(chiselRef, chiselLib)
+  .settings(addCompilerPlugin(chiselPluginLib))
+  .settings(libraryDependencies ++= chiselLibDeps.value)
+  .dependsOn(hardfloat, rocketMacros, rocketConfig)
+  .settings(commonSettings)
+  .settings(
+    libraryDependencies ++= Seq(
+      "org.scala-lang" % "scala-reflect" % scalaVersion.value,
+      "org.json4s" %% "json4s-jackson" % "3.6.1",
+      "org.scalatest" %% "scalatest" % "3.2.0" % "test"
+    )
+  )
+  .settings( // Settings for scalafix
+    semanticdbEnabled := true,
+    semanticdbVersion := scalafixSemanticdb.revision,
+    scalacOptions += "-Ywarn-unused-import"
+  )
+lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies)
+
+// -- Chipyard-managed External Projects --
 
 lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter"))
+  .sourceDependency(firrtlRef, firrtlLib)
   .settings(commonSettings)
+  .settings(libraryDependencies ++= (Global / firrtlLibDeps).value)
+lazy val firrtlInterpreterLibDeps = (firrtl_interpreter / Keys.libraryDependencies)
 
 lazy val treadle = (project in file("tools/treadle"))
+  .sourceDependency(firrtlRef, firrtlLib)
   .settings(commonSettings)
+  .settings(libraryDependencies ++= (Global / firrtlLibDeps).value)
+lazy val treadleLibDeps = (treadle / Keys.libraryDependencies)
 
 lazy val chisel_testers = (project in file("tools/chisel-testers"))
-  .dependsOn(chisel, firrtl_interpreter, treadle)
+  .sourceDependency(chiselRef, chiselLib)
-  .settings(
+  .settings(addCompilerPlugin(chiselPluginLib))
-      commonSettings,
+  .settings(libraryDependencies ++= chiselLibDeps.value)
-      libraryDependencies ++= Seq(
+  .dependsOn(firrtl_interpreter, treadle)
-        "junit" % "junit" % "4.12",
+  .settings(libraryDependencies ++= firrtlInterpreterLibDeps.value)
-        "org.scalatest" %% "scalatest" % "3.0.5",
+  .settings(libraryDependencies ++= treadleLibDeps.value)
-        "org.scalacheck" %% "scalacheck" % "1.14.0",
+  .settings(commonSettings)
-        "com.github.scopt" %% "scopt" % "3.7.0"
+lazy val chiselTestersLibDeps = (chisel_testers / Keys.libraryDependencies)
-      )
+
-    )
+// -- Normal Projects --
 
 // Contains annotations & firrtl passes you may wish to use in rocket-chip without
 // introducing a circular dependency between RC and MIDAS
 lazy val midasTargetUtils = ProjectRef(firesimDir, "targetutils")
 
- // Rocket-chip dependencies (subsumes making RC a RootProject)
-lazy val hardfloat  = (project in rocketChipDir / "hardfloat")
-  .settings(commonSettings).dependsOn(midasTargetUtils)
-
-lazy val rocketMacros  = (project in rocketChipDir / "macros")
-  .settings(commonSettings)
-
-lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/build-rules/sbt")
-  .settings(commonSettings)
-
-lazy val rocketchip = freshProject("rocketchip", rocketChipDir)
-  .settings(commonSettings)
-  .dependsOn(chisel, hardfloat, rocketMacros, rocketConfig)
-
 lazy val testchipip = (project in file("generators/testchipip"))
   .dependsOn(rocketchip, sifive_blocks)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
+lazy val testchipipLib = "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHOT"
 
-lazy val iocell = (project in file("./tools/barstools/iocell/"))
+lazy val chipyard = (project in file("generators/chipyard"))
-  .dependsOn(chisel)
+  .sourceDependency(testchipip, testchipipLib)
-  .settings(commonSettings)
+  .dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell,
-
-lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard"))
-  .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell,
     sha3, // On separate line to allow for cleaner tutorial-setup patches
     dsptools, `rocket-dsptools`,
-    gemmini, icenet, tracegen, ariane, nvdla, sodor)
+    gemmini, icenet, tracegen, cva6, nvdla, sodor)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen"))
+lazy val tracegen = (project in file("generators/tracegen"))
+  .sourceDependency(testchipip, testchipipLib)
   .dependsOn(rocketchip, sifive_cache, boom, utilities)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val utilities = conditionalDependsOn(project in file("generators/utilities"))
+lazy val utilities = (project in file("generators/utilities"))
+  .sourceDependency(testchipip, testchipipLib)
   .settings(commonSettings)
 
 lazy val icenet = (project in file("generators/icenet"))
-  .dependsOn(rocketchip, testchipip)
+  .sourceDependency(testchipip, testchipipLib)
+  .dependsOn(rocketchip)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
 lazy val hwacha = (project in file("generators/hwacha"))
   .dependsOn(rocketchip)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val boom = conditionalDependsOn(project in file("generators/boom"))
+lazy val boom = (project in file("generators/boom"))
+  .sourceDependency(testchipip, testchipipLib)
   .dependsOn(rocketchip)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val ariane = (project in file("generators/ariane"))
+lazy val cva6 = (project in file("generators/cva6"))
   .dependsOn(rocketchip)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
 lazy val sodor = (project in file("generators/riscv-sodor"))
   .dependsOn(rocketchip)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
 lazy val sha3 = (project in file("generators/sha3"))
   .dependsOn(rocketchip, chisel_testers, midasTargetUtils)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
+  .settings(libraryDependencies ++= chiselTestersLibDeps.value)
   .settings(commonSettings)
 
 lazy val gemmini = (project in file("generators/gemmini"))
-  .dependsOn(rocketchip, chisel_testers, testchipip)
+  .sourceDependency(testchipip, testchipipLib)
+  .dependsOn(rocketchip, chisel_testers)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
+  .settings(libraryDependencies ++= chiselTestersLibDeps.value)
   .settings(commonSettings)
 
 lazy val nvdla = (project in file("generators/nvdla"))
   .dependsOn(rocketchip)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/"))
+lazy val iocell = (project in file("./tools/barstools/iocell/"))
-  .dependsOn(chisel_testers, chipyard)
+  .sourceDependency(chiselRef, chiselLib)
+  .settings(addCompilerPlugin(chiselPluginLib))
+  .settings(libraryDependencies ++= chiselLibDeps.value)
+  .settings(commonSettings)
+
+lazy val tapeout = (project in file("./tools/barstools/tapeout/"))
+  .dependsOn(chisel_testers, chipyard) // must depend on chipyard to get scala resources
+  .settings(libraryDependencies ++= chiselTestersLibDeps.value)
   .settings(commonSettings)
-  .settings(libraryDependencies ++= Seq("io.github.daviddenton" %% "handlebars-scala-fork" % "2.3.0"))
 
 lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/"))
   .settings(commonSettings)
 
 lazy val barstoolsMacros = (project in file("./tools/barstools/macros/"))
-  .dependsOn(firrtl_interpreter, mdf, rocketchip)
+  .sourceDependency(chiselRef, chiselLib)
+  .settings(addCompilerPlugin(chiselPluginLib))
+  .settings(libraryDependencies ++= chiselLibDeps.value)
+  .dependsOn(firrtl_interpreter, mdf, chisel_testers)
+  .settings(libraryDependencies ++= chiselTestersLibDeps.value)
+  .settings(libraryDependencies ++= firrtlInterpreterLibDeps.value)
   .enablePlugins(sbtassembly.AssemblyPlugin)
   .settings(commonSettings)
 
 lazy val dsptools = freshProject("dsptools", file("./tools/dsptools"))
-  .dependsOn(chisel, chisel_testers)
+  .dependsOn(chisel_testers)
+  .settings(libraryDependencies ++= chiselTestersLibDeps.value)
   .settings(
-      commonSettings,
+    commonSettings,
-      libraryDependencies ++= Seq(
+    libraryDependencies ++= Seq(
-        "junit" % "junit" % "4.13" % "test",
+      "org.typelevel" %% "spire" % "0.16.2",
-        "org.scalatest" %% "scalatest" % "3.0.8",
+      "org.scalanlp" %% "breeze" % "1.1",
-        "org.scalacheck" %% "scalacheck" % "1.14.3" % "test"
+      "junit" % "junit" % "4.13" % "test",
+      "org.scalatest" %% "scalatest" % "3.0.+" % "test",
+      "org.scalacheck" %% "scalacheck" % "1.14.3" % "test",
   ))
 
 lazy val `rocket-dsptools` = freshProject("rocket-dsptools", file("./tools/dsptools/rocket"))
   .dependsOn(rocketchip, dsptools)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
 lazy val sifive_blocks = (project in file("generators/sifive-blocks"))
   .dependsOn(rocketchip)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val sifive_cache = (project in file("generators/sifive-cache")).settings(
+lazy val sifive_cache = (project in file("generators/sifive-cache"))
+  .settings(
     commonSettings,
-    scalaSource in Compile := baseDirectory.value / "design/craft"
+    scalaSource in Compile := baseDirectory.value / "design/craft")
-  ).dependsOn(rocketchip)
+  .dependsOn(rocketchip)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
 
 // Library components of FireSim
 lazy val midas      = ProjectRef(firesimDir, "midas")
 lazy val firesimLib = ProjectRef(firesimDir, "firesimLib")
 
-lazy val firechip = conditionalDependsOn(project in file("generators/firechip"))
+lazy val firechip = (project in file("generators/firechip"))
+  .sourceDependency(testchipip, testchipipLib)
   .dependsOn(chipyard, midasTargetUtils, midas, firesimLib % "test->test;compile->compile")
   .settings(
     commonSettings,

common.mk

@@ -17,7 +17,8 @@ HELP_COMPILATION_VARIABLES += \
 "   EXTRA_SIM_CXXFLAGS     = additional CXXFLAGS for building simulators" \
 "   EXTRA_SIM_LDFLAGS      = additional LDFLAGS for building simulators" \
 "   EXTRA_SIM_SOURCES      = additional simulation sources needed for simulator" \
-"   EXTRA_SIM_REQS         = additional make requirements to build the simulator"
+"   EXTRA_SIM_REQS         = additional make requirements to build the simulator" \
+"   ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client"
 
 EXTRA_GENERATOR_REQS ?=
 EXTRA_SIM_CXXFLAGS   ?=
@@ -41,13 +42,15 @@ HELP_COMMANDS += \
 "   run-binary-fast        = run [./$(shell basename $(sim))] and don't log instructions" \
 "   run-binary-debug       = run [./$(shell basename $(sim_debug))] and log instructions and waveform to files" \
 "   verilog                = generate intermediate verilog files from chisel elaboration and firrtl passes" \
-"   run-tests              = run all assembly and benchmark tests"
+"   firrtl                 = generate intermediate firrtl files from chisel elaboration" \
+"   run-tests              = run all assembly and benchmark tests" \
+"   launch-sbt             = start sbt terminal"
 
 #########################################################################################
 # include additional subproject make fragments
 # see HELP_COMPILATION_VARIABLES
 #########################################################################################
-include $(base_dir)/generators/ariane/ariane.mk
+include $(base_dir)/generators/cva6/cva6.mk
 include $(base_dir)/generators/tracegen/tracegen.mk
 include $(base_dir)/generators/nvdla/nvdla.mk
 include $(base_dir)/tools/dromajo/dromajo.mk
@@ -63,37 +66,23 @@ SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala)
 VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v)
 # This assumes no SBT meta-build sources
 SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools)
-SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt
+SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt $(base_dir)/project/build.properties
 
 #########################################################################################
-# jar creation variables and rules
+# SBT Server Setup (start server / rebuild proj. defs. if SBT_SOURCES change)
 #########################################################################################
-FIRRTL_JAR := $(base_dir)/lib/firrtl.jar
+$(SBT_THIN_CLIENT_TIMESTAMP): $(SBT_SOURCES)
-FIRRTL_TEST_JAR := $(base_dir)/test_lib/firrtl-test.jar
+ifneq (,$(wildcard $(SBT_THIN_CLIENT_TIMESTAMP)))
-
+	cd $(base_dir) && $(SBT) "reload"
-$(FIRRTL_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala)
-	$(MAKE) -C $(CHIPYARD_FIRRTL_DIR) SBT="$(SBT)" root_dir=$(CHIPYARD_FIRRTL_DIR) build-scala
-	mkdir -p $(@D)
-	cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl.jar $@
-	touch $@
-
-$(FIRRTL_TEST_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala)
-	cd $(CHIPYARD_FIRRTL_DIR) && $(SBT) "test:assembly"
-	mkdir -p $(@D)
-	cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl-test.jar $@
-	touch $@
-
-#########################################################################################
-# Bloop Project Definitions
-#########################################################################################
-$(BLOOP_CONFIG_DIR)/TIMESTAMP: $(SBT_SOURCES)
-	cd $(base_dir) && $(SBT) "project chipyardRoot" "bloopInstall"
 	touch $@
+else
+	cd $(base_dir) && $(SBT) "exit"
+endif
 
 #########################################################################################
 # create list of simulation file inputs
 #########################################################################################
-$(sim_files): $(call lookup_srcs,$(base_dir)/generators/utilities/src/main/scala,scala) $(FIRRTL_JAR) $(SCALA_BUILDTOOL_DEPS)
+$(sim_files): $(call lookup_srcs,$(base_dir)/generators/utilities/src/main/scala,scala) $(SCALA_BUILDTOOL_DEPS)
 	$(call run_scala_main,utilities,utilities.GenerateSimFiles,-td $(build_dir) -sim $(sim_name))
 
 #########################################################################################
@@ -103,7 +92,7 @@ $(sim_files): $(call lookup_srcs,$(base_dir)/generators/utilities/src/main/scala
 $(FIRRTL_FILE) $(ANNO_FILE): generator_temp
 	@echo "" > /dev/null
 
-# AG: must re-elaborate if ariane sources have changed... otherwise just run firrtl compile
+# AG: must re-elaborate if cva6 sources have changed... otherwise just run firrtl compile
 generator_temp: $(SCALA_SOURCES) $(sim_files) $(EXTRA_GENERATOR_REQS)
 	mkdir -p $(build_dir)
 	$(call run_scala_main,$(SBT_PROJECT),$(GENERATOR_PACKAGE).Generator,\
@@ -227,7 +216,7 @@ ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)
 endif
 
 #######################################
-# Rules for building DRAMSim2 library #
+# Rules for building DRAMSim2 library
 #######################################
 
 dramsim_dir = $(base_dir)/tools/DRAMSim2
@@ -236,6 +225,23 @@ dramsim_lib = $(dramsim_dir)/libdramsim.a
 $(dramsim_lib):
 	$(MAKE) -C $(dramsim_dir) $(notdir $@)
 
+################################################
+# Helper to run SBT or manage the SBT server
+################################################
+
+SBT_COMMAND ?= shell
+.PHONY: launch-sbt
+launch-sbt:
+	cd $(base_dir) && $(SBT_NON_THIN) "$(SBT_COMMAND)"
+
+.PHONY: shutdown-sbt-server
+shutdown-sbt-server:
+	cd $(base_dir) && $(SBT) "shutdown"
+
+.PHONY: start-sbt-server
+start-sbt-server:
+	cd $(base_dir) && $(SBT) "exit"
+
 #########################################################################################
 # print help text
 #########################################################################################

docs/Chipyard-Basics/Chipyard-Components.rst

@@ -20,9 +20,9 @@ Processor Cores
   An out-of-order RISC-V core.
   See :ref:`Berkeley Out-of-Order Machine (BOOM)` for more information.
 
-**Ariane Core**
+**CVA6 Core**
-  An in-order RISC-V core written in System Verilog.
+  An in-order RISC-V core written in System Verilog. Previously called Ariane.
-  See :ref:`Ariane Core` for more information.
+  See :ref:`CVA6 Core` for more information.
 
 Accelerators
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

docs/Customization/Custom-Core.rst

@@ -296,6 +296,6 @@ Now you have finished all the steps to prepare your cores for Chipyard! To gener
 in :ref:`custom_chisel` to add your project to the build system, then create a config by following the steps in :ref:`hetero_socs_`.
 You can now run most desired workflows for the new config just as you would for the built-in cores (depending on the functionality your core supports).
 
-If you would like to see an example of a complete third-party Verilog core integrated into Chipyard, ``generators/ariane/src/main/scala/ArianeTile.scala``
+If you would like to see an example of a complete third-party Verilog core integrated into Chipyard, ``generators/ariane/src/main/scala/CVA6Tile.scala``
-provides a concrete example of the Ariane core. Note that this particular example includes additional nuances with respect to the interaction of the AXI
+provides a concrete example of the CVA6 core. Note that this particular example includes additional nuances with respect to the interaction of the AXI
 interface with the memory coherency system.

docs/Generators/CVA6.rst

@@ -1,14 +1,14 @@
-Ariane Core
+CVA6 Core
 ====================================
 
-`Ariane <https://github.com/pulp-platform/ariane>`__ is a 6-stage in-order scalar processor core, originally developed at ETH-Zurich by F. Zaruba and L. Benini.
+`CVA6 <https://github.com/openhwgroup/cva6>`__ (previously called Ariane) is a 6-stage in-order scalar processor core, originally developed at ETH-Zurich by F. Zaruba and L. Benini.
-The `Ariane core` is wrapped in an `Ariane tile` so it can be used as a component within the `Rocket Chip SoC generator`.
+The `CVA6 core` is wrapped in an `CVA6 tile` so it can be used as a component within the `Rocket Chip SoC generator`.
 The core by itself exposes an AXI interface, interrupt ports, and other misc. ports that are connected from within the tile to TileLink buses and other parameterization signals.
 
 .. Warning:: Since the core uses an AXI interface to connect to memory, it is highly recommended to use the core in a single-core setup (since AXI is a non-coherent memory interface).
 
-While the core itself is not a generator, we expose the same parameterization that the Ariane core provides (i.e. change branch prediction parameters).
+While the core itself is not a generator, we expose the same parameterization that the CVA6 core provides (i.e. change branch prediction parameters).
 
 .. Warning::  This target does not support Verilator simulation at this time. Please use VCS.
 
-For more information, please refer to the `GitHub repository <https://github.com/pulp-platform/ariane>`__.
+For more information, please refer to the `GitHub repository <https://github.com/openhwgroup/cva6>`__.

docs/Generators/index.rst

@@ -27,7 +27,7 @@ so changes to the generators themselves will automatically be used when building
    TestChipIP
    SiFive-Generators
    SHA3
-   Ariane
+   CVA6
    NVDLA
    Sodor
 

generators/chipyard/src/main/scala/ConfigFragments.scala

@@ -1,5 +1,6 @@
 package chipyard.config
 
+import scala.util.matching.Regex
 import chisel3._
 import chisel3.util.{log2Up}
 
@@ -11,6 +12,7 @@ import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, D
 import freechips.rocketchip.groundtest.{GroundTestSubsystem}
 import freechips.rocketchip.tile._
 import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams}
+import freechips.rocketchip.tilelink.{HasTLBusParams}
 import freechips.rocketchip.util.{AsyncResetReg, Symmetric}
 import freechips.rocketchip.prci._
 
@@ -21,7 +23,7 @@ import hwacha.{Hwacha}
 import gemmini.{Gemmini, GemminiConfigs}
 
 import boom.common.{BoomTileAttachParams}
-import ariane.{ArianeTileAttachParams}
+import cva6.{CVA6TileAttachParams}
 
 import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.uart._
@@ -120,7 +122,7 @@ class WithTraceIO extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       trace = true))
-    case tp: ArianeTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+    case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       trace = true))
     case other => other
   }
@@ -149,6 +151,11 @@ class WithRocketDCacheScratchpad extends Config((site, here, up) => {
   }
 })
 
+// Replaces the L2 with a broadcast manager for maintaining coherence
+class WithBroadcastManager extends Config((site, here, up) => {
+  case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = CoherenceManagerWrapper.broadcastManager)
+})
+
 class WithHwachaTest extends Config((site, here, up) => {
   case TestSuitesKey => (tileParams: Seq[TileParams], suiteHelper: TestSuiteHelper, p: Parameters) => {
     up(TestSuitesKey).apply(tileParams, suiteHelper, p)
@@ -192,6 +199,34 @@ class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => {
   case DefaultClockFrequencyKey => (site(PeripheryBusKey).dtsFrequency.get / (1000 * 1000)).toDouble
 })
 
+class WithSystemBusFrequencyAsDefault extends Config((site, here, up) => {
+  case DefaultClockFrequencyKey => (site(SystemBusKey).dtsFrequency.get / (1000 * 1000)).toDouble
+})
+
+class BusFrequencyAssignment[T <: HasTLBusParams](re: Regex, key: Field[T]) extends Config((site, here, up) => {
+  case ClockFrequencyAssignersKey => up(ClockFrequencyAssignersKey, site) ++
+    Seq((cName: String) => site(key).dtsFrequency.flatMap { f =>
+      re.findFirstIn(cName).map {_ => (f / (1000 * 1000)).toDouble }
+    })
+})
+
+/**
+  * Provides a diplomatic frequency for all clock sinks with an unspecified
+  * frequency bound to each bus.
+  *
+  * For example, the L2 cache, when bound to the sbus, receives a separate
+  * clock that appears as "subsystem_sbus_<num>".  This fragment ensures that
+  * clock requests the same frequency as the sbus itself.
+  */
+
+class WithInheritBusFrequencyAssignments extends Config(
+  new BusFrequencyAssignment("subsystem_sbus_\\d+".r, SystemBusKey) ++
+  new BusFrequencyAssignment("subsystem_pbus_\\d+".r, PeripheryBusKey) ++
+  new BusFrequencyAssignment("subsystem_cbus_\\d+".r, ControlBusKey) ++
+  new BusFrequencyAssignment("subsystem_fbus_\\d+".r, FrontBusKey) ++
+  new BusFrequencyAssignment("subsystem_mbus_\\d+".r, MemoryBusKey)
+)
+
 /**
   * Mixins to specify crossing types between the 5 traditional TL buses
   *
@@ -221,16 +256,19 @@ class WithFbusToSbusCrossingType(xType: ClockCrossingType) extends Config((site,
   * up the diplomatic graph to the clock sources.
   */
 class WithPeripheryBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
-  case PeripheryBusKey => up(PeripheryBusKey).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
+  case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
 })
 class WithMemoryBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
-  case MemoryBusKey => up(MemoryBusKey).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
+  case MemoryBusKey => up(MemoryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
 })
 class WithSystemBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
-  case SystemBusKey => up(SystemBusKey).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
+  case SystemBusKey => up(SystemBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
+})
+class WithFrontBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
+  case FrontBusKey => up(FrontBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
 })
 class WithControlBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
-  case ControlBusKey => up(ControlBusKey).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
+  case ControlBusKey => up(ControlBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
 })
 
 class WithRationalMemoryBusCrossing extends WithSbusToMbusCrossingType(RationalCrossing(Symmetric))

generators/chipyard/src/main/scala/CustomBusTopologies.scala

@@ -13,14 +13,6 @@ import freechips.rocketchip.subsystem._
 
 // For subsystem/BusTopology.scala
 
-/**
-  * Keys that serve as a means to define crossing types from a Parameters instance
-  */
-case object SbusToMbusXTypeKey extends Field[ClockCrossingType](NoCrossing)
-case object SbusToCbusXTypeKey extends Field[ClockCrossingType](NoCrossing)
-case object CbusToPbusXTypeKey extends Field[ClockCrossingType](SynchronousCrossing())
-case object FbusToSbusXTypeKey extends Field[ClockCrossingType](SynchronousCrossing())
-
 // Biancolin: This, modified from Henry's email
 /** Parameterization of a topology containing a banked coherence manager and a bus for attaching memory devices. */
 case class CoherentMulticlockBusTopologyParams(
@@ -36,17 +28,35 @@ case class CoherentMulticlockBusTopologyParams(
     (SBUS, L2,   TLBusWrapperConnection(xType = NoCrossing, driveClockFromMaster = Some(true), nodeBinding = BIND_STAR)()),
     (L2,  MBUS,  TLBusWrapperConnection.crossTo(
       xType = sbusToMbusXType,
-      driveClockFromMaster = Some(true),
+      driveClockFromMaster = None,
       nodeBinding = BIND_QUERY))
   )
 )
 
+// This differs from upstream only in that it does not use the legacy crossTo
+// and crossFrom functions, and it ensures driveClockFromMaster = None
+case class HierarchicalMulticlockBusTopologyParams(
+  pbus: PeripheryBusParams,
+  fbus: FrontBusParams,
+  cbus: PeripheryBusParams,
+  xTypes: SubsystemCrossingParams
+) extends TLBusWrapperTopology(
+  instantiations = List(
+    (PBUS, pbus),
+    (FBUS, fbus),
+    (CBUS, cbus)),
+  connections = List(
+    (SBUS, CBUS, TLBusWrapperConnection.  crossTo(xType = xTypes.sbusToCbusXType, driveClockFromMaster = None)),
+    (CBUS, PBUS, TLBusWrapperConnection.  crossTo(xType = xTypes.cbusToPbusXType, driveClockFromMaster = None)),
+    (FBUS, SBUS, TLBusWrapperConnection.crossFrom(xType = xTypes.fbusToSbusXType, driveClockFromMaster = None)))
+)
+
 // For subsystem/Configs.scala
 
 class WithMulticlockCoherentBusTopology extends Config((site, here, up) => {
   case TLNetworkTopologyLocated(InSubsystem) => List(
     JustOneBusTopologyParams(sbus = site(SystemBusKey)),
-    HierarchicalBusTopologyParams(
+    HierarchicalMulticlockBusTopologyParams(
       pbus = site(PeripheryBusKey),
       fbus = site(FrontBusKey),
       cbus = site(ControlBusKey),

generators/chipyard/src/main/scala/Subsystem.scala

@@ -56,6 +56,23 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
     case b: BoomTile => b.module.core.coreMonitorBundle
   }.toList
 
+
+  // Relying on [[TLBusWrapperConnection]].driveClockFromMaster for
+  // bus-couplings that are not asynchronous strips the bus name from the sink
+  // ClockGroup. This makes it impossible to determine which clocks are driven
+  // by which bus based on the member names, which is problematic when there is
+  // a rational crossing between two buses. Instead, provide all bus clocks
+  // directly from the asyncClockGroupsNode in the subsystem to ensure bus
+  // names are always preserved in the top-level clock names.
+  //
+  // For example, using a RationalCrossing between the Sbus and Cbus, and
+  // driveClockFromMaster = Some(true) results in all cbus-attached device and
+  // bus clocks to be given names of the form "subsystem_sbus_[0-9]*".
+  // Conversly, if an async crossing is used, they instead receive names of the
+  // form "subsystem_cbus_[0-9]*". The assignment below provides the latter names in all cases.
+  Seq(PBUS, FBUS, MBUS, CBUS).foreach { loc =>
+    tlBusWrapperLocationMap.lift(loc).foreach { _.clockGroupNode := asyncClockGroupsNode }
+  }
   override lazy val module = new ChipyardSubsystemModuleImp(this)
 }
 

generators/chipyard/src/main/scala/TestSuites.scala

@@ -7,9 +7,6 @@ import freechips.rocketchip.tile.{XLen, TileParams}
 import freechips.rocketchip.config.{Parameters, Field, Config}
 import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite}
 
-import boom.common.{BoomTileAttachParams}
-import ariane.{ArianeTileAttachParams}
-
 /**
  * A set of pre-chosen regression tests
  */

generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala

@@ -1,30 +0,0 @@
-
-package chipyard.clocking
-
-import chisel3._
-
-import freechips.rocketchip.config.{Parameters}
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.prci._
-import freechips.rocketchip.util.{ResetCatchAndSync}
-
-/**
-  * Instantiates a reset synchronizer on all clock-reset pairs in a clock group
-  */
-class ClockGroupResetSynchronizer(implicit p: Parameters) extends LazyModule {
-  val node = ClockGroupAdapterNode()
-  lazy val module = new LazyRawModuleImp(this) {
-    (node.out zip node.in).map { case ((oG, _), (iG, _)) =>
-      (oG.member.data zip iG.member.data).foreach { case (o, i) =>
-        o.clock := i.clock
-        o.reset := ResetCatchAndSync(i.clock, i.reset.asBool)
-      }
-    }
-  }
-}
-
-object ClockGroupResetSynchronizer {
-  def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupResetSynchronizer()).node
-}
-
-

generators/chipyard/src/main/scala/config/AbstractConfig.scala

@@ -43,7 +43,8 @@ class AbstractConfig extends Config(
   new chipyard.config.WithUART ++                                // add a UART
   new chipyard.config.WithL2TLBs(1024) ++                        // use L2 TLBs
   new chipyard.config.WithNoSubsystemDrivenClocks ++             // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks
-  new chipyard.config.WithPeripheryBusFrequencyAsDefault ++      // Unspecified clocks will match the frequency specified by the pbus dtsFrequency parameter
+  new chipyard.config.WithInheritBusFrequencyAssignments ++      // Unspecified clocks within a bus will receive the bus frequency if set
+  new chipyard.config.WithPeripheryBusFrequencyAsDefault ++      // Unspecified frequencies with match the pbus frequency (which is always set)
   new freechips.rocketchip.subsystem.WithJtagDTM ++              // set the debug module to expose a JTAG port
   new freechips.rocketchip.subsystem.WithNoMMIOPort ++           // no top-level MMIO master port (overrides default set in rocketchip)
   new freechips.rocketchip.subsystem.WithNoSlavePort ++          // no top-level MMIO slave port (overrides default set in rocketchip)

generators/chipyard/src/main/scala/config/ArianeConfigs.scala

@@ -1,19 +0,0 @@
-package chipyard
-
-import chisel3._
-
-import freechips.rocketchip.config.{Config}
-
-// ---------------------
-// Ariane Configs
-// ---------------------
-
-class ArianeConfig extends Config(
-  new ariane.WithNArianeCores(1) ++                    // single Ariane core
-  new chipyard.config.AbstractConfig)
-
-class dmiArianeConfig extends Config(
-  new chipyard.harness.WithSerialAdapterTiedOff ++     // Tie off the serial port, override default instantiation of SimSerial
-  new chipyard.config.WithDMIDTM ++                    // have debug module expose a clocked DMI port
-  new ariane.WithNArianeCores(1) ++                    // single Ariane core
-  new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/CVA6Configs.scala

@@ -0,0 +1,19 @@
+package chipyard
+
+import chisel3._
+
+import freechips.rocketchip.config.{Config}
+
+// ---------------------
+// CVA6 Configs
+// ---------------------
+
+class CVA6Config extends Config(
+  new cva6.WithNCVA6Cores(1) ++                    // single CVA6 core
+  new chipyard.config.AbstractConfig)
+
+class dmiCVA6Config extends Config(
+  new chipyard.harness.WithSerialAdapterTiedOff ++ // Tie off the serial port, override default instantiation of SimSerial
+  new chipyard.config.WithDMIDTM ++                // have debug module expose a clocked DMI port
+  new cva6.WithNCVA6Cores(1) ++                    // single CVA6 core
+  new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -1,6 +1,7 @@
 package chipyard
 
 import freechips.rocketchip.config.{Config}
+import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
 
 // --------------
 // Rocket Configs
@@ -185,13 +186,19 @@ class MMIORocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
-class DividedClockRocketConfig extends Config(
+class MulticlockRocketConfig extends Config(
-  new chipyard.config.WithTileFrequency(200.0) ++
-  new freechips.rocketchip.subsystem.WithRationalRocketTiles ++   // Add rational crossings between RocketTile and uncore
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new chipyard.config.WithMemoryBusFrequency(50.0) ++
+  // Frequency specifications
-  new chipyard.config.WithAsynchrousMemoryBusCrossing ++
+  new chipyard.config.WithTileFrequency(1600.0) ++       // Matches the maximum frequency of U540 
-  new testchipip.WithAsynchronousSerialSlaveCrossing ++
+  new chipyard.config.WithSystemBusFrequency(800.0) ++   // Ditto
+  new chipyard.config.WithMemoryBusFrequency(1000.0) ++  // 2x the U540 freq (appropriate for a 128b Mbus)
+  new chipyard.config.WithPeripheryBusFrequency(100) ++  // Retains the default pbus frequency
+  new chipyard.config.WithSystemBusFrequencyAsDefault ++ // All unspecified clock frequencies, notably the implicit clock, will use the sbus freq (800 MHz)
+  //  Crossing specifications
+  new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS
+  new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS
+  new freechips.rocketchip.subsystem.WithRationalRocketTiles ++   // Add rational crossings between RocketTile and uncore
+  new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS
   new chipyard.config.AbstractConfig)
 
 class LBWIFRocketConfig extends Config(

generators/chipyard/src/main/scala/example/NodeTypes.scala

@@ -11,7 +11,7 @@ import testchipip.TLHelper
 
 // DOC include start: MyClient
 class MyClient(implicit p: Parameters) extends LazyModule {
-  val node = TLHelper.makeClientNode(TLClientParameters(
+  val node = TLHelper.makeClientNode(TLMasterParameters.v1(
     name = "my-client",
     sourceId = IdRange(0, 4),
     requestFifo = true,
@@ -29,7 +29,7 @@ class MyClient(implicit p: Parameters) extends LazyModule {
 class MyManager(implicit p: Parameters) extends LazyModule {
   val device = new SimpleDevice("my-device", Seq("tutorial,my-device0"))
   val beatBytes = 8
-  val node = TLHelper.makeManagerNode(beatBytes, TLManagerParameters(
+  val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1(
     address = Seq(AddressSet(0x20000, 0xfff)),
     resources = device.reg,
     regionType = RegionType.UNCACHED,
@@ -83,7 +83,7 @@ class MyClientGroup(implicit p: Parameters) extends LazyModule {
 
 // DOC include start: MyManagerGroup
 class MyManager1(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
-  val node = TLHelper.makeManagerNode(beatBytes, TLManagerParameters(
+  val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1(
     address = Seq(AddressSet(0x0, 0xfff))))
 
   lazy val module = new LazyModuleImp(this) {
@@ -92,7 +92,7 @@ class MyManager1(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
 }
 
 class MyManager2(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
-  val node = TLHelper.makeManagerNode(beatBytes, TLManagerParameters(
+  val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1(
     address = Seq(AddressSet(0x1000, 0xfff))))
 
   lazy val module = new LazyModuleImp(this) {

generators/chipyard/src/main/scala/example/TutorialTile.scala

@@ -15,8 +15,9 @@ import freechips.rocketchip.interrupts._
 import freechips.rocketchip.util._
 import freechips.rocketchip.tile._
 import freechips.rocketchip.amba.axi4._
+import freechips.rocketchip.prci.ClockSinkParameters
 
-// Example parameter class copied from Ariane, not included in documentation but for compile check only
+// Example parameter class copied from CVA6, not included in documentation but for compile check only
 // If you are here for documentation, DO NOT copy MyCoreParams and MyTileParams directly - always figure
 // out what parameters you need before you write the parameter class
 case class MyCoreParams(
@@ -39,16 +40,20 @@ case class MyCoreParams(
   val mulDiv: Option[MulDivParams] = Some(MulDivParams()) // copied from Rocket
   val fpu: Option[FPUParams] = Some(FPUParams()) // copied fma latencies from Rocket
   val nLocalInterrupts: Int = 0
+  val useNMI: Boolean = false
   val nPMPs: Int = 0 // TODO: Check
   val pmpGranularity: Int = 4 // copied from Rocket
   val nBreakpoints: Int = 0 // TODO: Check
   val useBPWatch: Boolean = false
+  val mcontextWidth: Int = 0
+  val scontextWidth: Int = 0
   val nPerfCounters: Int = 29
   val haveBasicCounters: Boolean = true
   val haveFSDirty: Boolean = false
   val misaWritable: Boolean = false
   val haveCFlush: Boolean = false
   val nL2TLBEntries: Int = 512 // copied from Rocket
+  val nL2TLBWays: Int = 1
   val mtvecInit: Option[BigInt] = Some(BigInt(0)) // copied from Rocket
   val mtvecWritable: Boolean = true // copied from Rocket
   val instBits: Int = if (useCompressed) 16 else 32
@@ -81,6 +86,7 @@ case class MyTileParams(
   val boundaryBuffers: Boolean = false
   val dcache: Option[DCacheParams] = Some(DCacheParams())
   val icache: Option[ICacheParams] = Some(ICacheParams())
+  val clockSinkParams: ClockSinkParameters = ClockSinkParameters()
   def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): MyTile = {
     new MyTile(this, crossing, lookup)
   }
@@ -164,7 +170,7 @@ class MyTileModuleImp(outer: MyTile) extends BaseTileModuleImp(outer){
   //   val core = Module(new MyCoreBlackbox(params...))
   // (as described in the blackbox tutorial) and connect appropriate signals. See the blackbox tutorial
   // (link on the top of the page) for more info.
-  // You can look at https://github.com/ucb-bar/ariane-wrapper/blob/master/src/main/scala/ArianeTile.scala
+  // You can look at https://github.com/ucb-bar/cva6-wrapper/blob/master/src/main/scala/CVA6Tile.scala
   // for a Verilog example.
 
   // If your core is in Chisel, you can simply instantiate the top module here like other Chisel module

generators/firechip/src/main/scala/BridgeBinders.scala

@@ -4,12 +4,13 @@ package firesim.firesim
 
 import chisel3._
 import chisel3.experimental.annotate
+import chisel3.util.experimental.BoringUtils
 
 import freechips.rocketchip.config.{Field, Config, Parameters}
 import freechips.rocketchip.diplomacy.{LazyModule}
 import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp}
 import freechips.rocketchip.amba.axi4.{AXI4Bundle}
-import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem, HasTilesModuleImp, ExtMem}
+import freechips.rocketchip.subsystem._
 import freechips.rocketchip.tile.{RocketTile}
 import sifive.blocks.devices.uart._
 
@@ -22,7 +23,7 @@ import midas.targetutils.{MemModelAnnotation, EnableModelMultiThreadingAnnotatio
 import firesim.bridges._
 import firesim.configs.MemModelKey
 import tracegen.{TraceGenSystemModuleImp}
-import ariane.ArianeTile
+import cva6.CVA6Tile
 
 import boom.common.{BoomTile}
 import barstools.iocell.chisel._
@@ -86,7 +87,12 @@ class WithNICBridge extends OverrideHarnessBinder({
 
 class WithUARTBridge extends OverrideHarnessBinder({
   (system: HasPeripheryUARTModuleImp, th: FireSim, ports: Seq[UARTPortIO]) =>
-    ports.map { p => UARTBridge(th.harnessClock, p)(system.p) }; Nil
+    val uartSyncClock = Wire(Clock())
+    uartSyncClock := false.B.asClock
+    val pbusClockNode = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(PBUS).fixedClockNode
+    val pbusClock = pbusClockNode.in.head._1.clock
+    BoringUtils.bore(pbusClock, Seq(uartSyncClock))
+    ports.map { p => UARTBridge(uartSyncClock, p)(system.p) }; Nil
 })
 
 class WithBlockDeviceBridge extends OverrideHarnessBinder({

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -188,21 +188,19 @@ class SupernodeFireSimRocketConfig extends Config(
   new FireSimRocketConfig)
 
 //**********************************************************************************
-//* Ariane Configurations
+//* CVA6 Configurations
 //*********************************************************************************/
-class FireSimArianeConfig extends Config(
+class FireSimCVA6Config extends Config(
   new WithDefaultFireSimBridges ++
   new WithDefaultMemModel ++
   new WithFireSimConfigTweaks ++
-  new chipyard.ArianeConfig)
+  new chipyard.CVA6Config)
 
 //**********************************************************************************
 //* Multiclock Configurations
 //*********************************************************************************/
 class FireSimMulticlockRocketConfig extends Config(
   new chipyard.config.WithTileFrequency(6400.0) ++ //lol
-  new WithDefaultFireSimBridges ++
+  new freechips.rocketchip.subsystem.WithRationalRocketTiles ++   // Add rational crossings between RocketTile and uncore
-  new WithDefaultMemModel ++
+  new FireSimRocketConfig)
-  new WithFireSimConfigTweaks ++
-  new chipyard.DividedClockRocketConfig)
 

generators/firechip/src/test/scala/ScalaTestSuite.scala

@@ -42,10 +42,9 @@ abstract class FireSimTestSuite(
   }
 
   def runTest(backend: String, name: String, debug: Boolean, additionalArgs: Seq[String] = Nil) = {
-    behavior of s"${name} running on ${backend} in MIDAS-level simulation"
     compileMlSimulator(backend, debug)
     if (isCmdAvailable(backend)) {
-      it should s"pass" in {
+      it should s"pass in ML simulation on ${backend}" in {
         assert(invokeMlSimulator(backend, name, debug, additionalArgs) == 0)
       }
     }
@@ -59,13 +58,15 @@ abstract class FireSimTestSuite(
         case _: BenchmarkTestSuite | _: BlockdevTestSuite | _: NICTestSuite => ".riscv"
         case _ => ""
       }
-      val results = suite.names.toSeq sliding (N, N) map { t =>
+      it should s"pass all tests in ${suite.makeTargetName}" in {
-        val subresults = t map (name =>
+        val results = suite.names.toSeq sliding (N, N) map { t =>
-          Future(name -> invokeMlSimulator(backend, s"$name$postfix", debug)))
+          val subresults = t map (name =>
-        Await result (Future sequence subresults, Duration.Inf)
+            Future(name -> invokeMlSimulator(backend, s"$name$postfix", debug)))
-      }
+          Await result (Future sequence subresults, Duration.Inf)
-      results.flatten foreach { case (name, exitcode) =>
+        }
-        it should s"pass $name" in { assert(exitcode == 0) }
+        results.flatten foreach { case (name, exitcode) =>
+          assert(exitcode == 0, "Failed $name")
+        }
       }
     } else {
       ignore should s"pass $backend"
@@ -96,7 +97,9 @@ abstract class FireSimTestSuite(
     }
   }
 
-  clean
+  mkdirs
+  behavior of s"Tuple: ${targetTuple}"
+  elaborateAndCompile()
   runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-humanreadable0"""))
   runSuite("verilator")(benchmarks)
 }
@@ -110,7 +113,7 @@ class RocketMulticlockF1Tests extends FireSimTestSuite(
   "FireSimMulticlockRocketConfig",
   "WithSynthAsserts_BaseF1Config")
 
-class ArianeF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig", "BaseF1Config")
+class CVA6F1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimCVA6Config", "BaseF1Config")
 
 // This test suite only mirrors what is run in CI. CI invokes each test individually, using a testOnly call.
 class CITests extends Suites(

generators/tracegen/src/main/scala/Tile.scala

@@ -13,6 +13,7 @@ import freechips.rocketchip.interrupts._
 import freechips.rocketchip.subsystem._
 import boom.lsu.{BoomNonBlockingDCache, LSU, LSUCoreIO}
 import boom.common.{BoomTileParams, MicroOp, BoomCoreParams, BoomModule}
+import freechips.rocketchip.prci.ClockSinkParameters
 
 
 class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p)
@@ -190,6 +191,7 @@ case class BoomTraceGenParams(
   val blockerCtrlAddr = None
   val name = None
   val traceParams = TraceGenParams(wordBits, addrBits, addrBag, maxRequests, memStart, numGens, dcache, hartId)
+  val clockSinkParams: ClockSinkParameters = ClockSinkParameters()
 }
 
 class BoomTraceGenTile private(

project/build.properties

@@ -1 +1 @@
-sbt.version=1.3.2
+sbt.version=1.4.4

project/plugins.sbt

@@ -1,20 +1,15 @@
-resolvers += Resolver.url("scalasbt", new URL("https://scalasbt.artifactoryonline.com/scalasbt/sbt-plugin-releases")) (Resolver.ivyStylePatterns)
-resolvers += Classpaths.sbtPluginReleases
-resolvers += "jgit-repo" at "https://download.eclipse.org/jgit/maven"
-
 addSbtPlugin("net.virtual-void" % "sbt-dependency-graph" % "0.9.2")
 addSbtPlugin("com.typesafe.sbt" % "sbt-ghpages" % "0.6.2")
 addSbtPlugin("com.typesafe.sbt" % "sbt-site" % "1.3.1")
-addSbtPlugin("com.eed3si9n" % "sbt-buildinfo" % "0.7.0")
+addSbtPlugin("com.eed3si9n" % "sbt-buildinfo" % "0.10.0")
 addSbtPlugin("org.xerial.sbt" % "sbt-pack" % "0.9.3")
 addSbtPlugin("com.eed3si9n" % "sbt-unidoc" % "0.4.1")
 addSbtPlugin("org.scoverage" % "sbt-scoverage" % "1.5.1")
 addSbtPlugin("org.scalastyle" %% "scalastyle-sbt-plugin" % "1.0.0")
-addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.14.6")
+addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.15.0")
-addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.1")
+addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.2")
 addSbtPlugin("com.github.gseitz" % "sbt-protobuf" % "0.6.3")
-addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.4")
+addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.21")
 addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "0.6.1")
-addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.1")
+addSbtPlugin("com.eed3si9n" % "sbt-sriracha" % "0.1.0")
-
+addSbtPlugin("org.scalameta" % "sbt-mdoc" % "2.2.5" )
-libraryDependencies += "com.github.os72" % "protoc-jar" % "3.5.1.1"

scripts/build-toolchains.sh

@@ -20,6 +20,7 @@ usage() {
     echo "Options"
     echo "   --prefix PREFIX : Install destination. If unset, defaults to $(pwd)/riscv-tools-install"
     echo "                     or $(pwd)/esp-tools-install"
+    echo "   --ignore-qemu   : Ignore installing QEMU"
     echo "   --help -h       : Display this message"
     exit "$1"
 }
@@ -34,6 +35,7 @@ die() {
 
 TOOLCHAIN="riscv-tools"
 EC2FASTINSTALL="false"
+IGNOREQEMU=""
 RISCV=""
 
 # getopts does not support long options, and is inflexible
@@ -45,6 +47,9 @@ do
         -p | --prefix )
             shift
             RISCV=$(realpath $1) ;;
+        --ignore-qemu )
+            shift
+            IGNOREQEMU="true" ;;
         riscv-tools | esp-tools)
             TOOLCHAIN=$1 ;;
         ec2fast )
@@ -102,12 +107,16 @@ if [ "${EC2FASTINSTALL}" = true ] ; then
     git submodule deinit "${module}" || :
 
 else
-    "${MAKE}" --version | (
+    MAKE_VER=$("${MAKE}" --version) || true
-        read -r makever
+    case ${MAKE_VER} in
-        case ${makever} in
+        'GNU Make '[4-9]\.*)
-        'GNU Make '[4-9]\.*|'GNU Make '[1-9][0-9]) ;;
+            ;;
-        *) false ;;
+        'GNU Make '[1-9][0-9])
-        esac; ) || die 'obsolete make version; need GNU make 4.x or later'
+            ;;
+        *)
+            die 'obsolete make version; need GNU make 4.x or later'
+            ;;
+    esac
 
     module_prepare riscv-gnu-toolchain qemu
     module_build riscv-gnu-toolchain --prefix="${RISCV}" --with-cmodel=medany
@@ -128,7 +137,9 @@ module_all riscv-tests --prefix="${RISCV}/riscv64-unknown-elf"
 
 SRCDIR="$(pwd)/toolchains" module_all libgloss --prefix="${RISCV}/riscv64-unknown-elf" --host=riscv64-unknown-elf
 
+if [ -z "$IGNOREQEMU" ] ; then
 SRCDIR="$(pwd)/toolchains" module_all qemu --prefix="${RISCV}" --target-list=riscv64-softmmu
+fi
 
 # make Dromajo
 git submodule update --init $CHIPYARD_DIR/tools/dromajo/dromajo-src

scripts/init-submodules-no-riscv-tools-nolog.sh

@@ -11,7 +11,7 @@ case ${MYGIT} in
 [1-9]*) ;;
 *) echo 'warning: unknown git version' ;;
 esac
-MINGIT="1.7.8"
+MINGIT="1.8.5"
 if [ "$MINGIT" != "$(echo -e "$MINGIT\n$MYGIT" | sort -V | head -n1)" ]; then
   echo "This script requires git version $MINGIT or greater. Exiting."
   false

scripts/tutorial-patches/build.sbt.patch

@@ -1,26 +1,30 @@
 diff --git a/build.sbt b/build.sbt
-index 5d642c1..56f6fda 100644
+index e80b2a5..b1989d9 100644
 --- a/build.sbt
 +++ b/build.sbt
-@@ -130,7 +130,7 @@ lazy val iocell = (project in file("./tools/barstools/iocell/"))
+@@ -184,7 +184,7 @@ lazy val testchipipLib = "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHO
- 
+ lazy val chipyard = (project in file("generators/chipyard"))
- lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard"))
+   .sourceDependency(testchipip, testchipipLib)
-   .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell,
+   .dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell,
 -    sha3, // On separate line to allow for cleaner tutorial-setup patches
 +//    sha3, // On separate line to allow for cleaner tutorial-setup patches
      dsptools, `rocket-dsptools`,
-     gemmini, icenet, tracegen, ariane, nvdla, sodor)
+     gemmini, icenet, tracegen, cva6, nvdla, sodor)
-   .settings(commonSettings)
+   .settings(libraryDependencies ++= rocketLibDeps.value)
-@@ -158,9 +158,9 @@ lazy val ariane = (project in file("generators/ariane"))
+@@ -227,11 +227,11 @@ lazy val sodor = (project in file("generators/riscv-sodor"))
-   .dependsOn(rocketchip)
+   .settings(libraryDependencies ++= rocketLibDeps.value)
    .settings(commonSettings)
  
 -lazy val sha3 = (project in file("generators/sha3"))
 -  .dependsOn(rocketchip, chisel_testers, midasTargetUtils)
+-  .settings(libraryDependencies ++= rocketLibDeps.value)
+-  .settings(libraryDependencies ++= chiselTestersLibDeps.value)
 -  .settings(commonSettings)
 +//lazy val sha3 = (project in file("generators/sha3"))
 +//  .dependsOn(rocketchip, chisel_testers, midasTargetUtils)
++//  .settings(libraryDependencies ++= rocketLibDeps.value)
++//  .settings(libraryDependencies ++= chiselTestersLibDeps.value)
 +//  .settings(commonSettings)
  
  lazy val gemmini = (project in file("generators/gemmini"))
-   .dependsOn(rocketchip, chisel_testers, testchipip)
+   .sourceDependency(testchipip, testchipipLib)

sims/verilator/Makefile

@@ -84,14 +84,14 @@ TRACING_CFLAGS := $(if $(filter $(VERILATOR_FST_MODE),0),,-DCY_FST_TRACE)
 #----------------------------------------------------------------------------------------
 # we initially had --noassert for performance, but several modules use
 # assertions, including dramsim, so we enable --assert by default
-VERILATOR_OPT_FLAGS := \
+VERILATOR_OPT_FLAGS ?= \
 	-O3 \
 	--x-assign fast \
 	--x-initial fast \
 	--output-split 10000 \
 	--output-split-cfuncs 100
 
-# default flags added for external IP (ariane/NVDLA)
+# default flags added for external IP (cva6/NVDLA)
 VERILOG_IP_VERILATOR_FLAGS := \
 	--unroll-count 256 \
 	-Wno-PINCONNECTEMPTY \
@@ -103,14 +103,14 @@ VERILOG_IP_VERILATOR_FLAGS := \
 	-Wno-style \
 	-Wall
 
-# normal flags used for chipyard builds (that are incompatible with vlog ip aka ariane/NVDLA)
+# normal flags used for chipyard builds (that are incompatible with vlog ip aka cva6/NVDLA)
 CHIPYARD_VERILATOR_FLAGS := \
 	--assert
 
-# options dependent on whether external IP (ariane/NVDLA) or just chipyard is used
+# options dependent on whether external IP (cva6/NVDLA) or just chipyard is used
 # NOTE: defer the evaluation of this until it is used!
 PLATFORM_OPTS = $(shell \
-	if grep -qiP "module\s+(Ariane|NVDLA)" $(build_dir)/*.*v; \
+	if grep -qiP "module\s+(CVA6|NVDLA)" $(build_dir)/*.*v; \
 	then echo "$(VERILOG_IP_VERILATOR_FLAGS)"; \
 	else echo "$(CHIPYARD_VERILATOR_FLAGS)"; fi)
 

variables.mk

@@ -146,40 +146,31 @@ sim_common_files       ?= $(build_dir)/sim_files.common.f
 # java arguments used in sbt
 #########################################################################################
 JAVA_HEAP_SIZE ?= 8G
-JAVA_ARGS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M
+JAVA_OPTS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M
 
 #########################################################################################
 # default sbt launch command
 #########################################################################################
-SCALA_VERSION=2.12.10
+# by default build chisel3/firrtl and other subprojects from source
-SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION))
+override SBT_OPTS += -Dsbt.sourcemode=true -Dsbt.workspace=$(base_dir)/tools
-SBT ?= java $(JAVA_ARGS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar
-
-BLOOP ?= bloop
-BLOOP_CONFIG_DIR ?= $(base_dir)/.bloop
-# This mirrors the bloop default. Set to a system-unique port in a multi-user environment
-BLOOP_NAILGUN_PORT ?= 8212
 
 SCALA_BUILDTOOL_DEPS = $(SBT_SOURCES)
 
-ifdef ENABLE_BLOOP
+SBT_THIN_CLIENT_TIMESTAMP = $(base_dir)/project/target/active.json
-override SCALA_BUILDTOOL_DEPS += $(BLOOP_CONFIG_DIR)/TIMESTAMP
+
-# Two notes about the bloop invocation:
+ifdef ENABLE_SBT_THIN_CLIENT
-# 1) the sed removes a leading {file:<path>} that sometimes needs to be
+override SCALA_BUILDTOOL_DEPS += $(SBT_THIN_CLIENT_TIMESTAMP)
-#    provided to SBT when a project but not for bloop.
+# enabling speeds up sbt loading
-# 2) Generally, one could could pass '--' to indicate all remaining arguments are
+SBT_CLIENT_FLAG = --client
-#    destined for the scala Main, however a bug in Bloop's argument parsing causes the
-#    --nailgun-port argument to be lost in this case. Workaround this by prefixing
-#    every main-destined argument with "--args"
-define run_scala_main
-	cd $(base_dir) && bloop --nailgun-port $(BLOOP_NAILGUN_PORT) run $(shell echo $(1) | sed 's/{.*}//') --main $(2)  $(addprefix --args ,$3)
-endef
-else
-define run_scala_main
-	cd $(base_dir) && $(SBT) "project $(1)" "runMain $(2) $(3)"
-endef
 endif
 
+SBT ?= java $(JAVA_OPTS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar $(SBT_OPTS) $(SBT_CLIENT_FLAG)
+SBT_NON_THIN ?= $(subst $(SBT_CLIENT_FLAG),,$(SBT))
+
+define run_scala_main
+	cd $(base_dir) && $(SBT) ";project $(1); runMain $(2) $(3)"
+endef
+
 FIRRTL_LOGLEVEL ?= error
 
 #########################################################################################

vlsi/Makefile

@@ -25,9 +25,15 @@ tech_dir           ?= $(if $(filter $(tech_name),asap7 nangate45),\
 SMEMS_COMP         ?= $(tech_dir)/sram-compiler.json
 SMEMS_CACHE        ?= $(tech_dir)/sram-cache.json
 SMEMS_HAMMER       ?= $(build_dir)/$(long_name).mems.hammer.json
-MACROCOMPILER_MODE ?= $(if $(filter $(tech_name),asap7),\
+
-                        --mode synflops,\
+ifeq ($(tech_name),asap7)
-                        -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict)
+	MACROCOMPILER_MODE ?= --mode synflops
+else ifdef USE_SRAM_COMPILER
+	MACROCOMPILER_MODE ?= -l $(SMEMS_COMP) --use-compiler -hir $(SMEMS_HAMMER) --mode strict
+else
+	MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict
+endif	
+
 ENV_YML            ?= $(vlsi_dir)/env.yml
 INPUT_CONFS        ?= $(if $(filter $(tech_name),nangate45),\
                         example-nangate45.yml,\