From 16c34e2cf3044152e231d4dbe2f8ba69b4fee740 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 4 Nov 2020 11:46:02 -0800 Subject: [PATCH 01/83] Bump Dromajo for old glibc --- tools/dromajo/dromajo-src | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/dromajo/dromajo-src b/tools/dromajo/dromajo-src index 56e2ff46..09fbef45 160000 --- a/tools/dromajo/dromajo-src +++ b/tools/dromajo/dromajo-src @@ -1 +1 @@ -Subproject commit 56e2ff46b70521916c362799517f4ed8e67e9e88 +Subproject commit 09fbef4565429f641a7eb93f190ad0e45e11d7f8 From 5e3d1a605d787b7bd02a2361ababd4954c7a7656 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 4 Nov 2020 11:57:23 -0800 Subject: [PATCH 02/83] Add --ignore-qemu flag to toolchains | Prepare QEMU when it builds --- scripts/build-toolchains.sh | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 2685872e..9ceb8808 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -20,6 +20,7 @@ usage() { echo "Options" echo " --prefix PREFIX : Install destination. If unset, defaults to $(pwd)/riscv-tools-install" echo " or $(pwd)/esp-tools-install" + echo " --ignore-qemu : Ignore installing QEMU" echo " --help -h : Display this message" exit "$1" } @@ -34,6 +35,7 @@ die() { TOOLCHAIN="riscv-tools" EC2FASTINSTALL="false" +IGNOREQEMU="false" RISCV="" # getopts does not support long options, and is inflexible @@ -45,6 +47,9 @@ do -p | --prefix ) shift RISCV=$(realpath $1) ;; + --ignore-qemu ) + shift + IGNOREQEMU="true" ;; riscv-tools | esp-tools) TOOLCHAIN=$1 ;; ec2fast ) @@ -109,7 +114,7 @@ else *) false ;; esac; ) || die 'obsolete make version; need GNU make 4.x or later' - module_prepare riscv-gnu-toolchain qemu + module_prepare riscv-gnu-toolchain module_build riscv-gnu-toolchain --prefix="${RISCV}" --with-cmodel=medany echo '==> Building GNU/Linux toolchain' module_make riscv-gnu-toolchain linux @@ -128,7 +133,9 @@ module_all riscv-tests --prefix="${RISCV}/riscv64-unknown-elf" SRCDIR="$(pwd)/toolchains" module_all libgloss --prefix="${RISCV}/riscv64-unknown-elf" --host=riscv64-unknown-elf +if [ "${IGNOREQEMU}" = false ] ; then SRCDIR="$(pwd)/toolchains" module_all qemu --prefix="${RISCV}" --target-list=riscv64-softmmu +fi # make Dromajo git submodule update --init $CHIPYARD_DIR/tools/dromajo/dromajo-src From a2ebbee2ac21d2703995b67daea8a18cc6713271 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 4 Nov 2020 15:05:11 -0800 Subject: [PATCH 03/83] Rename Ariane to CVA6 --- .circleci/check-commit.sh | 2 +- .circleci/config.yml | 6 +- .circleci/defaults.sh | 4 +- .circleci/run-tests.sh | 2 +- .gitmodules | 6 +- README.md | 6 +- build.sbt | 4 +- common.mk | 4 +- docs/Chipyard-Basics/Chipyard-Components.rst | 4 +- docs/Customization/Custom-Core.rst | 70 +++++++++---------- docs/Generators/{Ariane.rst => CVA6.rst} | 10 +-- docs/Generators/index.rst | 2 +- generators/ariane | 1 - .../src/main/scala/ConfigFragments.scala | 4 +- .../chipyard/src/main/scala/TestSuites.scala | 3 - .../src/main/scala/config/ArianeConfigs.scala | 19 ----- .../src/main/scala/config/CVA6Configs.scala | 19 +++++ .../src/main/scala/example/TutorialTile.scala | 14 ++-- generators/cva6 | 1 + .../src/main/scala/BridgeBinders.scala | 2 +- .../src/main/scala/TargetConfigs.scala | 8 +-- .../src/test/scala/ScalaTestSuite.scala | 2 +- scripts/tutorial-patches/build.sbt.patch | 10 +-- sims/firesim | 2 +- sims/verilator/Makefile | 8 +-- 25 files changed, 105 insertions(+), 108 deletions(-) rename docs/Generators/{Ariane.rst => CVA6.rst} (59%) delete mode 160000 generators/ariane delete mode 100644 generators/chipyard/src/main/scala/config/ArianeConfigs.scala create mode 100644 generators/chipyard/src/main/scala/config/CVA6Configs.scala create mode 160000 generators/cva6 diff --git a/.circleci/check-commit.sh b/.circleci/check-commit.sh index 68cc975c..2660fa49 100755 --- a/.circleci/check-commit.sh +++ b/.circleci/check-commit.sh @@ -48,7 +48,7 @@ search () { done } -submodules=("ariane" "boom" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor") +submodules=("cva6" "boom" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor") dir="generators" if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] then diff --git a/.circleci/config.yml b/.circleci/config.yml index 4ee84ced..6e74b9d5 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -234,12 +234,12 @@ jobs: - run-tests: group-key: "group-cores" project-key: "chipyard-boom" - chipyard-ariane-run-tests: + chipyard-cva6-run-tests: executor: main-env steps: - run-tests: group-key: "group-cores" - project-key: "chipyard-ariane" + project-key: "chipyard-cva6" timeout: "30m" chipyard-sodor-run-tests: executor: main-env @@ -431,7 +431,7 @@ workflows: - chipyard-boom-run-tests: requires: - prepare-chipyard-cores - - chipyard-ariane-run-tests: + - chipyard-cva6-run-tests: requires: - prepare-chipyard-cores - chipyard-sodor-run-tests: diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index e628de7b..c0bce62d 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -47,7 +47,7 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim # key value store to get the build groups declare -A grouping -grouping["group-cores"]="chipyard-ariane chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop" +grouping["group-cores"]="chipyard-cva6 chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop" grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spiflashread chipyard-spiflashwrite chipyard-mmios chipyard-lbwif" grouping["group-accels"]="chipyard-nvdla chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough" grouping["group-tracegen"]="tracegen tracegen-boom" @@ -67,7 +67,7 @@ mapping["chipyard-boom"]=" CONFIG=SmallBoomConfig" mapping["chipyard-blkdev"]=" CONFIG=SimBlockDeviceRocketConfig" mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig" mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig" -mapping["chipyard-ariane"]=" CONFIG=ArianeConfig" +mapping["chipyard-cva6"]=" CONFIG=CVA6Config" mapping["chipyard-spiflashread"]=" CONFIG=LargeSPIFlashROMRocketConfig" mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig" mapping["chipyard-mmios"]=" CONFIG=MMIORocketConfig verilog" diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index da5029b5..5ea53c78 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -91,7 +91,7 @@ case $1 in tracegen-boom) run_tracegen ${mapping[$1]} ;; - chipyard-ariane) + chipyard-cva6) make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/multiply.riscv ;; chipyard-sodor) diff --git a/.gitmodules b/.gitmodules index f374fa1f..d9dbe85f 100644 --- a/.gitmodules +++ b/.gitmodules @@ -113,9 +113,9 @@ [submodule "software/firemarshal"] path = software/firemarshal url = https://github.com/firesim/FireMarshal.git -[submodule "generators/ariane"] - path = generators/ariane - url = https://github.com/ucb-bar/ariane-wrapper.git +[submodule "generators/cva6"] + path = generators/cva6 + url = git@github.com:ucb-bar/cva6-wrapper.git [submodule "tools/DRAMSim2"] path = tools/DRAMSim2 url = https://github.com/firesim/DRAMSim2.git diff --git a/README.md b/README.md index ab542cf3..11f1b8d5 100644 --- a/README.md +++ b/README.md @@ -10,7 +10,7 @@ To get started using Chipyard, see the documentation on the Chipyard documentati Chipyard is an open source framework for agile development of Chisel-based systems-on-chip. It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators. -Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [Ariane][ariane]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC. +Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [CVA6][cva6]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC. Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation ([FireSim][firesim]), automated VLSI flows ([Hammer][hammer]), and software workload generation for bare-metal and Linux-based systems ([FireMarshal][firemarshal]). Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley]. @@ -35,7 +35,7 @@ If used for research, please cite Chipyard by the following publication: ``` @article{chipyard, - author={Amid, Alon and Biancolin, David and Gonzalez, Abraham and Grubb, Daniel and Karandikar, Sagar and Liew, Harrison and Magyar, Albert and Mao, Howard and Ou, Albert and Pemberton, Nathan and Rigge, Paul and Schmidt, Colin and Wright, John and Zhao, Jerry and Shao, Yakun Sophia and Asanovi\'{c}, Krste and Nikoli\'{c}, Borivoje}, + author={Amid, Alon and Biancolin, David and Gonzalez, Abraham and Grubb, Daniel and Karandikar, Sagar and Liew, Harrison and Magyar, Albert and Mao, Howard and Ou, Albert and Pemberton, Nathan and Rigge, Paul and Schmidt, Colin and Wright, John and Zhao, Jerry and Shao, Yakun Sophia and Asanovi\'{c}, Krste and Nikoli\'{c}, Borivoje}, journal={IEEE Micro}, title={Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs}, year={2020}, @@ -80,6 +80,6 @@ These additional publications cover many of the internal components used in Chip [rocket-chip]: https://github.com/freechipsproject/rocket-chip [boom]: https://github.com/riscv-boom/riscv-boom [firemarshal]: https://github.com/firesim/FireMarshal/ -[ariane]: https://github.com/pulp-platform/ariane/ +[cva6]: https://github.com/openhwgroup/cva6/ [gemmini]: https://github.com/ucb-bar/gemmini [nvdla]: http://nvdla.org/ diff --git a/build.sbt b/build.sbt index 750878ab..bbf7964f 100644 --- a/build.sbt +++ b/build.sbt @@ -132,7 +132,7 @@ lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsptools`, - gemmini, icenet, tracegen, ariane, nvdla, sodor) + gemmini, icenet, tracegen, cva6, nvdla, sodor) .settings(commonSettings) lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen")) @@ -154,7 +154,7 @@ lazy val boom = conditionalDependsOn(project in file("generators/boom")) .dependsOn(rocketchip) .settings(commonSettings) -lazy val ariane = (project in file("generators/ariane")) +lazy val cva6 = (project in file("generators/cva6")) .dependsOn(rocketchip) .settings(commonSettings) diff --git a/common.mk b/common.mk index 8ebc262c..ca34ffce 100644 --- a/common.mk +++ b/common.mk @@ -47,7 +47,7 @@ HELP_COMMANDS += \ # include additional subproject make fragments # see HELP_COMPILATION_VARIABLES ######################################################################################### -include $(base_dir)/generators/ariane/ariane.mk +include $(base_dir)/generators/cva6/cva6.mk include $(base_dir)/generators/tracegen/tracegen.mk include $(base_dir)/generators/nvdla/nvdla.mk include $(base_dir)/tools/dromajo/dromajo.mk @@ -103,7 +103,7 @@ $(sim_files): $(call lookup_srcs,$(base_dir)/generators/utilities/src/main/scala $(FIRRTL_FILE) $(ANNO_FILE): generator_temp @echo "" > /dev/null -# AG: must re-elaborate if ariane sources have changed... otherwise just run firrtl compile +# AG: must re-elaborate if cva6 sources have changed... otherwise just run firrtl compile generator_temp: $(SCALA_SOURCES) $(sim_files) $(EXTRA_GENERATOR_REQS) mkdir -p $(build_dir) $(call run_scala_main,$(SBT_PROJECT),$(GENERATOR_PACKAGE).Generator,\ diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index c24f81ed..4ad39d51 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -20,9 +20,9 @@ Processor Cores An out-of-order RISC-V core. See :ref:`Berkeley Out-of-Order Machine (BOOM)` for more information. -**Ariane Core** +**CVA6 Core** An in-order RISC-V core written in System Verilog. - See :ref:`Ariane Core` for more information. + See :ref:`CVA6 Core` for more information. Accelerators ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/docs/Customization/Custom-Core.rst b/docs/Customization/Custom-Core.rst index a76741ec..6da84cb7 100644 --- a/docs/Customization/Custom-Core.rst +++ b/docs/Customization/Custom-Core.rst @@ -6,14 +6,14 @@ Adding a custom core You may want to integrate a custom RISC-V core into the Chipyard framework. This documentation page provides step-by-step instructions on how to achieve this. -.. note:: +.. note:: RoCC is currently not supported by cores other than Rocket and BOOM. Please use Rocket or BOOM as the RoCC base core if you need to use RoCC. .. note:: - This page contains links to the files that contains important definitions in the Rocket chip repository, which is maintained separately - from Chipyard. If you find any discrepancy between the code on this page and the code in the source file, please report it through + This page contains links to the files that contains important definitions in the Rocket chip repository, which is maintained separately + from Chipyard. If you find any discrepancy between the code on this page and the code in the source file, please report it through GitHub issues! Wrap Verilog Module with Blackbox (Optional) @@ -30,15 +30,15 @@ This object is derived from``TileParams``, a trait containing the information ne their own implementation of ``InstantiableTileParams``, as well as ``CoreParams`` which is passed as a field in ``TileParams``. ``TileParams`` holds the parameters for the tile, which include parameters for all components in the tile (e.g. -core, cache, MMU, etc.), while ``CoreParams`` contains parameters specific to the core on the tile. -They must be implemented as case classes with fields that can be overridden by -other config fragments as the constructor parameters. See the appendix at the bottom of the page for a list of -variable to be implemented. You can also add custom fields to them, but standard fields should always be preferred. +core, cache, MMU, etc.), while ``CoreParams`` contains parameters specific to the core on the tile. +They must be implemented as case classes with fields that can be overridden by +other config fragments as the constructor parameters. See the appendix at the bottom of the page for a list of +variable to be implemented. You can also add custom fields to them, but standard fields should always be preferred. -``InstantiableTileParams[TileType]`` holds the constructor of ``TileType`` on top of the fields of ``TileParams``, +``InstantiableTileParams[TileType]`` holds the constructor of ``TileType`` on top of the fields of ``TileParams``, where ``TileType`` is the tile class (see the next section). All custom cores will also need to implement ``instantiate()`` in their tile parameter class to return a new instance -of the tile class ``TileType``. +of the tile class ``TileType``. ``TileParams`` (in the file `BaseTile.scala `_) , ``InstantiableTileParams`` (in the file `BaseTile.scala `_), @@ -88,7 +88,7 @@ contains the following fields: val nBreakpoints: Int // # of hardware breakpoints supported (in RISC-V debug specs) val useBPWatch: Boolean // Support hardware breakpoints val nPerfCounters: Int // # of supported performance counters - val haveBasicCounters: Boolean // Support basic counters defined in the RISC-V counter extension + val haveBasicCounters: Boolean // Support basic counters defined in the RISC-V counter extension val haveFSDirty: Boolean // If true, the core will set FS field in mstatus CSR to dirty when appropriate val misaWritable: Boolean // Support writable misa CSR (like variable instruction bits) val haveCFlush: Boolean // Rocket specific: enables Rocket's custom instruction extension to flush the cache @@ -96,7 +96,7 @@ contains the following fields: val mtvecInit: Option[BigInt] // mtvec CSR (of V extension) initial value val mtvecWritable: Boolean // If mtvec CSR is writable - // Normally, you don't need to change these values (except lrscCycles) + // Normally, you don't need to change these values (except lrscCycles) def customCSRs(implicit p: Parameters): CustomCSRs = new CustomCSRs def hasSupervisorMode: Boolean = useSupervisor || useVM @@ -113,19 +113,19 @@ contains the following fields: def eLen(xLen: Int, fLen: Int): Int = xLen max fLen def vMemDataBits: Int = 0 } - + case class FPUParams( - minFLen: Int = 32, // Minimum floating point length (no need to change) + minFLen: Int = 32, // Minimum floating point length (no need to change) fLen: Int = 64, // Maximum floating point length, use 32 if only single precision is supported divSqrt: Boolean = true, // Div/Sqrt operation supported sfmaLatency: Int = 3, // Rocket specific: Fused multiply-add pipeline latency (single precision) dfmaLatency: Int = 4 // Rocket specific: Fused multiply-add pipeline latency (double precision) ) -Most of the fields here (marked "Rocket spcific") are originally designed for the Rocket core and thus contain some -implementation-specific details, but many of them are general enough to be useful for other cores. You may ignore +Most of the fields here (marked "Rocket spcific") are originally designed for the Rocket core and thus contain some +implementation-specific details, but many of them are general enough to be useful for other cores. You may ignore any fields marked "Rocket specific" and use their default values; however, if you need to store additional information -with meaning or usage similar to these "Rocket specific" fields, it is recommended to use these fields instead of +with meaning or usage similar to these "Rocket specific" fields, it is recommended to use these fields instead of creating your own custom fields. You will also need a ``CanAttachTile`` class to add the tile config into the config system, with the following format: @@ -144,14 +144,14 @@ from the parameters in this class for every such class it found. value may break Chipyard components that rely on them (e.g. an inaccurate indication of supported ISA extension will result in an incorrect test suite being generated) as well as any custom modules that use them. ALWAYS document any fields you ignore or with altered usage in your core implementation, and if you are implementing other devices that - would look up these config values, also document them. "Rocket specific" values are generally safe to ignore, but + would look up these config values, also document them. "Rocket specific" values are generally safe to ignore, but you should document them if you use them. Create Tile Class ----------------- In Chipyard, all Tiles are diplomatically instantiated. In the first phase, diplomatic nodes which specify Tile-to-System -interconnects are evaluated, while in the second "Module Implementation" phase, hardware is elaborated. +interconnects are evaluated, while in the second "Module Implementation" phase, hardware is elaborated. See :ref:`tilelink_and_diplomacy` for more details. In this step, you will need to implement a tile class for your core, which specifies the constraints on the core's parameters and the connections with other diplomatic nodes. This class usually contains Diplomacy/TileLink code only, and Chisel RTL code should not go here. @@ -167,10 +167,10 @@ which allow the tile to accept external interrupt. A typical tile has the follow Connect TileLink Buses ---------------------- -Chipyard uses TileLink as its onboard bus protocol. If your core doesn't use TileLink, you will need to insert converters +Chipyard uses TileLink as its onboard bus protocol. If your core doesn't use TileLink, you will need to insert converters between the core's memory protocol and TileLink within the Tile module. in the tile class. Below is an example of how to connect a core using AXI4 to the TileLink bus with converters provided by -Rocket chip: +Rocket chip: .. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala :language: scala @@ -179,11 +179,11 @@ Rocket chip: Remember, you may not need all of these intermediate widgets. See :ref:`diplomatic_widgets` for the meaning of each intermediate widget. If you are using TileLink, then you only need the tap node and the TileLink node used by your components. Chipyard also -provides converters for AHB, APB and AXIS, and most of the AXI4 widgets has equivalent widget for these bus protocol; see the -source files in ``generators/rocket-chip/src/main/scala/amba`` for more info. +provides converters for AHB, APB and AXIS, and most of the AXI4 widgets has equivalent widget for these bus protocol; see the +source files in ``generators/rocket-chip/src/main/scala/amba`` for more info. If you are using some other bus protocol, you may implement your own converters, using the files in ``generators/rocket-chip/src/main/scala/amba`` -as the template, but it is not recommended unless you are familiar with TileLink. +as the template, but it is not recommended unless you are familiar with TileLink. ``memAXI4Node`` is an AXI4 master node and is defined as following in our example: @@ -215,7 +215,7 @@ The implementation class contains the parameterized, actual hardware that depend framework according to the info provided in the Tile class. This class will normally contains Chisel RTL code. If your core is in Verilog, you will need to instantiate the black box class that wraps your Verilog implementation and connect it with the buses and other components. No Diplomacy/TileLink code should be in this class; you should only connect the IO signals in TileLink -interfaces or other diplomatically defined components, which are located in the tile class. +interfaces or other diplomatically defined components, which are located in the tile class. The implementation class for your core is of the following form: @@ -234,12 +234,12 @@ If you create an AXI4 node (or equivalents), you will need to connect them to yo Connect Interrupt ----------------- -Chipyard allows a tile to either receive interrupts from other devices or initiate interrupts to notify other cores/devices. -In the tile that inherited ``SinksExternalInterrupts``, one can create a ``TileInterrupts`` object (a Chisel bundle) and +Chipyard allows a tile to either receive interrupts from other devices or initiate interrupts to notify other cores/devices. +In the tile that inherited ``SinksExternalInterrupts``, one can create a ``TileInterrupts`` object (a Chisel bundle) and call ``decodeCoreInterrupts()`` with the object as the argument. Note that you should call this function in the implementation class since it returns a Chisel bundle used by RTL code. You can then read the interrupt bits from the ``TileInterrupts`` bundle -we create above. The definition of ``TileInterrupts`` -(in the file `Interrupts.scala `_) is +we create above. The definition of ``TileInterrupts`` +(in the file `Interrupts.scala `_) is .. code-block:: scala @@ -247,7 +247,7 @@ we create above. The definition of ``TileInterrupts`` val debug = Bool() // debug interrupt val mtip = Bool() // Machine level timer interrupt val msip = Bool() // Machine level software interrupt - val meip = Bool() // Machine level external interrupt + val meip = Bool() // Machine level external interrupt val seip = usingSupervisor.option(Bool()) // Valid only if supervisor mode is supported val lip = Vec(coreParams.nLocalInterrupts, Bool()) // Local interrupts } @@ -261,7 +261,7 @@ Here is an example on how to connect these signals in the implementation class: Also, the tile can also notify other cores or devices for some events by calling following functions in ``SourcesExternalNotifications`` from the implementation class: -(These functions can be found in in the trait ``SourcesExternalNotifications`` in the file +(These functions can be found in in the trait ``SourcesExternalNotifications`` in the file `Interrupts.scala `_) .. code-block:: scala @@ -290,12 +290,12 @@ the current config. An example of such config will be like this: :end-before: DOC include end: Config fragment Chipyard looks up the tile parameters in the field ``TilesLocated(InSubsystem)``, whose type is a list of ``InstantiableTileParams``. -This config fragment simply appends new tile parameters to the end of this list. +This config fragment simply appends new tile parameters to the end of this list. Now you have finished all the steps to prepare your cores for Chipyard! To generate the custom core, simply follow the instructions in :ref:`custom_chisel` to add your project to the build system, then create a config by following the steps in :ref:`hetero_socs_`. -You can now run most desired workflows for the new config just as you would for the built-in cores (depending on the functionality your core supports). +You can now run most desired workflows for the new config just as you would for the built-in cores (depending on the functionality your core supports). -If you would like to see an example of a complete third-party Verilog core integrated into Chipyard, ``generators/ariane/src/main/scala/ArianeTile.scala`` -provides a concrete example of the Ariane core. Note that this particular example includes additional nuances with respect to the interaction of the AXI -interface with the memory coherency system. +If you would like to see an example of a complete third-party Verilog core integrated into Chipyard, ``generators/ariane/src/main/scala/CVA6Tile.scala`` +provides a concrete example of the CVA6 core. Note that this particular example includes additional nuances with respect to the interaction of the AXI +interface with the memory coherency system. diff --git a/docs/Generators/Ariane.rst b/docs/Generators/CVA6.rst similarity index 59% rename from docs/Generators/Ariane.rst rename to docs/Generators/CVA6.rst index e58f9dfc..6250c614 100644 --- a/docs/Generators/Ariane.rst +++ b/docs/Generators/CVA6.rst @@ -1,14 +1,14 @@ -Ariane Core +CVA6 Core ==================================== -`Ariane `__ is a 6-stage in-order scalar processor core, originally developed at ETH-Zurich by F. Zaruba and L. Benini. -The `Ariane core` is wrapped in an `Ariane tile` so it can be used as a component within the `Rocket Chip SoC generator`. +`CVA6 `__ is a 6-stage in-order scalar processor core, originally developed at ETH-Zurich by F. Zaruba and L. Benini. +The `CVA6 core` is wrapped in an `CVA6 tile` so it can be used as a component within the `Rocket Chip SoC generator`. The core by itself exposes an AXI interface, interrupt ports, and other misc. ports that are connected from within the tile to TileLink buses and other parameterization signals. .. Warning:: Since the core uses an AXI interface to connect to memory, it is highly recommended to use the core in a single-core setup (since AXI is a non-coherent memory interface). -While the core itself is not a generator, we expose the same parameterization that the Ariane core provides (i.e. change branch prediction parameters). +While the core itself is not a generator, we expose the same parameterization that the CVA6 core provides (i.e. change branch prediction parameters). .. Warning:: This target does not support Verilator simulation at this time. Please use VCS. -For more information, please refer to the `GitHub repository `__. +For more information, please refer to the `GitHub repository `__. diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index cebb17e5..cfc7d601 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -27,7 +27,7 @@ so changes to the generators themselves will automatically be used when building TestChipIP SiFive-Generators SHA3 - Ariane + CVA6 NVDLA Sodor diff --git a/generators/ariane b/generators/ariane deleted file mode 160000 index 3a2eed60..00000000 --- a/generators/ariane +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 3a2eed602faac24e58a530db429f23f11810aae9 diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 68c41724..0db4ed4c 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -21,7 +21,7 @@ import hwacha.{Hwacha} import gemmini.{Gemmini, GemminiConfigs} import boom.common.{BoomTileAttachParams} -import ariane.{ArianeTileAttachParams} +import cva6.{CVA6TileAttachParams} import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ @@ -120,7 +120,7 @@ class WithTraceIO extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( trace = true)) - case tp: ArianeTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy( trace = true)) case other => other } diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala index 8cdfd3c9..596337c0 100644 --- a/generators/chipyard/src/main/scala/TestSuites.scala +++ b/generators/chipyard/src/main/scala/TestSuites.scala @@ -7,9 +7,6 @@ import freechips.rocketchip.tile.{XLen, TileParams} import freechips.rocketchip.config.{Parameters, Field, Config} import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite} -import boom.common.{BoomTileAttachParams} -import ariane.{ArianeTileAttachParams} - /** * A set of pre-chosen regression tests */ diff --git a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala deleted file mode 100644 index 6e75ac54..00000000 --- a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala +++ /dev/null @@ -1,19 +0,0 @@ -package chipyard - -import chisel3._ - -import freechips.rocketchip.config.{Config} - -// --------------------- -// Ariane Configs -// --------------------- - -class ArianeConfig extends Config( - new ariane.WithNArianeCores(1) ++ // single Ariane core - new chipyard.config.AbstractConfig) - -class dmiArianeConfig extends Config( - new chipyard.harness.WithSerialAdapterTiedOff ++ // Tie off the serial port, override default instantiation of SimSerial - new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port - new ariane.WithNArianeCores(1) ++ // single Ariane core - new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/CVA6Configs.scala b/generators/chipyard/src/main/scala/config/CVA6Configs.scala new file mode 100644 index 00000000..132a3009 --- /dev/null +++ b/generators/chipyard/src/main/scala/config/CVA6Configs.scala @@ -0,0 +1,19 @@ +package chipyard + +import chisel3._ + +import freechips.rocketchip.config.{Config} + +// --------------------- +// CVA6 Configs +// --------------------- + +class CVA6Config extends Config( + new cva6.WithNCVA6Cores(1) ++ // single CVA6 core + new chipyard.config.AbstractConfig) + +class dmiCVA6Config extends Config( + new chipyard.harness.WithSerialAdapterTiedOff ++ // Tie off the serial port, override default instantiation of SimSerial + new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port + new cva6.WithNCVA6Cores(1) ++ // single CVA6 core + new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala index 1f58e5e4..9af2cb54 100644 --- a/generators/chipyard/src/main/scala/example/TutorialTile.scala +++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala @@ -16,7 +16,7 @@ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.amba.axi4._ -// Example parameter class copied from Ariane, not included in documentation but for compile check only +// Example parameter class copied from CVA6, not included in documentation but for compile check only // If you are here for documentation, DO NOT copy MyCoreParams and MyTileParams directly - always figure // out what parameters you need before you write the parameter class case class MyCoreParams( @@ -127,9 +127,9 @@ class MyTile( // TODO: Create TileLink nodes and connections here. // DOC include end: Tile class - + // DOC include start: AXI4 node - // # of bits used in TileLink ID for master node. 4 bits can support 16 master nodes, but you can have a longer ID if you need more. + // # of bits used in TileLink ID for master node. 4 bits can support 16 master nodes, but you can have a longer ID if you need more. val idBits = 4 val memAXI4Node = AXI4MasterNode( Seq(AXI4MasterPortParameters( @@ -160,17 +160,17 @@ class MyTileModuleImp(outer: MyTile) extends BaseTileModuleImp(outer){ // TODO: Create the top module of the core and connect it with the ports in "outer" - // If your core is in Verilog (assume your blackbox is called "MyCoreBlackbox"), instantiate it here like - // val core = Module(new MyCoreBlackbox(params...)) + // If your core is in Verilog (assume your blackbox is called "MyCoreBlackbox"), instantiate it here like + // val core = Module(new MyCoreBlackbox(params...)) // (as described in the blackbox tutorial) and connect appropriate signals. See the blackbox tutorial // (link on the top of the page) for more info. - // You can look at https://github.com/ucb-bar/ariane-wrapper/blob/master/src/main/scala/ArianeTile.scala + // You can look at https://github.com/ucb-bar/cva6-wrapper/blob/master/src/main/scala/CVA6Tile.scala // for a Verilog example. // If your core is in Chisel, you can simply instantiate the top module here like other Chisel module // and connect appropriate signal. You can even implement this class as your top module. // See https://github.com/riscv-boom/riscv-boom/blob/master/src/main/scala/common/tile.scala and - // https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/RocketTile.scala for + // https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/RocketTile.scala for // Chisel example. // DOC include end: Implementation class diff --git a/generators/cva6 b/generators/cva6 new file mode 160000 index 00000000..27157f7b --- /dev/null +++ b/generators/cva6 @@ -0,0 +1 @@ +Subproject commit 27157f7bbdd1ebc395fc8e22e46b3118290fa188 diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index e4f691e2..0572fabd 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -22,7 +22,7 @@ import midas.targetutils.{MemModelAnnotation, EnableModelMultiThreadingAnnotatio import firesim.bridges._ import firesim.configs.MemModelKey import tracegen.{TraceGenSystemModuleImp} -import ariane.ArianeTile +import cva6.CVA6Tile import boom.common.{BoomTile} import barstools.iocell.chisel._ diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 719599f4..89ac8073 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -128,7 +128,7 @@ class FireSimQuadRocketConfig extends Config( new chipyard.QuadRocketConfig) // A stripped down configuration that should fit on all supported hosts. -// Flat to avoid having to reorganize the config class hierarchy to remove certain features +// Flat to avoid having to reorganize the config class hierarchy to remove certain features class FireSimSmallSystemConfig extends Config( new WithDefaultFireSimBridges ++ new WithDefaultMemModel ++ @@ -188,13 +188,13 @@ class SupernodeFireSimRocketConfig extends Config( new FireSimRocketConfig) //********************************************************************************** -//* Ariane Configurations +//* CVA6 Configurations //*********************************************************************************/ -class FireSimArianeConfig extends Config( +class FireSimCVA6Config extends Config( new WithDefaultFireSimBridges ++ new WithDefaultMemModel ++ new WithFireSimConfigTweaks ++ - new chipyard.ArianeConfig) + new chipyard.CVA6Config) //********************************************************************************** //* Multiclock Configurations diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index ea1627b7..64b9b4ba 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -110,7 +110,7 @@ class RocketMulticlockF1Tests extends FireSimTestSuite( "FireSimMulticlockRocketConfig", "WithSynthAsserts_BaseF1Config") -class ArianeF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig", "BaseF1Config") +class CVA6F1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimCVA6Config", "BaseF1Config") // This test suite only mirrors what is run in CI. CI invokes each test individually, using a testOnly call. class CITests extends Suites( diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch index aa7f0bd4..cb289b6f 100644 --- a/scripts/tutorial-patches/build.sbt.patch +++ b/scripts/tutorial-patches/build.sbt.patch @@ -3,24 +3,24 @@ index 5d642c1..56f6fda 100644 --- a/build.sbt +++ b/build.sbt @@ -130,7 +130,7 @@ lazy val iocell = (project in file("./tools/barstools/iocell/")) - + lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, - sha3, // On separate line to allow for cleaner tutorial-setup patches +// sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsptools`, - gemmini, icenet, tracegen, ariane, nvdla, sodor) + gemmini, icenet, tracegen, cva6, nvdla, sodor) .settings(commonSettings) -@@ -158,9 +158,9 @@ lazy val ariane = (project in file("generators/ariane")) +@@ -158,9 +158,9 @@ lazy val cva6 = (project in file("generators/cva6")) .dependsOn(rocketchip) .settings(commonSettings) - + -lazy val sha3 = (project in file("generators/sha3")) - .dependsOn(rocketchip, chisel_testers, midasTargetUtils) - .settings(commonSettings) +//lazy val sha3 = (project in file("generators/sha3")) +// .dependsOn(rocketchip, chisel_testers, midasTargetUtils) +// .settings(commonSettings) - + lazy val gemmini = (project in file("generators/gemmini")) .dependsOn(rocketchip, chisel_testers, testchipip) diff --git a/sims/firesim b/sims/firesim index 1c76c446..57efb2ec 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 1c76c446dab42b782f8128c3e7e56b4e9ab104d7 +Subproject commit 57efb2ec032a8c7afa2f458761cc79b2614180b5 diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 211b5676..65e64179 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -91,7 +91,7 @@ VERILATOR_OPT_FLAGS := \ --output-split 10000 \ --output-split-cfuncs 100 -# default flags added for external IP (ariane/NVDLA) +# default flags added for external IP (cva6/NVDLA) VERILOG_IP_VERILATOR_FLAGS := \ --unroll-count 256 \ -Wno-PINCONNECTEMPTY \ @@ -103,14 +103,14 @@ VERILOG_IP_VERILATOR_FLAGS := \ -Wno-style \ -Wall -# normal flags used for chipyard builds (that are incompatible with vlog ip aka ariane/NVDLA) +# normal flags used for chipyard builds (that are incompatible with vlog ip aka cva6/NVDLA) CHIPYARD_VERILATOR_FLAGS := \ --assert -# options dependent on whether external IP (ariane/NVDLA) or just chipyard is used +# options dependent on whether external IP (cva6/NVDLA) or just chipyard is used # NOTE: defer the evaluation of this until it is used! PLATFORM_OPTS = $(shell \ - if grep -qiP "module\s+(Ariane|NVDLA)" $(build_dir)/*.*v; \ + if grep -qiP "module\s+(CVA6|NVDLA)" $(build_dir)/*.*v; \ then echo "$(VERILOG_IP_VERILATOR_FLAGS)"; \ else echo "$(CHIPYARD_VERILATOR_FLAGS)"; fi) From 94eceeb6249f477e2e257eebb8da757d4f5a345b Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 4 Nov 2020 15:54:09 -0800 Subject: [PATCH 04/83] Use empty variable instead of t/f --- scripts/build-toolchains.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 9ceb8808..84fdbd45 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -35,7 +35,7 @@ die() { TOOLCHAIN="riscv-tools" EC2FASTINSTALL="false" -IGNOREQEMU="false" +IGNOREQEMU="" RISCV="" # getopts does not support long options, and is inflexible @@ -133,7 +133,7 @@ module_all riscv-tests --prefix="${RISCV}/riscv64-unknown-elf" SRCDIR="$(pwd)/toolchains" module_all libgloss --prefix="${RISCV}/riscv64-unknown-elf" --host=riscv64-unknown-elf -if [ "${IGNOREQEMU}" = false ] ; then +if [ -z "$IGNOREQEMU" ] ; then SRCDIR="$(pwd)/toolchains" module_all qemu --prefix="${RISCV}" --target-list=riscv64-softmmu fi From fc8c5e4b3019d65fc0ec0040ffdb7477c55daf6a Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 4 Nov 2020 18:02:49 -0800 Subject: [PATCH 05/83] Use HTTPS for submodules --- .gitmodules | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitmodules b/.gitmodules index d9dbe85f..7054c14f 100644 --- a/.gitmodules +++ b/.gitmodules @@ -115,7 +115,7 @@ url = https://github.com/firesim/FireMarshal.git [submodule "generators/cva6"] path = generators/cva6 - url = git@github.com:ucb-bar/cva6-wrapper.git + url = https://github.com/ucb-bar/cva6-wrapper.git [submodule "tools/DRAMSim2"] path = tools/DRAMSim2 url = https://github.com/firesim/DRAMSim2.git From 59c9163bd5ca201b37ff7ed6633755e3811fbb23 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 4 Nov 2020 18:37:26 -0800 Subject: [PATCH 06/83] Bump CVA6 for submodule fixes --- generators/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/cva6 b/generators/cva6 index 27157f7b..3f0513a9 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit 27157f7bbdd1ebc395fc8e22e46b3118290fa188 +Subproject commit 3f0513a9bd9394047c7cc1fbd50ea5077bb2e36c From 9052b41328bcc76da1d6e9718edce4b4e044face Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 4 Nov 2020 20:59:14 -0800 Subject: [PATCH 07/83] Re-ignore QEMU from gnu-toolchain | Avoid piping make version in toolchain build --- scripts/build-toolchains.sh | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 84fdbd45..1897d157 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -107,14 +107,18 @@ if [ "${EC2FASTINSTALL}" = true ] ; then git submodule deinit "${module}" || : else - "${MAKE}" --version | ( - read -r makever - case ${makever} in - 'GNU Make '[4-9]\.*|'GNU Make '[1-9][0-9]) ;; - *) false ;; - esac; ) || die 'obsolete make version; need GNU make 4.x or later' + MAKE_VER=$("${MAKE}" --version) || true + case ${MAKE_VER} in + 'GNU Make '[4-9]\.*) + ;; + 'GNU Make '[1-9][0-9]) + ;; + *) + die 'obsolete make version; need GNU make 4.x or later' + ;; + esac - module_prepare riscv-gnu-toolchain + module_prepare riscv-gnu-toolchain qemu module_build riscv-gnu-toolchain --prefix="${RISCV}" --with-cmodel=medany echo '==> Building GNU/Linux toolchain' module_make riscv-gnu-toolchain linux From 60cd99900264f57a3d075c6fc8ba214136e41c5c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 4 Nov 2020 21:09:24 -0800 Subject: [PATCH 08/83] Bump CVA6 for Make fix --- generators/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/cva6 b/generators/cva6 index 3f0513a9..e3576371 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit 3f0513a9bd9394047c7cc1fbd50ea5077bb2e36c +Subproject commit e35763717b25c08df215b10334fd2d40845e1912 From 0685812c342c31d735472ad13573ce8f21ed3687 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 5 Nov 2020 10:30:00 -0800 Subject: [PATCH 09/83] Bump CVA6 --- generators/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/cva6 b/generators/cva6 index e3576371..8a11e2c9 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit e35763717b25c08df215b10334fd2d40845e1912 +Subproject commit 8a11e2c97627459d0449853447bfc7ca64608b82 From 2de5f7dd7e245ad3f47cbfa69a68b925c38df3af Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 5 Nov 2020 15:48:50 -0800 Subject: [PATCH 10/83] [ci skip] Note that CVA6 was called Ariane in the past --- README.md | 2 +- docs/Chipyard-Basics/Chipyard-Components.rst | 2 +- docs/Generators/CVA6.rst | 2 +- sims/firesim | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/README.md b/README.md index 11f1b8d5..0283da58 100644 --- a/README.md +++ b/README.md @@ -10,7 +10,7 @@ To get started using Chipyard, see the documentation on the Chipyard documentati Chipyard is an open source framework for agile development of Chisel-based systems-on-chip. It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators. -Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [CVA6][cva6]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC. +Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [CVA6 (Ariane)][cva6]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC. Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation ([FireSim][firesim]), automated VLSI flows ([Hammer][hammer]), and software workload generation for bare-metal and Linux-based systems ([FireMarshal][firemarshal]). Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley]. diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index 4ad39d51..398b537d 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -21,7 +21,7 @@ Processor Cores See :ref:`Berkeley Out-of-Order Machine (BOOM)` for more information. **CVA6 Core** - An in-order RISC-V core written in System Verilog. + An in-order RISC-V core written in System Verilog. Previously called Ariane. See :ref:`CVA6 Core` for more information. Accelerators diff --git a/docs/Generators/CVA6.rst b/docs/Generators/CVA6.rst index 6250c614..bfca746a 100644 --- a/docs/Generators/CVA6.rst +++ b/docs/Generators/CVA6.rst @@ -1,7 +1,7 @@ CVA6 Core ==================================== -`CVA6 `__ is a 6-stage in-order scalar processor core, originally developed at ETH-Zurich by F. Zaruba and L. Benini. +`CVA6 `__ (previously called Ariane) is a 6-stage in-order scalar processor core, originally developed at ETH-Zurich by F. Zaruba and L. Benini. The `CVA6 core` is wrapped in an `CVA6 tile` so it can be used as a component within the `Rocket Chip SoC generator`. The core by itself exposes an AXI interface, interrupt ports, and other misc. ports that are connected from within the tile to TileLink buses and other parameterization signals. diff --git a/sims/firesim b/sims/firesim index 57efb2ec..37fe89a6 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 57efb2ec032a8c7afa2f458761cc79b2614180b5 +Subproject commit 37fe89a65f1c1ccd8d2cc0d1efd0c06308d0224d From a559d624df583fa1968ac52ede8cd1bfb22356be Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 7 Nov 2020 18:42:29 -0800 Subject: [PATCH 11/83] [clocking] Drive all buses directly from the asyncClockGroup --- .../src/main/scala/CustomBusTopologies.scala | 22 +++++++++++++++++-- .../chipyard/src/main/scala/Subsystem.scala | 17 ++++++++++++++ 2 files changed, 37 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/CustomBusTopologies.scala b/generators/chipyard/src/main/scala/CustomBusTopologies.scala index c1c09285..db617f83 100644 --- a/generators/chipyard/src/main/scala/CustomBusTopologies.scala +++ b/generators/chipyard/src/main/scala/CustomBusTopologies.scala @@ -36,17 +36,35 @@ case class CoherentMulticlockBusTopologyParams( (SBUS, L2, TLBusWrapperConnection(xType = NoCrossing, driveClockFromMaster = Some(true), nodeBinding = BIND_STAR)()), (L2, MBUS, TLBusWrapperConnection.crossTo( xType = sbusToMbusXType, - driveClockFromMaster = Some(true), + driveClockFromMaster = None, nodeBinding = BIND_QUERY)) ) ) +// This differs from upstream only in that it does not use the legacy crossTo +// and crossFrom functions to ensure driveClockFromMaster = None +case class HierarchicalMulticlockBusTopologyParams( + pbus: PeripheryBusParams, + fbus: FrontBusParams, + cbus: PeripheryBusParams, + xTypes: SubsystemCrossingParams +) extends TLBusWrapperTopology( + instantiations = List( + (PBUS, pbus), + (FBUS, fbus), + (CBUS, cbus)), + connections = List( + (SBUS, CBUS, TLBusWrapperConnection(xType = xTypes.sbusToCbusXType, nodeBinding = BIND_STAR)()), + (CBUS, PBUS, TLBusWrapperConnection(xType = xTypes.cbusToPbusXType, nodeBinding = BIND_STAR)()), + (FBUS, SBUS, TLBusWrapperConnection(xType = xTypes.fbusToSbusXType, nodeBinding = BIND_QUERY, flipRendering = true)())) +) + // For subsystem/Configs.scala class WithMulticlockCoherentBusTopology extends Config((site, here, up) => { case TLNetworkTopologyLocated(InSubsystem) => List( JustOneBusTopologyParams(sbus = site(SystemBusKey)), - HierarchicalBusTopologyParams( + HierarchicalMulticlockBusTopologyParams( pbus = site(PeripheryBusKey), fbus = site(FrontBusKey), cbus = site(ControlBusKey), diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 5dd6ac18..40b8cc8c 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -56,6 +56,23 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem case b: BoomTile => b.module.core.coreMonitorBundle }.toList + + // Relying on [[TLBusWrapperConnection]].driveClockFromMaster for + // bus-couplings that are not asynchronous strips the bus name from the sink + // ClockGroup. This makes it impossible to determine which clocks are driven + // by which bus based on the member names, which is problematic when there is + // a rational crossing between two buses. Instead, provide all bus clocks + // directly from the asyncClockGroupsNode in the subsystem to ensure bus + // names are always preserved in the top-level clock names. + // + // For example, using a RationalCrossing between the Sbus and Cbus, and + // driveClockFromMaster = Some(true) results in all cbus-attached device and + // bus clocks to be given names of the form "subsystem_sbus_[0-9]*". + // Conversly, if an async crossing is used, they instead receive names of the + // form "subsystem_cbus_[0-9]*". The assignment below the latter names in all cases. + Seq(PBUS, FBUS, MBUS, CBUS).foreach { loc => + tlBusWrapperLocationMap.lift(loc).foreach { _.clockGroupNode := asyncClockGroupsNode } + } override lazy val module = new ChipyardSubsystemModuleImp(this) } From 04cd6b59bdb9aff69164dc894a4704c7eabe4c36 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 7 Nov 2020 18:45:48 -0800 Subject: [PATCH 12/83] [clocking] Add a fragment to set bus clock-sink freqs more intuitively --- .../src/main/scala/ConfigFragments.scala | 30 +++++++++++++++++++ .../chipyard/src/main/scala/Subsystem.scala | 2 +- 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 0db4ed4c..fb706895 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -1,5 +1,6 @@ package chipyard.config +import scala.util.matching.Regex import chisel3._ import chisel3.util.{log2Up} @@ -11,6 +12,7 @@ import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, D import freechips.rocketchip.groundtest.{GroundTestSubsystem} import freechips.rocketchip.tile._ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams} +import freechips.rocketchip.tilelink.{HasTLBusParams} import freechips.rocketchip.util.{AsyncResetReg, Symmetric} import freechips.rocketchip.prci._ @@ -183,6 +185,34 @@ class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => { case DefaultClockFrequencyKey => (site(PeripheryBusKey).dtsFrequency.get / (1000 * 1000)).toDouble }) +class WithSystemBusFrequencyAsDefault extends Config((site, here, up) => { + case DefaultClockFrequencyKey => (site(SystemBusKey).dtsFrequency.get / (1000 * 1000)).toDouble +}) + +class BusFrequencyAssignment[T <: HasTLBusParams](re: Regex, key: Field[T]) extends Config((site, here, up) => { + case ClockFrequencyAssignersKey => up(ClockFrequencyAssignersKey, site) ++ + Seq((cName: String) => site(key).dtsFrequency.flatMap { f => + re.findFirstIn(cName).map {_ => (f / (1000 * 1000)).toDouble } + }) +}) + +/** + * Provides a diplomatic frequency for all clock sinks with an unspecified + * frequency bound to each bus. + * + * For example, the L2 cache, when bound to the sbus, receives a separate + * clock that appears as "subsystem_sbus_". This fragment ensures that + * clock requests the same frequency as the sbus itself. + */ + +class WithInheritBusFrequencyAssignments extends Config( + new BusFrequencyAssignment("subsystem_sbus_\\d+".r, SystemBusKey) ++ + new BusFrequencyAssignment("subsystem_pbus_\\d+".r, PeripheryBusKey) ++ + new BusFrequencyAssignment("subsystem_cbus_\\d+".r, ControlBusKey) ++ + new BusFrequencyAssignment("subsystem_fbus_\\d+".r, FrontBusKey) ++ + new BusFrequencyAssignment("subsystem_mbus_\\d+".r, MemoryBusKey) +) + /** * Mixins to specify crossing types between the 5 traditional TL buses * diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 40b8cc8c..09e35d95 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -69,7 +69,7 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem // driveClockFromMaster = Some(true) results in all cbus-attached device and // bus clocks to be given names of the form "subsystem_sbus_[0-9]*". // Conversly, if an async crossing is used, they instead receive names of the - // form "subsystem_cbus_[0-9]*". The assignment below the latter names in all cases. + // form "subsystem_cbus_[0-9]*". The assignment below provides the latter names in all cases. Seq(PBUS, FBUS, MBUS, CBUS).foreach { loc => tlBusWrapperLocationMap.lift(loc).foreach { _.clockGroupNode := asyncClockGroupsNode } } From 4da9e49fc169d87da4462f8d244dfba53e67ffcb Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 7 Nov 2020 21:24:04 -0800 Subject: [PATCH 13/83] [clocking] Fix up() invocations in freq specification fragments --- .../chipyard/src/main/scala/ConfigFragments.scala | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index fb706895..479120ba 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -242,16 +242,19 @@ class WithFbusToSbusCrossingType(xType: ClockCrossingType) extends Config((site, * up the diplomatic graph to the clock sources. */ class WithPeripheryBusFrequency(freqMHz: Double) extends Config((site, here, up) => { - case PeripheryBusKey => up(PeripheryBusKey).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) + case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) }) class WithMemoryBusFrequency(freqMHz: Double) extends Config((site, here, up) => { - case MemoryBusKey => up(MemoryBusKey).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) + case MemoryBusKey => up(MemoryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) }) class WithSystemBusFrequency(freqMHz: Double) extends Config((site, here, up) => { - case SystemBusKey => up(SystemBusKey).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) + case SystemBusKey => up(SystemBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) +}) +class WithFrontBusFrequency(freqMHz: Double) extends Config((site, here, up) => { + case FrontBusKey => up(FrontBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) }) class WithControlBusFrequency(freqMHz: Double) extends Config((site, here, up) => { - case ControlBusKey => up(ControlBusKey).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) + case ControlBusKey => up(ControlBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) }) class WithRationalMemoryBusCrossing extends WithSbusToMbusCrossingType(RationalCrossing(Symmetric)) From 08c31014ccae0774c4621802c8ae1e812c515db0 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 7 Nov 2020 21:29:31 -0800 Subject: [PATCH 14/83] Build out a more complete multiclock example configuration --- .../src/main/scala/CustomBusTopologies.scala | 2 +- .../main/scala/config/AbstractConfig.scala | 3 ++- .../src/main/scala/config/RocketConfigs.scala | 19 +++++++++++++------ 3 files changed, 16 insertions(+), 8 deletions(-) diff --git a/generators/chipyard/src/main/scala/CustomBusTopologies.scala b/generators/chipyard/src/main/scala/CustomBusTopologies.scala index db617f83..2f6f3de7 100644 --- a/generators/chipyard/src/main/scala/CustomBusTopologies.scala +++ b/generators/chipyard/src/main/scala/CustomBusTopologies.scala @@ -42,7 +42,7 @@ case class CoherentMulticlockBusTopologyParams( ) // This differs from upstream only in that it does not use the legacy crossTo -// and crossFrom functions to ensure driveClockFromMaster = None +// and crossFrom functions, and it ensures driveClockFromMaster = None case class HierarchicalMulticlockBusTopologyParams( pbus: PeripheryBusParams, fbus: FrontBusParams, diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 301c03d7..347b0c06 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -43,7 +43,8 @@ class AbstractConfig extends Config( new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs new chipyard.config.WithNoSubsystemDrivenClocks ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks - new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // Unspecified clocks will match the frequency specified by the pbus dtsFrequency parameter + new chipyard.config.WithInheritBusFrequencyAssignments ++ // Unspecified clocks within a bus will receive the bus frequency if set + new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // Unspecified frequencies with match the pbus frequency (which is always set) new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index d413cc12..1afb4515 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -1,6 +1,7 @@ package chipyard import freechips.rocketchip.config.{Config} +import freechips.rocketchip.diplomacy.{AsynchronousCrossing} // -------------- // Rocket Configs @@ -175,13 +176,19 @@ class MMIORocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) -class DividedClockRocketConfig extends Config( - new chipyard.config.WithTileFrequency(200.0) ++ - new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore +class MulticlockRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new chipyard.config.WithMemoryBusFrequency(50.0) ++ - new chipyard.config.WithAsynchrousMemoryBusCrossing ++ - new testchipip.WithAsynchronousSerialSlaveCrossing ++ + // Frequency specifications + new chipyard.config.WithTileFrequency(1600.0) ++ // Matches the maximum frequency of U540 + new chipyard.config.WithSystemBusFrequency(800.0) ++ // Ditto + new chipyard.config.WithMemoryBusFrequency(1000.0) ++ // 2x the U540 freq (appropriate for a 128b Mbus) + new chipyard.config.WithPeripheryBusFrequency(100) ++ // Retains the default pbus frequency + new chipyard.config.WithSystemBusFrequencyAsDefault ++ // All unspecified clock frequencies, notably the implicit clock, will use the sbus freq (800 MHz) + // Crossing specifications + new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS + new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS + new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore + new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS new chipyard.config.AbstractConfig) class LBWIFRocketConfig extends Config( From 098a83ce98b0bf301bf53c486086c8ccbdf67086 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 7 Nov 2020 21:57:18 -0800 Subject: [PATCH 15/83] [CI] Add a multiclock config --- .circleci/config.yml | 6 ++++++ .circleci/defaults.sh | 3 ++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 6e74b9d5..f18f0e62 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -248,6 +248,12 @@ jobs: group-key: "group-cores" project-key: "chipyard-sodor" timeout: "30m" + chipyard-multiclock-rocket-run-tests: + executor: main-env + steps: + - run-tests: + group-key: "group-cores" + project-key: "chipyard-multiclock-rocket" chipyard-dmirocket-run-tests: executor: main-env steps: diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index c0bce62d..e9ccdfb5 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -47,7 +47,7 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim # key value store to get the build groups declare -A grouping -grouping["group-cores"]="chipyard-cva6 chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop" +grouping["group-cores"]="chipyard-cva6 chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket" grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spiflashread chipyard-spiflashwrite chipyard-mmios chipyard-lbwif" grouping["group-accels"]="chipyard-nvdla chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough" grouping["group-tracegen"]="tracegen tracegen-boom" @@ -75,6 +75,7 @@ mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config" mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig" mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig" mapping["chipyard-sodor"]=" CONFIG=Sodor5StageConfig" +mapping["chipyard-multiclock-rocket"]=" CONFIG=MulticlockRocketConfig" mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests" mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Tests" From 230bd81e0eeebe02021f3a094ce88ce5f9a8e715 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 8 Nov 2020 11:20:24 -0800 Subject: [PATCH 16/83] [firechip] Update legacy firechip config --- generators/firechip/src/main/scala/TargetConfigs.scala | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 89ac8073..e8f2afb5 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -201,8 +201,6 @@ class FireSimCVA6Config extends Config( //*********************************************************************************/ class FireSimMulticlockRocketConfig extends Config( new chipyard.config.WithTileFrequency(6400.0) ++ //lol - new WithDefaultFireSimBridges ++ - new WithDefaultMemModel ++ - new WithFireSimConfigTweaks ++ - new chipyard.DividedClockRocketConfig) + new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore + new FireSimRocketConfig) From 80487cc3710616c60871bf83a341ac4017607f82 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 10 Nov 2020 11:58:53 -0800 Subject: [PATCH 17/83] Update HierarchicalMulticlockBusTopologyParams to use cross{In, Out} --- .../chipyard/src/main/scala/CustomBusTopologies.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/chipyard/src/main/scala/CustomBusTopologies.scala b/generators/chipyard/src/main/scala/CustomBusTopologies.scala index 2f6f3de7..ee694d22 100644 --- a/generators/chipyard/src/main/scala/CustomBusTopologies.scala +++ b/generators/chipyard/src/main/scala/CustomBusTopologies.scala @@ -54,9 +54,9 @@ case class HierarchicalMulticlockBusTopologyParams( (FBUS, fbus), (CBUS, cbus)), connections = List( - (SBUS, CBUS, TLBusWrapperConnection(xType = xTypes.sbusToCbusXType, nodeBinding = BIND_STAR)()), - (CBUS, PBUS, TLBusWrapperConnection(xType = xTypes.cbusToPbusXType, nodeBinding = BIND_STAR)()), - (FBUS, SBUS, TLBusWrapperConnection(xType = xTypes.fbusToSbusXType, nodeBinding = BIND_QUERY, flipRendering = true)())) + (SBUS, CBUS, TLBusWrapperConnection. crossTo(xType = xTypes.sbusToCbusXType, driveClockFromMaster = None)), + (CBUS, PBUS, TLBusWrapperConnection. crossTo(xType = xTypes.cbusToPbusXType, driveClockFromMaster = None)), + (FBUS, SBUS, TLBusWrapperConnection.crossFrom(xType = xTypes.fbusToSbusXType, driveClockFromMaster = None))) ) // For subsystem/Configs.scala From 1110dd702cd02510f47e5a8cfd7bdbc88181a164 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Wed, 11 Nov 2020 18:57:16 +0000 Subject: [PATCH 18/83] Bump RC, firesim and barstools for chisel3.4 updates Note: firesim and barstools point to commits in the sifive forks of those repos I didn't update the URL in .gitmodules because I'm not sure how that works in a PR (because you wouldn't really want to merge sync'ing to the sifive repo). Requires: ucb-bar/barstools#92 and firesim/firesim#658 The version of rocket-chip, chisel3 and firrtl is chosen here because it is the latest known to pass my tests. You will likely want to bump further. --- generators/rocket-chip | 2 +- sims/firesim | 2 +- tools/barstools | 2 +- tools/chisel3 | 2 +- tools/firrtl | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/generators/rocket-chip b/generators/rocket-chip index 6eb1a3de..577994e3 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 6eb1a3de082e27c752d9e4c1ae971c693cc192eb +Subproject commit 577994e38e3115cafa3a232b0fc60584aacb996e diff --git a/sims/firesim b/sims/firesim index 37fe89a6..f89d746a 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 37fe89a65f1c1ccd8d2cc0d1efd0c06308d0224d +Subproject commit f89d746aa3c0c35c78a883c22c58679aeb9e2030 diff --git a/tools/barstools b/tools/barstools index 4a5c75fc..20d370be 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 4a5c75fcf85f03af858f1d7db04303d4b0733de7 +Subproject commit 20d370be496d3f9e873e5e63bf8d220727701dff diff --git a/tools/chisel3 b/tools/chisel3 index cc2971fe..d379dca4 160000 --- a/tools/chisel3 +++ b/tools/chisel3 @@ -1 +1 @@ -Subproject commit cc2971feb15d4bc8cb4a8138b5a095ccbc92dcc3 +Subproject commit d379dca4413d4cb08b02165a493faff01f3ddbb9 diff --git a/tools/firrtl b/tools/firrtl index c07da8a5..05d047a9 160000 --- a/tools/firrtl +++ b/tools/firrtl @@ -1 +1 @@ -Subproject commit c07da8a581789b88f7e6ffc98c8e810565034ad9 +Subproject commit 05d047a9befda3877f5d8a0a9e1076ffd520ddf9 From ba59d0318fe8552d0b9018d9305ba0433ae1c40e Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 15 Nov 2020 16:14:38 -0800 Subject: [PATCH 19/83] Bump barstools --- tools/barstools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/barstools b/tools/barstools index 20d370be..8e5757b5 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 20d370be496d3f9e873e5e63bf8d220727701dff +Subproject commit 8e5757b5ceb8a2c0246e3368baa5bc347dd6f99b From 70d43210d880a1257f864141d87fa5a4d6c6fe58 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 15 Nov 2020 18:18:04 -0800 Subject: [PATCH 20/83] [temp] Unable to build/get past chisel-testers --- .sbtopts | 2 ++ build.sbt | 8 ++------ common.mk | 20 +------------------- generators/boom | 2 +- generators/cva6 | 2 +- generators/hwacha | 2 +- generators/riscv-sodor | 2 +- generators/sifive-blocks | 2 +- generators/sifive-cache | 2 +- project/build.properties | 2 +- project/plugins.sbt | 6 ++++-- tools/chisel-testers | 2 +- tools/firrtl-interpreter | 2 +- tools/treadle | 2 +- variables.mk | 8 +++++++- 15 files changed, 26 insertions(+), 38 deletions(-) create mode 100644 .sbtopts diff --git a/.sbtopts b/.sbtopts new file mode 100644 index 00000000..e6cc0650 --- /dev/null +++ b/.sbtopts @@ -0,0 +1,2 @@ +-Dsbt.sourcemode=true +-Dsbt.workspace=$PWD diff --git a/build.sbt b/build.sbt index bbf7964f..e6320076 100644 --- a/build.sbt +++ b/build.sbt @@ -14,7 +14,7 @@ lazy val commonSettings = Seq( case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard case _ => MergeStrategy.first}}, scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"), - libraryDependencies += "org.scalatest" %% "scalatest" % "3.0.8" % "test", + libraryDependencies += "org.scalatest" %% "scalatest" % "3.2.0" % "test", libraryDependencies += "org.json4s" %% "json4s-jackson" % "3.6.1", libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value, libraryDependencies += "com.github.scopt" %% "scopt" % "3.7.0", @@ -77,11 +77,7 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => } toSeq // Subproject definitions begin -// -// FIRRTL is handled as an unmanaged dependency. Make will build the firrtl jar -// before launching sbt if any of the firrtl source files has been updated -// The jar is dropped in chipyard's lib/ directory, which is used as the unmanagedBase -// for all subprojects + lazy val chisel = (project in file("tools/chisel3")) lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) diff --git a/common.mk b/common.mk index ca34ffce..d0b11fe3 100644 --- a/common.mk +++ b/common.mk @@ -65,24 +65,6 @@ VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools) SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt -######################################################################################### -# jar creation variables and rules -######################################################################################### -FIRRTL_JAR := $(base_dir)/lib/firrtl.jar -FIRRTL_TEST_JAR := $(base_dir)/test_lib/firrtl-test.jar - -$(FIRRTL_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala) - $(MAKE) -C $(CHIPYARD_FIRRTL_DIR) SBT="$(SBT)" root_dir=$(CHIPYARD_FIRRTL_DIR) build-scala - mkdir -p $(@D) - cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl.jar $@ - touch $@ - -$(FIRRTL_TEST_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala) - cd $(CHIPYARD_FIRRTL_DIR) && $(SBT) "test:assembly" - mkdir -p $(@D) - cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl-test.jar $@ - touch $@ - ######################################################################################### # Bloop Project Definitions ######################################################################################### @@ -93,7 +75,7 @@ $(BLOOP_CONFIG_DIR)/TIMESTAMP: $(SBT_SOURCES) ######################################################################################### # create list of simulation file inputs ######################################################################################### -$(sim_files): $(call lookup_srcs,$(base_dir)/generators/utilities/src/main/scala,scala) $(FIRRTL_JAR) $(SCALA_BUILDTOOL_DEPS) +$(sim_files): $(call lookup_srcs,$(base_dir)/generators/utilities/src/main/scala,scala) $(SCALA_BUILDTOOL_DEPS) $(call run_scala_main,utilities,utilities.GenerateSimFiles,-td $(build_dir) -sim $(sim_name)) ######################################################################################### diff --git a/generators/boom b/generators/boom index dc22cacf..2dfec3d0 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit dc22cacf71fe88b95f3393d622f53648bf0440bd +Subproject commit 2dfec3d012e61ff07108af6034a86e60979deecd diff --git a/generators/cva6 b/generators/cva6 index 8a11e2c9..c2b9fc41 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit 8a11e2c97627459d0449853447bfc7ca64608b82 +Subproject commit c2b9fc412179a386fb4b662d13e588a9613f41d5 diff --git a/generators/hwacha b/generators/hwacha index e29b65db..c1b7306f 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit e29b65db86e4486ebdfd4f39d1265df83a2d7d9d +Subproject commit c1b7306f319aef6ea9ff0fd88d11d10244ee9e87 diff --git a/generators/riscv-sodor b/generators/riscv-sodor index d92a8476..cca8a7aa 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit d92a8476e4afbae189381d708136aef7d3970952 +Subproject commit cca8a7aa5743b9f9bf25779b87b464187c5c3fbc diff --git a/generators/sifive-blocks b/generators/sifive-blocks index c240e629..612ed01d 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit c240e629e2fc111cbb12e4fe707be898b5204984 +Subproject commit 612ed01df3be83ad0198fb9bd7e367ea43df3d56 diff --git a/generators/sifive-cache b/generators/sifive-cache index 4ebefa3e..d4db623f 160000 --- a/generators/sifive-cache +++ b/generators/sifive-cache @@ -1 +1 @@ -Subproject commit 4ebefa3e30ec44bd2f4ff82747025fb7b362b954 +Subproject commit d4db623ff534f775ffc49f59c4a9ef24d5d759d0 diff --git a/project/build.properties b/project/build.properties index 8522443d..0837f7a1 100644 --- a/project/build.properties +++ b/project/build.properties @@ -1 +1 @@ -sbt.version=1.3.2 +sbt.version=1.3.13 diff --git a/project/plugins.sbt b/project/plugins.sbt index 3fe776fa..8c0937ed 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -5,16 +5,18 @@ resolvers += "jgit-repo" at "https://download.eclipse.org/jgit/maven" addSbtPlugin("net.virtual-void" % "sbt-dependency-graph" % "0.9.2") addSbtPlugin("com.typesafe.sbt" % "sbt-ghpages" % "0.6.2") addSbtPlugin("com.typesafe.sbt" % "sbt-site" % "1.3.1") -addSbtPlugin("com.eed3si9n" % "sbt-buildinfo" % "0.7.0") +addSbtPlugin("com.eed3si9n" % "sbt-buildinfo" % "0.10.0") addSbtPlugin("org.xerial.sbt" % "sbt-pack" % "0.9.3") addSbtPlugin("com.eed3si9n" % "sbt-unidoc" % "0.4.1") addSbtPlugin("org.scoverage" % "sbt-scoverage" % "1.5.1") addSbtPlugin("org.scalastyle" %% "scalastyle-sbt-plugin" % "1.0.0") -addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.14.6") +addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.15.0") addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.1") addSbtPlugin("com.github.gseitz" % "sbt-protobuf" % "0.6.3") addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.4") addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "0.6.1") addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.1") +addSbtPlugin("com.eed3si9n" % "sbt-sriracha" % "0.1.0") +addSbtPlugin("org.scalameta" % "sbt-mdoc" % "2.2.5" ) libraryDependencies += "com.github.os72" % "protoc-jar" % "3.5.1.1" diff --git a/tools/chisel-testers b/tools/chisel-testers index 1aa906fe..c5b99a45 160000 --- a/tools/chisel-testers +++ b/tools/chisel-testers @@ -1 +1 @@ -Subproject commit 1aa906fe168eb5ddca705ec955b27cf5c8856e4d +Subproject commit c5b99a452f84af3f581d34e9c51c6c65b6c2a63c diff --git a/tools/firrtl-interpreter b/tools/firrtl-interpreter index a881c07d..5ab0cfe7 160000 --- a/tools/firrtl-interpreter +++ b/tools/firrtl-interpreter @@ -1 +1 @@ -Subproject commit a881c07df6bceea462dbbd9a28e25721a1e88567 +Subproject commit 5ab0cfe7020ca17804078c85d020730764ee176f diff --git a/tools/treadle b/tools/treadle index 1c67bc84..925687ad 160000 --- a/tools/treadle +++ b/tools/treadle @@ -1 +1 @@ -Subproject commit 1c67bc846aafc3bdd707f76ead8cefd5f93e0376 +Subproject commit 925687ad22c42dd2c8b4dc127c0476f9902b3163 diff --git a/variables.mk b/variables.mk index b187a23d..2828366c 100644 --- a/variables.mk +++ b/variables.mk @@ -154,6 +154,12 @@ JAVA_ARGS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M SCALA_VERSION=2.12.10 SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION)) SBT ?= java $(JAVA_ARGS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar +# Running with sbt-launch.jar doesn't read .sbtopts by default +# # Set if the file exists (if it exists, we're building chisel3 and firrtl from source) +sbtopts_file := $(base_dir)/.sbtopts +ifneq (,$(wildcard $(sbtopts_file))) + SBT_OPTS ?= $(shell cat $(sbtopts_file)) +endif BLOOP ?= bloop BLOOP_CONFIG_DIR ?= $(base_dir)/.bloop @@ -176,7 +182,7 @@ define run_scala_main endef else define run_scala_main - cd $(base_dir) && $(SBT) "project $(1)" "runMain $(2) $(3)" + cd $(base_dir) && $(SBT) $(SBT_OPTS) "project $(1)" "runMain $(2) $(3)" endef endif From 9d9813fe0abf8146aaade002ef06203b8065c491 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 16 Nov 2020 22:24:18 -0800 Subject: [PATCH 21/83] [temp] Following RC's way to build Chisel from source or Maven [ci skip] --- .sbtopts | 2 +- build.sbt | 25 ++++++++++++++++++++----- 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/.sbtopts b/.sbtopts index e6cc0650..2358d787 100644 --- a/.sbtopts +++ b/.sbtopts @@ -1,2 +1,2 @@ -Dsbt.sourcemode=true --Dsbt.workspace=$PWD +-Dsbt.workspace=$PWD/tools diff --git a/build.sbt b/build.sbt index e6320076..cffc235d 100644 --- a/build.sbt +++ b/build.sbt @@ -78,7 +78,15 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => // Subproject definitions begin -lazy val chisel = (project in file("tools/chisel3")) +// This needs to stay in sync with the chisel3 and firrtl git submodules +val chiselVersion = "3.4.0" + +lazy val chiselRef = ProjectRef(workspaceDirectory / "chisel3", "chisel") +lazy val chiselLib = "edu.berkeley.cs" %% "chisel3" % chiselVersion +// While not built from source, *must* be in sync with the chisel3 git submodule +// Building from source requires extending sbt-sriracha or a similar plugin and +// keeping scalaVersion in sync with chisel3 to the minor version +lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) .settings(commonSettings) @@ -87,7 +95,9 @@ lazy val treadle = (project in file("tools/treadle")) .settings(commonSettings) lazy val chisel_testers = (project in file("tools/chisel-testers")) - .dependsOn(chisel, firrtl_interpreter, treadle) + .sourceDependency(chiselRef, chiselLib) + .dependsOn(firrtl_interpreter, treadle) + .settings(addCompilerPlugin(chiselPluginLib)) .settings( commonSettings, libraryDependencies ++= Seq( @@ -113,15 +123,18 @@ lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/bu .settings(commonSettings) lazy val rocketchip = freshProject("rocketchip", rocketChipDir) + .sourceDependency(chiselRef, chiselLib) + .dependsOn(hardfloat, rocketMacros, rocketConfig) + .settings(addCompilerPlugin(chiselPluginLib)) .settings(commonSettings) - .dependsOn(chisel, hardfloat, rocketMacros, rocketConfig) lazy val testchipip = (project in file("generators/testchipip")) .dependsOn(rocketchip, sifive_blocks) .settings(commonSettings) lazy val iocell = (project in file("./tools/barstools/iocell/")) - .dependsOn(chisel) + .sourceDependency(chiselRef, chiselLib) + .settings(addCompilerPlugin(chiselPluginLib)) .settings(commonSettings) lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) @@ -184,7 +197,9 @@ lazy val barstoolsMacros = (project in file("./tools/barstools/macros/")) .settings(commonSettings) lazy val dsptools = freshProject("dsptools", file("./tools/dsptools")) - .dependsOn(chisel, chisel_testers) + .sourceDependency(chiselRef, chiselLib) + .dependsOn(chisel_testers) + .settings(addCompilerPlugin(chiselPluginLib)) .settings( commonSettings, libraryDependencies ++= Seq( From a0d479f3ea996524c9a57a65dff4128b2da5604f Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 16 Nov 2020 22:55:04 -0800 Subject: [PATCH 22/83] Working FIRRTL/RC/Chisel3 build | chisel-testers still broken --- build.sbt | 27 +++++++++------------------ project/plugins.sbt | 2 +- 2 files changed, 10 insertions(+), 19 deletions(-) diff --git a/build.sbt b/build.sbt index cffc235d..27b08a3b 100644 --- a/build.sbt +++ b/build.sbt @@ -79,14 +79,7 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => // Subproject definitions begin // This needs to stay in sync with the chisel3 and firrtl git submodules -val chiselVersion = "3.4.0" - -lazy val chiselRef = ProjectRef(workspaceDirectory / "chisel3", "chisel") -lazy val chiselLib = "edu.berkeley.cs" %% "chisel3" % chiselVersion -// While not built from source, *must* be in sync with the chisel3 git submodule -// Building from source requires extending sbt-sriracha or a similar plugin and -// keeping scalaVersion in sync with chisel3 to the minor version -lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full +lazy val chisel = (project in file("tools/chisel3")) lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) .settings(commonSettings) @@ -95,9 +88,7 @@ lazy val treadle = (project in file("tools/treadle")) .settings(commonSettings) lazy val chisel_testers = (project in file("tools/chisel-testers")) - .sourceDependency(chiselRef, chiselLib) - .dependsOn(firrtl_interpreter, treadle) - .settings(addCompilerPlugin(chiselPluginLib)) + .dependsOn(firrtl_interpreter, treadle, chisel) .settings( commonSettings, libraryDependencies ++= Seq( @@ -123,18 +114,20 @@ lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/bu .settings(commonSettings) lazy val rocketchip = freshProject("rocketchip", rocketChipDir) - .sourceDependency(chiselRef, chiselLib) - .dependsOn(hardfloat, rocketMacros, rocketConfig) - .settings(addCompilerPlugin(chiselPluginLib)) + .dependsOn(hardfloat, rocketMacros, rocketConfig, chisel) .settings(commonSettings) + .settings( // Settings for scalafix + semanticdbEnabled := true, + semanticdbVersion := scalafixSemanticdb.revision, + scalacOptions += "-Ywarn-unused-import" + ) lazy val testchipip = (project in file("generators/testchipip")) .dependsOn(rocketchip, sifive_blocks) .settings(commonSettings) lazy val iocell = (project in file("./tools/barstools/iocell/")) - .sourceDependency(chiselRef, chiselLib) - .settings(addCompilerPlugin(chiselPluginLib)) + .dependsOn(chisel) .settings(commonSettings) lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) @@ -197,9 +190,7 @@ lazy val barstoolsMacros = (project in file("./tools/barstools/macros/")) .settings(commonSettings) lazy val dsptools = freshProject("dsptools", file("./tools/dsptools")) - .sourceDependency(chiselRef, chiselLib) .dependsOn(chisel_testers) - .settings(addCompilerPlugin(chiselPluginLib)) .settings( commonSettings, libraryDependencies ++= Seq( diff --git a/project/plugins.sbt b/project/plugins.sbt index 8c0937ed..b6fe132a 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -13,7 +13,7 @@ addSbtPlugin("org.scalastyle" %% "scalastyle-sbt-plugin" % "1.0.0") addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.15.0") addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.1") addSbtPlugin("com.github.gseitz" % "sbt-protobuf" % "0.6.3") -addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.4") +addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.21") addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "0.6.1") addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.1") addSbtPlugin("com.eed3si9n" % "sbt-sriracha" % "0.1.0") From 1b00d540f0a964dfbe86449df6491eda7910d639 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 17 Nov 2020 15:14:30 -0800 Subject: [PATCH 23/83] Add config fragment for replacing L2 with broadcastManager --- generators/chipyard/src/main/scala/ConfigFragments.scala | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 479120ba..c5c85e47 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -151,6 +151,11 @@ class WithRocketDCacheScratchpad extends Config((site, here, up) => { } }) +// Replaces the L2 with a broadcast manager for maintaining coherence +class WithBroadcastManager extends Config((site, here, up) => { + case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = CoherenceManagerWrapper.broadcastManager) +}) + class WithHwachaTest extends Config((site, here, up) => { case TestSuitesKey => (tileParams: Seq[TileParams], suiteHelper: TestSuiteHelper, p: Parameters) => { up(TestSuitesKey).apply(tileParams, suiteHelper, p) From 5b1b4b3efe65299360a0de838bcc2c7025880b38 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 19 Nov 2020 15:28:24 -0800 Subject: [PATCH 24/83] Bump Gemmini/Hwacha/Sha3 --- generators/gemmini | 2 +- generators/hwacha | 2 +- generators/sha3 | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/gemmini b/generators/gemmini index caaf781e..371bc330 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit caaf781ec9d69e45443e496046bc6ab439e3e54f +Subproject commit 371bc33038e633779f52e26eaa0031f2820c2f0d diff --git a/generators/hwacha b/generators/hwacha index c1b7306f..e0109674 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit c1b7306f319aef6ea9ff0fd88d11d10244ee9e87 +Subproject commit e0109674572f4b40641a89db9e0429e51b5cb73a diff --git a/generators/sha3 b/generators/sha3 index 762d9d08..a4ea9602 160000 --- a/generators/sha3 +++ b/generators/sha3 @@ -1 +1 @@ -Subproject commit 762d9d08f8ccd96ba7ab12ead6d38a6b57fa8710 +Subproject commit a4ea960248fdf8267b515723d472b018b09ac24f From 222580a290ec243d8cc97154b61d5e1467b35c69 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 19 Nov 2020 16:13:58 -0800 Subject: [PATCH 25/83] Bump dsptools --- tools/dsptools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/dsptools b/tools/dsptools index e32ab8a0..ce6d87b2 160000 --- a/tools/dsptools +++ b/tools/dsptools @@ -1 +1 @@ -Subproject commit e32ab8a0c77d419b52376064534090ff2583929d +Subproject commit ce6d87b2f23bf87085e4913e8324513147f43488 From 571e7517eb57deb10ad32e0e8e2d0ec1aaec036f Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 19 Nov 2020 20:06:28 -0800 Subject: [PATCH 26/83] Bump barstools, chisel-testers, dsptools | Split build.sbt dependencies between projects | Bump CY collateral --- .gitmodules | 2 +- build.sbt | 78 ++++++++++++------- .../scala/clocking/ResetSynchronizer.scala | 30 ------- .../src/main/scala/example/NodeTypes.scala | 8 +- .../src/main/scala/example/TutorialTile.scala | 2 + tools/barstools | 2 +- tools/chisel-testers | 2 +- tools/dsptools | 2 +- 8 files changed, 60 insertions(+), 66 deletions(-) delete mode 100644 generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala diff --git a/.gitmodules b/.gitmodules index 7054c14f..55b4be56 100644 --- a/.gitmodules +++ b/.gitmodules @@ -76,7 +76,7 @@ url = https://github.com/ucb-bar/dsptools.git [submodule "tools/chisel-testers"] path = tools/chisel-testers - url = https://github.com/freechipsproject/chisel-testers.git + url = https://github.com/abejgonzalez/chisel-testers.git [submodule "tools/treadle"] path = tools/treadle url = https://github.com/freechipsproject/treadle.git diff --git a/build.sbt b/build.sbt index 27b08a3b..77a0962a 100644 --- a/build.sbt +++ b/build.sbt @@ -14,14 +14,11 @@ lazy val commonSettings = Seq( case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard case _ => MergeStrategy.first}}, scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"), - libraryDependencies += "org.scalatest" %% "scalatest" % "3.2.0" % "test", - libraryDependencies += "org.json4s" %% "json4s-jackson" % "3.6.1", + libraryDependencies += "org.scalatest" %% "scalatest" % "3.2.2" % "test", + libraryDependencies += "org.scalatestplus" %% "scalacheck-1-14" % "3.1.1.1" % "test", + libraryDependencies += "org.json4s" %% "json4s-jackson" % "3.6.10", libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value, - libraryDependencies += "com.github.scopt" %% "scopt" % "3.7.0", - libraryDependencies += "org.scala-lang.modules" % "scala-jline" % "2.12.1", - libraryDependencies += "com.typesafe.play" %% "play-json" % "2.6.10", libraryDependencies += "org.typelevel" %% "spire" % "0.16.2", - libraryDependencies += "org.scalanlp" %% "breeze" % "1.0", addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, allDependencies := allDependencies.value.filterNot(_.organization == "edu.berkeley.cs"), @@ -72,9 +69,9 @@ def freshProject(name: String, dir: File): Project = { // Fork each scala test for now, to work around persistent mutable state // in Rocket-Chip based generators def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => - val options = ForkOptions() - new Group(test.name, Seq(test), SubProcess(options)) - } toSeq + val options = ForkOptions() + new Group(test.name, Seq(test), SubProcess(options)) +} toSeq // Subproject definitions begin @@ -82,22 +79,32 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => lazy val chisel = (project in file("tools/chisel3")) lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) - .settings(commonSettings) + .settings( + commonSettings, + libraryDependencies ++= Seq( + "org.scala-lang.modules" % "scala-jline" % "2.12.1", + )) lazy val treadle = (project in file("tools/treadle")) - .settings(commonSettings) + .settings( + commonSettings, + libraryDependencies ++= Seq( + "org.scala-lang.modules" % "scala-jline" % "2.12.1", + "com.github.scopt" %% "scopt" % "3.7.1", + "org.json4s" %% "json4s-native" % "3.6.10" + )) lazy val chisel_testers = (project in file("tools/chisel-testers")) .dependsOn(firrtl_interpreter, treadle, chisel) .settings( - commonSettings, - libraryDependencies ++= Seq( - "junit" % "junit" % "4.12", - "org.scalatest" %% "scalatest" % "3.0.5", - "org.scalacheck" %% "scalacheck" % "1.14.0", - "com.github.scopt" %% "scopt" % "3.7.0" - ) - ) + commonSettings, + libraryDependencies ++= Seq( + "junit" % "junit" % "4.13", + "org.scalatest" %% "scalatest" % "3.2.2", + "org.scalatestplus" %% "scalacheck-1-14" % "3.1.1.1", + "org.scalacheck" %% "scalacheck" % "1.14.3", + "com.github.scopt" %% "scopt" % "3.7.1" + )) // Contains annotations & firrtl passes you may wish to use in rocket-chip without // introducing a circular dependency between RC and MIDAS @@ -170,7 +177,11 @@ lazy val sha3 = (project in file("generators/sha3")) lazy val gemmini = (project in file("generators/gemmini")) .dependsOn(rocketchip, chisel_testers, testchipip) - .settings(commonSettings) + .settings( + commonSettings, + libraryDependencies ++= Seq( + "org.scalanlp" %% "breeze" % "0.13.2" + )) lazy val nvdla = (project in file("generators/nvdla")) .dependsOn(rocketchip) @@ -182,26 +193,37 @@ lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeo .settings(libraryDependencies ++= Seq("io.github.daviddenton" %% "handlebars-scala-fork" % "2.3.0")) lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/")) - .settings(commonSettings) + .settings( + commonSettings, + libraryDependencies ++= Seq( + "com.typesafe.play" %% "play-json" % "2.6.10" + )) lazy val barstoolsMacros = (project in file("./tools/barstools/macros/")) .dependsOn(firrtl_interpreter, mdf, rocketchip) .enablePlugins(sbtassembly.AssemblyPlugin) .settings(commonSettings) +val dsptoolsDependencies = Seq( + "org.scalanlp" %% "breeze" % "1.0", + "junit" % "junit" % "4.13" % "test", + "org.scalatest" %% "scalatest" % "3.2.2", + "org.scalacheck" %% "scalacheck" % "1.14.3" % "test" +) + lazy val dsptools = freshProject("dsptools", file("./tools/dsptools")) .dependsOn(chisel_testers) .settings( - commonSettings, - libraryDependencies ++= Seq( - "junit" % "junit" % "4.13" % "test", - "org.scalatest" %% "scalatest" % "3.0.8", - "org.scalacheck" %% "scalacheck" % "1.14.3" % "test" - )) + commonSettings, + libraryDependencies ++= dsptoolsDependencies + ) lazy val `rocket-dsptools` = freshProject("rocket-dsptools", file("./tools/dsptools/rocket")) .dependsOn(rocketchip, dsptools) - .settings(commonSettings) + .settings( + commonSettings, + libraryDependencies ++= dsptoolsDependencies + ) lazy val sifive_blocks = (project in file("generators/sifive-blocks")) .dependsOn(rocketchip) diff --git a/generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala b/generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala deleted file mode 100644 index 2ba8e855..00000000 --- a/generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala +++ /dev/null @@ -1,30 +0,0 @@ - -package chipyard.clocking - -import chisel3._ - -import freechips.rocketchip.config.{Parameters} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.prci._ -import freechips.rocketchip.util.{ResetCatchAndSync} - -/** - * Instantiates a reset synchronizer on all clock-reset pairs in a clock group - */ -class ClockGroupResetSynchronizer(implicit p: Parameters) extends LazyModule { - val node = ClockGroupAdapterNode() - lazy val module = new LazyRawModuleImp(this) { - (node.out zip node.in).map { case ((oG, _), (iG, _)) => - (oG.member.data zip iG.member.data).foreach { case (o, i) => - o.clock := i.clock - o.reset := ResetCatchAndSync(i.clock, i.reset.asBool) - } - } - } -} - -object ClockGroupResetSynchronizer { - def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupResetSynchronizer()).node -} - - diff --git a/generators/chipyard/src/main/scala/example/NodeTypes.scala b/generators/chipyard/src/main/scala/example/NodeTypes.scala index 0e2b6565..914e5ba5 100644 --- a/generators/chipyard/src/main/scala/example/NodeTypes.scala +++ b/generators/chipyard/src/main/scala/example/NodeTypes.scala @@ -11,7 +11,7 @@ import testchipip.TLHelper // DOC include start: MyClient class MyClient(implicit p: Parameters) extends LazyModule { - val node = TLHelper.makeClientNode(TLClientParameters( + val node = TLHelper.makeClientNode(TLMasterParameters.v1( name = "my-client", sourceId = IdRange(0, 4), requestFifo = true, @@ -29,7 +29,7 @@ class MyClient(implicit p: Parameters) extends LazyModule { class MyManager(implicit p: Parameters) extends LazyModule { val device = new SimpleDevice("my-device", Seq("tutorial,my-device0")) val beatBytes = 8 - val node = TLHelper.makeManagerNode(beatBytes, TLManagerParameters( + val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1( address = Seq(AddressSet(0x20000, 0xfff)), resources = device.reg, regionType = RegionType.UNCACHED, @@ -83,7 +83,7 @@ class MyClientGroup(implicit p: Parameters) extends LazyModule { // DOC include start: MyManagerGroup class MyManager1(beatBytes: Int)(implicit p: Parameters) extends LazyModule { - val node = TLHelper.makeManagerNode(beatBytes, TLManagerParameters( + val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1( address = Seq(AddressSet(0x0, 0xfff)))) lazy val module = new LazyModuleImp(this) { @@ -92,7 +92,7 @@ class MyManager1(beatBytes: Int)(implicit p: Parameters) extends LazyModule { } class MyManager2(beatBytes: Int)(implicit p: Parameters) extends LazyModule { - val node = TLHelper.makeManagerNode(beatBytes, TLManagerParameters( + val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1( address = Seq(AddressSet(0x1000, 0xfff)))) lazy val module = new LazyModuleImp(this) { diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala index 9af2cb54..23b05f76 100644 --- a/generators/chipyard/src/main/scala/example/TutorialTile.scala +++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala @@ -43,6 +43,8 @@ case class MyCoreParams( val pmpGranularity: Int = 4 // copied from Rocket val nBreakpoints: Int = 0 // TODO: Check val useBPWatch: Boolean = false + val mcontextWidth: Int = 0 + val scontextWidth: Int = 0 val nPerfCounters: Int = 29 val haveBasicCounters: Boolean = true val haveFSDirty: Boolean = false diff --git a/tools/barstools b/tools/barstools index 8e5757b5..845af06b 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 8e5757b5ceb8a2c0246e3368baa5bc347dd6f99b +Subproject commit 845af06b1515c69b1d788726134e92b808bf45e4 diff --git a/tools/chisel-testers b/tools/chisel-testers index c5b99a45..5b9cc56d 160000 --- a/tools/chisel-testers +++ b/tools/chisel-testers @@ -1 +1 @@ -Subproject commit c5b99a452f84af3f581d34e9c51c6c65b6c2a63c +Subproject commit 5b9cc56dd80c8d3bce67d54385d769037e2481d8 diff --git a/tools/dsptools b/tools/dsptools index ce6d87b2..74612fd7 160000 --- a/tools/dsptools +++ b/tools/dsptools @@ -1 +1 @@ -Subproject commit ce6d87b2f23bf87085e4913e8324513147f43488 +Subproject commit 74612fd76645bfcfcc1c711ed43025cb8105e539 From 11ab0d73461f7322ce906f9beb0133a01fa4116c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 20 Nov 2020 10:48:44 -0800 Subject: [PATCH 27/83] Put libdeps back into commonSettings in build.sbt --- build.sbt | 56 ++++++++++++++++++------------------------------------- 1 file changed, 18 insertions(+), 38 deletions(-) diff --git a/build.sbt b/build.sbt index 77a0962a..e58e7d60 100644 --- a/build.sbt +++ b/build.sbt @@ -18,7 +18,13 @@ lazy val commonSettings = Seq( libraryDependencies += "org.scalatestplus" %% "scalacheck-1-14" % "3.1.1.1" % "test", libraryDependencies += "org.json4s" %% "json4s-jackson" % "3.6.10", libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value, + libraryDependencies += "com.github.scopt" %% "scopt" % "3.7.1", + libraryDependencies += "org.scala-lang.modules" % "scala-jline" % "2.12.1", + libraryDependencies += "com.typesafe.play" %% "play-json" % "2.6.10", libraryDependencies += "org.typelevel" %% "spire" % "0.16.2", + libraryDependencies += "org.scalanlp" %% "breeze" % "1.0", + libraryDependencies += "org.json4s" %% "json4s-native" % "3.6.10", + libraryDependencies += "junit" % "junit" % "4.13", addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, allDependencies := allDependencies.value.filterNot(_.organization == "edu.berkeley.cs"), @@ -75,27 +81,16 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => // Subproject definitions begin -// This needs to stay in sync with the chisel3 and firrtl git submodules lazy val chisel = (project in file("tools/chisel3")) lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) - .settings( - commonSettings, - libraryDependencies ++= Seq( - "org.scala-lang.modules" % "scala-jline" % "2.12.1", - )) + .settings(commonSettings) lazy val treadle = (project in file("tools/treadle")) - .settings( - commonSettings, - libraryDependencies ++= Seq( - "org.scala-lang.modules" % "scala-jline" % "2.12.1", - "com.github.scopt" %% "scopt" % "3.7.1", - "org.json4s" %% "json4s-native" % "3.6.10" - )) + .settings(commonSettings) lazy val chisel_testers = (project in file("tools/chisel-testers")) - .dependsOn(firrtl_interpreter, treadle, chisel) + .dependsOn(chisel, firrtl_interpreter, treadle) .settings( commonSettings, libraryDependencies ++= Seq( @@ -121,7 +116,7 @@ lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/bu .settings(commonSettings) lazy val rocketchip = freshProject("rocketchip", rocketChipDir) - .dependsOn(hardfloat, rocketMacros, rocketConfig, chisel) + .dependsOn(chisel, hardfloat, rocketMacros, rocketConfig) .settings(commonSettings) .settings( // Settings for scalafix semanticdbEnabled := true, @@ -177,11 +172,7 @@ lazy val sha3 = (project in file("generators/sha3")) lazy val gemmini = (project in file("generators/gemmini")) .dependsOn(rocketchip, chisel_testers, testchipip) - .settings( - commonSettings, - libraryDependencies ++= Seq( - "org.scalanlp" %% "breeze" % "0.13.2" - )) + .settings(commonSettings) lazy val nvdla = (project in file("generators/nvdla")) .dependsOn(rocketchip) @@ -193,37 +184,26 @@ lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeo .settings(libraryDependencies ++= Seq("io.github.daviddenton" %% "handlebars-scala-fork" % "2.3.0")) lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/")) - .settings( - commonSettings, - libraryDependencies ++= Seq( - "com.typesafe.play" %% "play-json" % "2.6.10" - )) + .settings(commonSettings) lazy val barstoolsMacros = (project in file("./tools/barstools/macros/")) .dependsOn(firrtl_interpreter, mdf, rocketchip) .enablePlugins(sbtassembly.AssemblyPlugin) .settings(commonSettings) -val dsptoolsDependencies = Seq( - "org.scalanlp" %% "breeze" % "1.0", - "junit" % "junit" % "4.13" % "test", - "org.scalatest" %% "scalatest" % "3.2.2", - "org.scalacheck" %% "scalacheck" % "1.14.3" % "test" -) - lazy val dsptools = freshProject("dsptools", file("./tools/dsptools")) .dependsOn(chisel_testers) .settings( commonSettings, - libraryDependencies ++= dsptoolsDependencies - ) + libraryDependencies ++= Seq( + "junit" % "junit" % "4.13" % "test", + "org.scalatest" %% "scalatest" % "3.2.2", + "org.scalacheck" %% "scalacheck" % "1.14.3" % "test" + )) lazy val `rocket-dsptools` = freshProject("rocket-dsptools", file("./tools/dsptools/rocket")) .dependsOn(rocketchip, dsptools) - .settings( - commonSettings, - libraryDependencies ++= dsptoolsDependencies - ) + .settings(commonSettings) lazy val sifive_blocks = (project in file("generators/sifive-blocks")) .dependsOn(rocketchip) From 2b4fb555af8dc06c8f6fe19c32d1002afebc0f09 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 20 Nov 2020 12:15:19 -0800 Subject: [PATCH 28/83] Use ProjectRef for FIRRTL and use it for firrtl-interpreter --- build.sbt | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/build.sbt b/build.sbt index e58e7d60..51172677 100644 --- a/build.sbt +++ b/build.sbt @@ -81,9 +81,12 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => // Subproject definitions begin -lazy val chisel = (project in file("tools/chisel3")) +lazy val chisel = (project in file("tools/chisel3")) + +lazy val firrtl = ProjectRef(workspaceDirectory / "firrtl", "firrtl") lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) + .dependsOn(firrtl) .settings(commonSettings) lazy val treadle = (project in file("tools/treadle")) @@ -107,7 +110,8 @@ lazy val midasTargetUtils = ProjectRef(firesimDir, "targetutils") // Rocket-chip dependencies (subsumes making RC a RootProject) lazy val hardfloat = (project in rocketChipDir / "hardfloat") - .settings(commonSettings).dependsOn(midasTargetUtils) + .dependsOn(midasTargetUtils) + .settings(commonSettings) lazy val rocketMacros = (project in rocketChipDir / "macros") .settings(commonSettings) From 51b254f6b34f4f2535c260d4ba71030992f9f113 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 20 Nov 2020 13:52:38 -0800 Subject: [PATCH 29/83] Small build.sbt cleanup --- build.sbt | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/build.sbt b/build.sbt index 51172677..ba0fea4e 100644 --- a/build.sbt +++ b/build.sbt @@ -1,12 +1,12 @@ import Tests._ -// This gives us a nicer handle to the root project instead of using the +// This gives us a nicer handle to the root project instead of using the // implicit one lazy val chipyardRoot = Project("chipyardRoot", file(".")) lazy val commonSettings = Seq( organization := "edu.berkeley.cs", - version := "1.0", + version := "1.3", scalaVersion := "2.12.10", traceLevel := 15, test in assembly := {}, @@ -14,17 +14,19 @@ lazy val commonSettings = Seq( case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard case _ => MergeStrategy.first}}, scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"), - libraryDependencies += "org.scalatest" %% "scalatest" % "3.2.2" % "test", - libraryDependencies += "org.scalatestplus" %% "scalacheck-1-14" % "3.1.1.1" % "test", - libraryDependencies += "org.json4s" %% "json4s-jackson" % "3.6.10", - libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value, - libraryDependencies += "com.github.scopt" %% "scopt" % "3.7.1", - libraryDependencies += "org.scala-lang.modules" % "scala-jline" % "2.12.1", - libraryDependencies += "com.typesafe.play" %% "play-json" % "2.6.10", - libraryDependencies += "org.typelevel" %% "spire" % "0.16.2", - libraryDependencies += "org.scalanlp" %% "breeze" % "1.0", - libraryDependencies += "org.json4s" %% "json4s-native" % "3.6.10", - libraryDependencies += "junit" % "junit" % "4.13", + libraryDependencies ++= Seq( + "org.scalatest" %% "scalatest" % "3.2.2" % "test", + "org.scalatestplus" %% "scalacheck-1-14" % "3.1.1.1" % "test", + "org.json4s" %% "json4s-jackson" % "3.6.10", + "org.scala-lang" % "scala-reflect" % scalaVersion.value, + "com.github.scopt" %% "scopt" % "3.7.1", + "org.scala-lang.modules" % "scala-jline" % "2.12.1", + "com.typesafe.play" %% "play-json" % "2.6.10", + "org.typelevel" %% "spire" % "0.16.2", + "org.scalanlp" %% "breeze" % "1.0", + "org.json4s" %% "json4s-native" % "3.6.10", + "junit" % "junit" % "4.13" + ), addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, allDependencies := allDependencies.value.filterNot(_.organization == "edu.berkeley.cs"), From c6e49e0716ba21e34f83447c6f2156d0d3946fa9 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 20 Nov 2020 15:05:00 -0800 Subject: [PATCH 30/83] Follow RC's SBT sriracha use | Bump FIRRTL plugin --- build.sbt | 21 ++++++++++++++++----- project/plugins.sbt | 2 +- 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/build.sbt b/build.sbt index ba0fea4e..6ac4c85e 100644 --- a/build.sbt +++ b/build.sbt @@ -83,19 +83,27 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => // Subproject definitions begin +val chiselVersion = "3.4.0" lazy val chisel = (project in file("tools/chisel3")) +lazy val chiselLib = "edu.berkeley.cs" %% "chisel3" % chiselVersion +// While not built from source, *must* be in sync with the chisel3 git submodule +// Building from source requires extending sbt-sriracha or a similar plugin and +// keeping scalaVersion in sync with chisel3 to the minor version +lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full -lazy val firrtl = ProjectRef(workspaceDirectory / "firrtl", "firrtl") +lazy val firrtlRef = ProjectRef(workspaceDirectory / "firrtl", "firrtl") lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) - .dependsOn(firrtl) + .dependsOn(firrtlRef) .settings(commonSettings) lazy val treadle = (project in file("tools/treadle")) .settings(commonSettings) lazy val chisel_testers = (project in file("tools/chisel-testers")) - .dependsOn(chisel, firrtl_interpreter, treadle) + .sourceDependency(chisel, chiselLib) + .settings(addCompilerPlugin(chiselPluginLib)) + .dependsOn(firrtl_interpreter, treadle) .settings( commonSettings, libraryDependencies ++= Seq( @@ -122,7 +130,9 @@ lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/bu .settings(commonSettings) lazy val rocketchip = freshProject("rocketchip", rocketChipDir) - .dependsOn(chisel, hardfloat, rocketMacros, rocketConfig) + .sourceDependency(chisel, chiselLib) + .settings(addCompilerPlugin(chiselPluginLib)) + .dependsOn(hardfloat, rocketMacros, rocketConfig) .settings(commonSettings) .settings( // Settings for scalafix semanticdbEnabled := true, @@ -135,7 +145,8 @@ lazy val testchipip = (project in file("generators/testchipip")) .settings(commonSettings) lazy val iocell = (project in file("./tools/barstools/iocell/")) - .dependsOn(chisel) + .sourceDependency(chisel, chiselLib) + .settings(addCompilerPlugin(chiselPluginLib)) .settings(commonSettings) lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) diff --git a/project/plugins.sbt b/project/plugins.sbt index b6fe132a..496deb8d 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -19,4 +19,4 @@ addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.1") addSbtPlugin("com.eed3si9n" % "sbt-sriracha" % "0.1.0") addSbtPlugin("org.scalameta" % "sbt-mdoc" % "2.2.5" ) -libraryDependencies += "com.github.os72" % "protoc-jar" % "3.5.1.1" +libraryDependencies += "com.github.os72" % "protoc-jar" % "3.11.4" From 6f827456c8403e2809e0ae1d28ed4342cbb0102b Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 20 Nov 2020 16:09:07 -0800 Subject: [PATCH 31/83] Helper make target to launch SBT | Move SBT_OPTS to SBT variable --- common.mk | 8 ++++++++ variables.mk | 9 +++++---- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/common.mk b/common.mk index d0b11fe3..80565a37 100644 --- a/common.mk +++ b/common.mk @@ -218,6 +218,14 @@ dramsim_lib = $(dramsim_dir)/libdramsim.a $(dramsim_lib): $(MAKE) -C $(dramsim_dir) $(notdir $@) +####################################### +# Helper to run SBT # +####################################### + +.PHONY: launch-sbt +launch-sbt: + cd $(base_dir) && $(SBT) + ######################################################################################### # print help text ######################################################################################### diff --git a/variables.mk b/variables.mk index 2828366c..42dc48c5 100644 --- a/variables.mk +++ b/variables.mk @@ -151,9 +151,6 @@ JAVA_ARGS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M ######################################################################################### # default sbt launch command ######################################################################################### -SCALA_VERSION=2.12.10 -SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION)) -SBT ?= java $(JAVA_ARGS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar # Running with sbt-launch.jar doesn't read .sbtopts by default # # Set if the file exists (if it exists, we're building chisel3 and firrtl from source) sbtopts_file := $(base_dir)/.sbtopts @@ -161,6 +158,10 @@ ifneq (,$(wildcard $(sbtopts_file))) SBT_OPTS ?= $(shell cat $(sbtopts_file)) endif +SCALA_VERSION=2.12.10 +SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION)) +SBT ?= java $(JAVA_ARGS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar $(SBT_OPTS) + BLOOP ?= bloop BLOOP_CONFIG_DIR ?= $(base_dir)/.bloop # This mirrors the bloop default. Set to a system-unique port in a multi-user environment @@ -182,7 +183,7 @@ define run_scala_main endef else define run_scala_main - cd $(base_dir) && $(SBT) $(SBT_OPTS) "project $(1)" "runMain $(2) $(3)" + cd $(base_dir) && $(SBT) "project $(1)" "runMain $(2) $(3)" endef endif From 3dfc03c31de01ec99f3b36d50c74ed4ba397f0e0 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 20 Nov 2020 17:02:59 -0800 Subject: [PATCH 32/83] Add more plugins and libdeps --- build.sbt | 7 +++++-- project/plugins.sbt | 2 +- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/build.sbt b/build.sbt index 6ac4c85e..00605b69 100644 --- a/build.sbt +++ b/build.sbt @@ -25,7 +25,9 @@ lazy val commonSettings = Seq( "org.typelevel" %% "spire" % "0.16.2", "org.scalanlp" %% "breeze" % "1.0", "org.json4s" %% "json4s-native" % "3.6.10", - "junit" % "junit" % "4.13" + "junit" % "junit" % "4.13", + "org.apache.commons" % "commons-text" % "1.8", + "net.jcazevedo" %% "moultingyaml" % "0.4.2" ), addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, @@ -98,12 +100,13 @@ lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) .settings(commonSettings) lazy val treadle = (project in file("tools/treadle")) + .dependsOn(firrtlRef) .settings(commonSettings) lazy val chisel_testers = (project in file("tools/chisel-testers")) .sourceDependency(chisel, chiselLib) .settings(addCompilerPlugin(chiselPluginLib)) - .dependsOn(firrtl_interpreter, treadle) + .dependsOn(firrtl_interpreter, treadle, firrtlRef) .settings( commonSettings, libraryDependencies ++= Seq( diff --git a/project/plugins.sbt b/project/plugins.sbt index 496deb8d..61e69a3d 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -11,7 +11,7 @@ addSbtPlugin("com.eed3si9n" % "sbt-unidoc" % "0.4.1") addSbtPlugin("org.scoverage" % "sbt-scoverage" % "1.5.1") addSbtPlugin("org.scalastyle" %% "scalastyle-sbt-plugin" % "1.0.0") addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.15.0") -addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.1") +addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.2") addSbtPlugin("com.github.gseitz" % "sbt-protobuf" % "0.6.3") addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.21") addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "0.6.1") From 9545abb65de6490b8a6e9ee760b21d131916f4cc Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 21 Nov 2020 10:40:11 -0800 Subject: [PATCH 33/83] Working elaboration (breaks during barstools FIRRTL) --- build.sbt | 45 ++++++++++++++++++++------------------------- 1 file changed, 20 insertions(+), 25 deletions(-) diff --git a/build.sbt b/build.sbt index 00605b69..968b22cd 100644 --- a/build.sbt +++ b/build.sbt @@ -27,7 +27,8 @@ lazy val commonSettings = Seq( "org.json4s" %% "json4s-native" % "3.6.10", "junit" % "junit" % "4.13", "org.apache.commons" % "commons-text" % "1.8", - "net.jcazevedo" %% "moultingyaml" % "0.4.2" + "net.jcazevedo" %% "moultingyaml" % "0.4.2", + "org.antlr" % "antlr4-runtime" % "4.7.1" ), addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, @@ -47,19 +48,6 @@ lazy val firesimDir = if (firesimAsLibrary) { file("../../sim") } -// Checks for -DROCKET_USE_MAVEN. -// If it's there, use a maven dependency. -// Else, depend on subprojects in git submodules. -def conditionalDependsOn(prj: Project): Project = { - if (sys.props.contains("ROCKET_USE_MAVEN")) { - prj.settings(Seq( - libraryDependencies += "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHOT", - )) - } else { - prj.dependsOn(testchipip) - } -} - /** * It has been a struggle for us to override settings in subprojects. * An example would be adding a dependency to rocketchip on midas's targetutils library, @@ -93,20 +81,21 @@ lazy val chiselLib = "edu.berkeley.cs" %% "chisel3" % chiselVersion // keeping scalaVersion in sync with chisel3 to the minor version lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full -lazy val firrtlRef = ProjectRef(workspaceDirectory / "firrtl", "firrtl") +lazy val firrtlRef = ProjectRef(file("tools/firrtl"), "firrtl") +lazy val firrtlLib = "edu.berkeley.cs" %% "firrtl" % "1.4-SNAPSHOT" lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) - .dependsOn(firrtlRef) + .sourceDependency(firrtlRef, firrtlLib) .settings(commonSettings) lazy val treadle = (project in file("tools/treadle")) - .dependsOn(firrtlRef) + .sourceDependency(firrtlRef, firrtlLib) .settings(commonSettings) lazy val chisel_testers = (project in file("tools/chisel-testers")) .sourceDependency(chisel, chiselLib) .settings(addCompilerPlugin(chiselPluginLib)) - .dependsOn(firrtl_interpreter, treadle, firrtlRef) + .dependsOn(firrtl_interpreter, treadle) .settings( commonSettings, libraryDependencies ++= Seq( @@ -146,24 +135,28 @@ lazy val rocketchip = freshProject("rocketchip", rocketChipDir) lazy val testchipip = (project in file("generators/testchipip")) .dependsOn(rocketchip, sifive_blocks) .settings(commonSettings) +lazy val testchipipLib = "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHOT" lazy val iocell = (project in file("./tools/barstools/iocell/")) .sourceDependency(chisel, chiselLib) .settings(addCompilerPlugin(chiselPluginLib)) .settings(commonSettings) -lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) +lazy val chipyard = (project in file("generators/chipyard")) + .sourceDependency(testchipip, testchipipLib) .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsptools`, gemmini, icenet, tracegen, cva6, nvdla, sodor) .settings(commonSettings) -lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen")) +lazy val tracegen = (project in file("generators/tracegen")) + .sourceDependency(testchipip, testchipipLib) .dependsOn(rocketchip, sifive_cache, boom, utilities) .settings(commonSettings) -lazy val utilities = conditionalDependsOn(project in file("generators/utilities")) +lazy val utilities = (project in file("generators/utilities")) + .sourceDependency(testchipip, testchipipLib) .settings(commonSettings) lazy val icenet = (project in file("generators/icenet")) @@ -174,7 +167,8 @@ lazy val hwacha = (project in file("generators/hwacha")) .dependsOn(rocketchip) .settings(commonSettings) -lazy val boom = conditionalDependsOn(project in file("generators/boom")) +lazy val boom = (project in file("generators/boom")) + .sourceDependency(testchipip, testchipipLib) .dependsOn(rocketchip) .settings(commonSettings) @@ -198,8 +192,8 @@ lazy val nvdla = (project in file("generators/nvdla")) .dependsOn(rocketchip) .settings(commonSettings) -lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/")) - .dependsOn(chisel_testers, chipyard) +lazy val tapeout = (project in file("./tools/barstools/tapeout/")) + .dependsOn(chisel_testers, chipyard) // must depend on chipyard to get scala resources .settings(commonSettings) .settings(libraryDependencies ++= Seq("io.github.daviddenton" %% "handlebars-scala-fork" % "2.3.0")) @@ -238,7 +232,8 @@ lazy val sifive_cache = (project in file("generators/sifive-cache")).settings( lazy val midas = ProjectRef(firesimDir, "midas") lazy val firesimLib = ProjectRef(firesimDir, "firesimLib") -lazy val firechip = conditionalDependsOn(project in file("generators/firechip")) +lazy val firechip = (project in file("generators/firechip")) + .sourceDependency(testchipip, testchipipLib) .dependsOn(chipyard, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") .settings( commonSettings, From 94c85c70bbe173077d1665190ccf1e3863bfeb4e Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Mon, 16 Nov 2020 10:37:23 -0800 Subject: [PATCH 34/83] bump IceNet for input/output tap and checksum fixes --- generators/icenet | 2 +- software/firemarshal | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/icenet b/generators/icenet index 277a9080..c14e5a02 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit 277a9080fe92afb25d942f3207252e0ddea1b864 +Subproject commit c14e5a02a7e4fee4d59b6cb0c1087976aba3fe14 diff --git a/software/firemarshal b/software/firemarshal index 45aebace..199f23ed 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit 45aebace86d3a46c357337a19d4c8e894a5d0ed4 +Subproject commit 199f23ed74f723313b3bf225a9b4cfed8b6f6399 From 71a3ea8abcacd9907b3a1bcc4e2588b6905526fa Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 24 Nov 2020 16:44:20 -0800 Subject: [PATCH 35/83] Allow custom verilator optimization flags --- sims/verilator/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 65e64179..2b250ee9 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -84,7 +84,7 @@ TRACING_CFLAGS := $(if $(filter $(VERILATOR_FST_MODE),0),,-DCY_FST_TRACE) #---------------------------------------------------------------------------------------- # we initially had --noassert for performance, but several modules use # assertions, including dramsim, so we enable --assert by default -VERILATOR_OPT_FLAGS := \ +VERILATOR_OPT_FLAGS ?= \ -O3 \ --x-assign fast \ --x-initial fast \ From c223f18f73f932f26ccba5782a470a09ad94032e Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 25 Nov 2020 20:57:17 -0800 Subject: [PATCH 36/83] Bump barstools --- tools/barstools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/barstools b/tools/barstools index 845af06b..9be550e2 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 845af06b1515c69b1d788726134e92b808bf45e4 +Subproject commit 9be550e23d2f6a2968f35719ba55edb8aefaf138 From 8a46d4a1ea7032bf0442d743b77d8e553419c1b7 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 27 Nov 2020 17:34:48 -0800 Subject: [PATCH 37/83] Bump BOOM and Barstools --- generators/boom | 2 +- tools/barstools | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/boom b/generators/boom index 2dfec3d0..f3a30168 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 2dfec3d012e61ff07108af6034a86e60979deecd +Subproject commit f3a301689e8ceee54f247a6c0913d28454bd376a diff --git a/tools/barstools b/tools/barstools index 9be550e2..fa699af0 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 9be550e23d2f6a2968f35719ba55edb8aefaf138 +Subproject commit fa699af02635681c8af90f2169a6705fe5e3e37a From 60e834c812b40c2317715f0a4cd6135436c2b448 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 28 Nov 2020 16:01:35 -0800 Subject: [PATCH 38/83] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index f89d746a..5e64d783 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit f89d746aa3c0c35c78a883c22c58679aeb9e2030 +Subproject commit 5e64d78300a2e5316878af862447c84cee9f6c12 From b7ed614b1968de05c49f3c258867211cfe20b3a6 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 30 Nov 2020 21:22:55 -0800 Subject: [PATCH 39/83] Attempt at "fixing" build.sbt | Bump sub-projects --- build.sbt | 202 +++++++++++++++++++++++++++++------------- generators/boom | 2 +- generators/cva6 | 2 +- generators/gemmini | 2 +- generators/sha3 | 2 +- generators/testchipip | 2 +- project/plugins.sbt | 6 -- sims/firesim | 2 +- tools/barstools | 2 +- tools/dsptools | 2 +- 10 files changed, 147 insertions(+), 77 deletions(-) diff --git a/build.sbt b/build.sbt index 968b22cd..01655abc 100644 --- a/build.sbt +++ b/build.sbt @@ -14,25 +14,22 @@ lazy val commonSettings = Seq( case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard case _ => MergeStrategy.first}}, scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"), - libraryDependencies ++= Seq( - "org.scalatest" %% "scalatest" % "3.2.2" % "test", - "org.scalatestplus" %% "scalacheck-1-14" % "3.1.1.1" % "test", - "org.json4s" %% "json4s-jackson" % "3.6.10", - "org.scala-lang" % "scala-reflect" % scalaVersion.value, - "com.github.scopt" %% "scopt" % "3.7.1", - "org.scala-lang.modules" % "scala-jline" % "2.12.1", - "com.typesafe.play" %% "play-json" % "2.6.10", - "org.typelevel" %% "spire" % "0.16.2", - "org.scalanlp" %% "breeze" % "1.0", - "org.json4s" %% "json4s-native" % "3.6.10", - "junit" % "junit" % "4.13", - "org.apache.commons" % "commons-text" % "1.8", - "net.jcazevedo" %% "moultingyaml" % "0.4.2", - "org.antlr" % "antlr4-runtime" % "4.7.1" - ), - addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), + addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), // TODO: Needed for just Rocket? unmanagedBase := (chipyardRoot / unmanagedBase).value, - allDependencies := allDependencies.value.filterNot(_.organization == "edu.berkeley.cs"), + allDependencies := { + // drop dependencies (org, name) + val dropDeps = Seq( + ("edu.berkeley.cs", "firrtl"), + ("edu.berkeley.cs", "chisel3"), + ("edu.berkeley.cs", "rocketchip"), + ("edu.berkeley.cs", "chisel-iotesters"), + ("edu.berkeley.cs", "treadle"), + ("edu.berkeley.cs", "firrtl-interpreter")) + + allDependencies.value.filterNot { dep => + dropDeps.contains((dep.organization, dep.name)) + } + }, exportJars := true, resolvers ++= Seq( Resolver.sonatypeRepo("snapshots"), @@ -73,86 +70,135 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => // Subproject definitions begin +// -- Rocket Chip -- + val chiselVersion = "3.4.0" -lazy val chisel = (project in file("tools/chisel3")) +lazy val chiselRef = ProjectRef(workspaceDirectory / "chisel3", "chisel") lazy val chiselLib = "edu.berkeley.cs" %% "chisel3" % chiselVersion +lazy val chiselLibDeps = (chiselRef / Keys.libraryDependencies) // While not built from source, *must* be in sync with the chisel3 git submodule // Building from source requires extending sbt-sriracha or a similar plugin and // keeping scalaVersion in sync with chisel3 to the minor version lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full -lazy val firrtlRef = ProjectRef(file("tools/firrtl"), "firrtl") -lazy val firrtlLib = "edu.berkeley.cs" %% "firrtl" % "1.4-SNAPSHOT" - -lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) - .sourceDependency(firrtlRef, firrtlLib) - .settings(commonSettings) - -lazy val treadle = (project in file("tools/treadle")) - .sourceDependency(firrtlRef, firrtlLib) - .settings(commonSettings) - -lazy val chisel_testers = (project in file("tools/chisel-testers")) - .sourceDependency(chisel, chiselLib) - .settings(addCompilerPlugin(chiselPluginLib)) - .dependsOn(firrtl_interpreter, treadle) - .settings( - commonSettings, - libraryDependencies ++= Seq( - "junit" % "junit" % "4.13", - "org.scalatest" %% "scalatest" % "3.2.2", - "org.scalatestplus" %% "scalacheck-1-14" % "3.1.1.1", - "org.scalacheck" %% "scalacheck" % "1.14.3", - "com.github.scopt" %% "scopt" % "3.7.1" - )) - -// Contains annotations & firrtl passes you may wish to use in rocket-chip without -// introducing a circular dependency between RC and MIDAS -lazy val midasTargetUtils = ProjectRef(firesimDir, "targetutils") +val firrtlVersion = "1.4-SNAPSHOT" +lazy val firrtlRef = ProjectRef(workspaceDirectory / "firrtl", "firrtl") +lazy val firrtlLib = "edu.berkeley.cs" %% "firrtl" % firrtlVersion +//lazy val firrtlLibDeps = (firrtlRef / Keys.libraryDependencies) // TODO: Won't work because of antlr plugin +lazy val firrtlLibDeps = Seq( + "org.scalatest" %% "scalatest" % "3.2.0" % "test", + "org.scalatestplus" %% "scalacheck-1-14" % "3.1.3.0" % "test", + "com.github.scopt" %% "scopt" % "3.7.1", + "net.jcazevedo" %% "moultingyaml" % "0.4.2", + "org.json4s" %% "json4s-native" % "3.6.9", + "org.apache.commons" % "commons-text" % "1.8", + "org.antlr" % "antlr4-runtime" % "4.7.1" +) // Rocket-chip dependencies (subsumes making RC a RootProject) lazy val hardfloat = (project in rocketChipDir / "hardfloat") + .sourceDependency(chiselRef, chiselLib) + .settings(addCompilerPlugin(chiselPluginLib)) + .settings(libraryDependencies ++= chiselLibDeps.value) .dependsOn(midasTargetUtils) .settings(commonSettings) + .settings( + libraryDependencies ++= Seq( + "org.scala-lang" % "scala-reflect" % scalaVersion.value, + "org.json4s" %% "json4s-jackson" % "3.6.1", + "org.scalatest" %% "scalatest" % "3.2.0" % "test" + ) + ) lazy val rocketMacros = (project in rocketChipDir / "macros") .settings(commonSettings) + .settings( + libraryDependencies ++= Seq( + "org.scala-lang" % "scala-reflect" % scalaVersion.value, + "org.json4s" %% "json4s-jackson" % "3.6.1", + "org.scalatest" %% "scalatest" % "3.2.0" % "test" + ) + ) lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/build-rules/sbt") .settings(commonSettings) + .settings( + libraryDependencies ++= Seq( + "org.scala-lang" % "scala-reflect" % scalaVersion.value, + "org.json4s" %% "json4s-jackson" % "3.6.1", + "org.scalatest" %% "scalatest" % "3.2.0" % "test" + ) + ) lazy val rocketchip = freshProject("rocketchip", rocketChipDir) - .sourceDependency(chisel, chiselLib) + .sourceDependency(chiselRef, chiselLib) .settings(addCompilerPlugin(chiselPluginLib)) + .settings(libraryDependencies ++= chiselLibDeps.value) .dependsOn(hardfloat, rocketMacros, rocketConfig) .settings(commonSettings) + .settings( + libraryDependencies ++= Seq( + "org.scala-lang" % "scala-reflect" % scalaVersion.value, + "org.json4s" %% "json4s-jackson" % "3.6.1", + "org.scalatest" %% "scalatest" % "3.2.0" % "test" + ) + ) .settings( // Settings for scalafix semanticdbEnabled := true, semanticdbVersion := scalafixSemanticdb.revision, scalacOptions += "-Ywarn-unused-import" ) +lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies) + +// -- "Problematic" Projects -- + +lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) + .sourceDependency(firrtlRef, firrtlLib) + .settings(libraryDependencies ++= firrtlLibDeps) + .settings(commonSettings) +lazy val firrtlInterpreterLibDeps = (firrtl_interpreter / Keys.libraryDependencies) + +lazy val treadle = (project in file("tools/treadle")) + .sourceDependency(firrtlRef, firrtlLib) + .settings(libraryDependencies ++= firrtlLibDeps) + .settings(commonSettings) +lazy val treadleLibDeps = (treadle / Keys.libraryDependencies) + +lazy val chisel_testers = (project in file("tools/chisel-testers")) + .sourceDependency(chiselRef, chiselLib) + .settings(addCompilerPlugin(chiselPluginLib)) + .settings(libraryDependencies ++= chiselLibDeps.value) + .dependsOn(firrtl_interpreter, treadle) + .settings(libraryDependencies ++= firrtlInterpreterLibDeps.value) + .settings(libraryDependencies ++= treadleLibDeps.value) + .settings(commonSettings) +lazy val chiselTestersLibDeps = (chisel_testers / Keys.libraryDependencies) + +// -- UCB-controlled Projects -- + +// Contains annotations & firrtl passes you may wish to use in rocket-chip without +// introducing a circular dependency between RC and MIDAS +lazy val midasTargetUtils = ProjectRef(firesimDir, "targetutils") lazy val testchipip = (project in file("generators/testchipip")) .dependsOn(rocketchip, sifive_blocks) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val testchipipLib = "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHOT" -lazy val iocell = (project in file("./tools/barstools/iocell/")) - .sourceDependency(chisel, chiselLib) - .settings(addCompilerPlugin(chiselPluginLib)) - .settings(commonSettings) - lazy val chipyard = (project in file("generators/chipyard")) .sourceDependency(testchipip, testchipipLib) - .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, + .dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsptools`, gemmini, icenet, tracegen, cva6, nvdla, sodor) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val tracegen = (project in file("generators/tracegen")) .sourceDependency(testchipip, testchipipLib) .dependsOn(rocketchip, sifive_cache, boom, utilities) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val utilities = (project in file("generators/utilities")) @@ -160,73 +206,103 @@ lazy val utilities = (project in file("generators/utilities")) .settings(commonSettings) lazy val icenet = (project in file("generators/icenet")) - .dependsOn(rocketchip, testchipip) + .sourceDependency(testchipip, testchipipLib) + .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val hwacha = (project in file("generators/hwacha")) .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val boom = (project in file("generators/boom")) .sourceDependency(testchipip, testchipipLib) .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val cva6 = (project in file("generators/cva6")) .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val sodor = (project in file("generators/riscv-sodor")) .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val sha3 = (project in file("generators/sha3")) .dependsOn(rocketchip, chisel_testers, midasTargetUtils) + .settings(libraryDependencies ++= rocketLibDeps.value) + .settings(libraryDependencies ++= chiselTestersLibDeps.value) .settings(commonSettings) lazy val gemmini = (project in file("generators/gemmini")) - .dependsOn(rocketchip, chisel_testers, testchipip) + .sourceDependency(testchipip, testchipipLib) + .dependsOn(rocketchip, chisel_testers) + .settings(libraryDependencies ++= rocketLibDeps.value) + .settings(libraryDependencies ++= chiselTestersLibDeps.value) .settings(commonSettings) lazy val nvdla = (project in file("generators/nvdla")) .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) + .settings(commonSettings) + +lazy val iocell = (project in file("./tools/barstools/iocell/")) + .sourceDependency(chiselRef, chiselLib) + .settings(addCompilerPlugin(chiselPluginLib)) + .settings(libraryDependencies ++= chiselLibDeps.value) .settings(commonSettings) lazy val tapeout = (project in file("./tools/barstools/tapeout/")) .dependsOn(chisel_testers, chipyard) // must depend on chipyard to get scala resources + .settings(libraryDependencies ++= chiselTestersLibDeps.value) .settings(commonSettings) - .settings(libraryDependencies ++= Seq("io.github.daviddenton" %% "handlebars-scala-fork" % "2.3.0")) lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/")) .settings(commonSettings) lazy val barstoolsMacros = (project in file("./tools/barstools/macros/")) - .dependsOn(firrtl_interpreter, mdf, rocketchip) + .sourceDependency(chiselRef, chiselLib) + .settings(addCompilerPlugin(chiselPluginLib)) + .settings(libraryDependencies ++= chiselLibDeps.value) + .dependsOn(firrtl_interpreter, mdf, chisel_testers) + .settings(libraryDependencies ++= chiselTestersLibDeps.value) + .settings(libraryDependencies ++= firrtlInterpreterLibDeps.value) .enablePlugins(sbtassembly.AssemblyPlugin) .settings(commonSettings) lazy val dsptools = freshProject("dsptools", file("./tools/dsptools")) .dependsOn(chisel_testers) + .settings(libraryDependencies ++= chiselTestersLibDeps.value) .settings( commonSettings, libraryDependencies ++= Seq( + "org.typelevel" %% "spire" % "0.16.2", + "org.scalanlp" %% "breeze" % "1.1", "junit" % "junit" % "4.13" % "test", - "org.scalatest" %% "scalatest" % "3.2.2", - "org.scalacheck" %% "scalacheck" % "1.14.3" % "test" + "org.scalatest" %% "scalatest" % "3.0.+" % "test", + "org.scalacheck" %% "scalacheck" % "1.14.3" % "test", )) lazy val `rocket-dsptools` = freshProject("rocket-dsptools", file("./tools/dsptools/rocket")) .dependsOn(rocketchip, dsptools) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val sifive_blocks = (project in file("generators/sifive-blocks")) .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) -lazy val sifive_cache = (project in file("generators/sifive-cache")).settings( +lazy val sifive_cache = (project in file("generators/sifive-cache")) + .settings( commonSettings, - scalaSource in Compile := baseDirectory.value / "design/craft" - ).dependsOn(rocketchip) + scalaSource in Compile := baseDirectory.value / "design/craft") + .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) // Library components of FireSim lazy val midas = ProjectRef(firesimDir, "midas") diff --git a/generators/boom b/generators/boom index f3a30168..6198e335 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit f3a301689e8ceee54f247a6c0913d28454bd376a +Subproject commit 6198e33545f2ec2c70a6ac9afba78c7023e9605b diff --git a/generators/cva6 b/generators/cva6 index c2b9fc41..d40a8f5c 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit c2b9fc412179a386fb4b662d13e588a9613f41d5 +Subproject commit d40a8f5c844f4169c8e74d3fa05f36286f9e4bb6 diff --git a/generators/gemmini b/generators/gemmini index 371bc330..eb719930 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 371bc33038e633779f52e26eaa0031f2820c2f0d +Subproject commit eb7199307d3adf994c78b02a54859f3e37ac7012 diff --git a/generators/sha3 b/generators/sha3 index a4ea9602..74e41f57 160000 --- a/generators/sha3 +++ b/generators/sha3 @@ -1 +1 @@ -Subproject commit a4ea960248fdf8267b515723d472b018b09ac24f +Subproject commit 74e41f579213549501ccf292d101f9db73ee2347 diff --git a/generators/testchipip b/generators/testchipip index 03af7aa5..6fbb1b77 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 03af7aa53988dd96dffd613d1d50a5c6661e0a82 +Subproject commit 6fbb1b77b90da5e88bfde8e504595a332cca0e0b diff --git a/project/plugins.sbt b/project/plugins.sbt index 61e69a3d..fa2a1a57 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -1,7 +1,3 @@ -resolvers += Resolver.url("scalasbt", new URL("https://scalasbt.artifactoryonline.com/scalasbt/sbt-plugin-releases")) (Resolver.ivyStylePatterns) -resolvers += Classpaths.sbtPluginReleases -resolvers += "jgit-repo" at "https://download.eclipse.org/jgit/maven" - addSbtPlugin("net.virtual-void" % "sbt-dependency-graph" % "0.9.2") addSbtPlugin("com.typesafe.sbt" % "sbt-ghpages" % "0.6.2") addSbtPlugin("com.typesafe.sbt" % "sbt-site" % "1.3.1") @@ -18,5 +14,3 @@ addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "0.6.1") addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.1") addSbtPlugin("com.eed3si9n" % "sbt-sriracha" % "0.1.0") addSbtPlugin("org.scalameta" % "sbt-mdoc" % "2.2.5" ) - -libraryDependencies += "com.github.os72" % "protoc-jar" % "3.11.4" diff --git a/sims/firesim b/sims/firesim index 5e64d783..4752009e 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 5e64d78300a2e5316878af862447c84cee9f6c12 +Subproject commit 4752009e98fdd0b1848c6a3cde21fee331885939 diff --git a/tools/barstools b/tools/barstools index fa699af0..3a29f535 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit fa699af02635681c8af90f2169a6705fe5e3e37a +Subproject commit 3a29f535726a191d09164470eb1ce1a1ddd5bf9a diff --git a/tools/dsptools b/tools/dsptools index 74612fd7..27304bde 160000 --- a/tools/dsptools +++ b/tools/dsptools @@ -1 +1 @@ -Subproject commit 74612fd76645bfcfcc1c711ed43025cb8105e539 +Subproject commit 27304bdeae3e4fb969c7cac1e0bda358be7cdb12 From 5bc7e6cd685428d50a8bd28ee1e97dfda730577c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 1 Dec 2020 22:28:23 -0800 Subject: [PATCH 40/83] Support SBT thin client | Rename JAVA_ARGS -> OPTS | Support env. SBT_OPTS --- .gitignore | 1 + .sbtopts | 2 -- build.sbt | 2 +- common.mk | 14 +++++++++----- project/build.properties | 2 +- variables.mk | 21 +++++++++++---------- 6 files changed, 23 insertions(+), 19 deletions(-) delete mode 100644 .sbtopts diff --git a/.gitignore b/.gitignore index a85d0dd2..153e7275 100644 --- a/.gitignore +++ b/.gitignore @@ -20,3 +20,4 @@ tags env-riscv-tools.sh env-esp-tools.sh .bloop/ +.bsp/ diff --git a/.sbtopts b/.sbtopts deleted file mode 100644 index 2358d787..00000000 --- a/.sbtopts +++ /dev/null @@ -1,2 +0,0 @@ --Dsbt.sourcemode=true --Dsbt.workspace=$PWD/tools diff --git a/build.sbt b/build.sbt index 01655abc..1132dde1 100644 --- a/build.sbt +++ b/build.sbt @@ -81,7 +81,7 @@ lazy val chiselLibDeps = (chiselRef / Keys.libraryDependencies) // keeping scalaVersion in sync with chisel3 to the minor version lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full -val firrtlVersion = "1.4-SNAPSHOT" +val firrtlVersion = "1.4.+" lazy val firrtlRef = ProjectRef(workspaceDirectory / "firrtl", "firrtl") lazy val firrtlLib = "edu.berkeley.cs" %% "firrtl" % firrtlVersion //lazy val firrtlLibDeps = (firrtlRef / Keys.libraryDependencies) // TODO: Won't work because of antlr plugin diff --git a/common.mk b/common.mk index 80565a37..4f632a26 100644 --- a/common.mk +++ b/common.mk @@ -63,7 +63,7 @@ SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala) VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v) # This assumes no SBT meta-build sources SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools) -SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt +SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt $(base_dir)/project/build.properties ######################################################################################### # Bloop Project Definitions @@ -209,7 +209,7 @@ ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),) endif ####################################### -# Rules for building DRAMSim2 library # +# Rules for building DRAMSim2 library ####################################### dramsim_dir = $(base_dir)/tools/DRAMSim2 @@ -218,14 +218,18 @@ dramsim_lib = $(dramsim_dir)/libdramsim.a $(dramsim_lib): $(MAKE) -C $(dramsim_dir) $(notdir $@) -####################################### -# Helper to run SBT # -####################################### +################################################ +# Helper to run SBT or shutdown the SBT server +################################################ .PHONY: launch-sbt launch-sbt: cd $(base_dir) && $(SBT) +.PHONY: launch-sbt +shutdown-sbt: + cd $(base_dir) && $(SBT) shutdown + ######################################################################################### # print help text ######################################################################################### diff --git a/project/build.properties b/project/build.properties index 0837f7a1..7de0a938 100644 --- a/project/build.properties +++ b/project/build.properties @@ -1 +1 @@ -sbt.version=1.3.13 +sbt.version=1.4.4 diff --git a/variables.mk b/variables.mk index 42dc48c5..73918376 100644 --- a/variables.mk +++ b/variables.mk @@ -146,21 +146,22 @@ sim_common_files ?= $(build_dir)/sim_files.common.f # java arguments used in sbt ######################################################################################### JAVA_HEAP_SIZE ?= 8G -JAVA_ARGS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M +JAVA_OPTS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M ######################################################################################### # default sbt launch command ######################################################################################### -# Running with sbt-launch.jar doesn't read .sbtopts by default -# # Set if the file exists (if it exists, we're building chisel3 and firrtl from source) -sbtopts_file := $(base_dir)/.sbtopts -ifneq (,$(wildcard $(sbtopts_file))) - SBT_OPTS ?= $(shell cat $(sbtopts_file)) +# by default build chisel3/firrtl and other subprojects from source +override SBT_OPTS += -Dsbt.sourcemode=true -Dsbt.workspace=$(base_dir)/tools + +ifdef ENABLE_SBT_THIN_CLIENT +# enabling speeds up sbt loading +# however if build.sbt changes are done you need to +# "shutdown" the server (shutdown-sbt target) to reload build.sbt changes +SBT_CLIENT_FLAG = --client endif -SCALA_VERSION=2.12.10 -SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION)) -SBT ?= java $(JAVA_ARGS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar $(SBT_OPTS) +SBT ?= java $(JAVA_OPTS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar $(SBT_OPTS) $(SBT_CLIENT_FLAG) BLOOP ?= bloop BLOOP_CONFIG_DIR ?= $(base_dir)/.bloop @@ -183,7 +184,7 @@ define run_scala_main endef else define run_scala_main - cd $(base_dir) && $(SBT) "project $(1)" "runMain $(2) $(3)" + cd $(base_dir) && $(SBT) ";project $(1); runMain $(2) $(3)" endef endif From 4e53dc1e663560131f5b12fb0dcd7079a0dd0bdc Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 2 Dec 2020 12:18:12 -0800 Subject: [PATCH 41/83] Cleanly reload proj. defs. with thin client support --- .gitignore | 1 + common.mk | 18 +++++++++++++++--- variables.mk | 7 +++++-- 3 files changed, 21 insertions(+), 5 deletions(-) diff --git a/.gitignore b/.gitignore index 153e7275..77b9eb6c 100644 --- a/.gitignore +++ b/.gitignore @@ -21,3 +21,4 @@ env-riscv-tools.sh env-esp-tools.sh .bloop/ .bsp/ +*_TIMESTAMP diff --git a/common.mk b/common.mk index 4f632a26..f149d1ae 100644 --- a/common.mk +++ b/common.mk @@ -69,9 +69,20 @@ SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $ # Bloop Project Definitions ######################################################################################### $(BLOOP_CONFIG_DIR)/TIMESTAMP: $(SBT_SOURCES) - cd $(base_dir) && $(SBT) "project chipyardRoot" "bloopInstall" + cd $(base_dir) && $(SBT) ";project chipyardRoot; bloopInstall" touch $@ +######################################################################################### +# SBT Server Setup (needed to rebuild project correctly) +######################################################################################### +$(SBT_THIN_CLIENT_TIMESTAMP): $(SBT_SOURCES) +ifneq (,$(wildcard $(SBT_THIN_CLIENT_TIMESTAMP))) + cd $(base_dir) && $(SBT) "reload" + touch $@ +else + touch $@ +endif + ######################################################################################### # create list of simulation file inputs ######################################################################################### @@ -226,9 +237,10 @@ $(dramsim_lib): launch-sbt: cd $(base_dir) && $(SBT) -.PHONY: launch-sbt +.PHONY: shutdown-sbt shutdown-sbt: - cd $(base_dir) && $(SBT) shutdown + cd $(base_dir) && $(SBT) "shutdown" + rm -rf $(SBT_THIN_CLIENT_TIMESTAMP) ######################################################################################### # print help text diff --git a/variables.mk b/variables.mk index 73918376..731b7e1e 100644 --- a/variables.mk +++ b/variables.mk @@ -154,7 +154,12 @@ JAVA_OPTS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M # by default build chisel3/firrtl and other subprojects from source override SBT_OPTS += -Dsbt.sourcemode=true -Dsbt.workspace=$(base_dir)/tools +SCALA_BUILDTOOL_DEPS = $(SBT_SOURCES) + +SBT_THIN_CLIENT_TIMESTAMP = $(base_dir)/SBT_TIMESTAMP + ifdef ENABLE_SBT_THIN_CLIENT +override SCALA_BUILDTOOL_DEPS += $(SBT_THIN_CLIENT_TIMESTAMP) # enabling speeds up sbt loading # however if build.sbt changes are done you need to # "shutdown" the server (shutdown-sbt target) to reload build.sbt changes @@ -168,8 +173,6 @@ BLOOP_CONFIG_DIR ?= $(base_dir)/.bloop # This mirrors the bloop default. Set to a system-unique port in a multi-user environment BLOOP_NAILGUN_PORT ?= 8212 -SCALA_BUILDTOOL_DEPS = $(SBT_SOURCES) - ifdef ENABLE_BLOOP override SCALA_BUILDTOOL_DEPS += $(BLOOP_CONFIG_DIR)/TIMESTAMP # Two notes about the bloop invocation: From a0e2dcfc4ecddeaa79c3cb8904b6b2de4e397435 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 2 Dec 2020 14:46:46 -0800 Subject: [PATCH 42/83] Remove support for bloop --- .gitignore | 1 - common.mk | 7 ------- project/plugins.sbt | 1 - variables.mk | 19 ------------------- 4 files changed, 28 deletions(-) diff --git a/.gitignore b/.gitignore index 77b9eb6c..a80f88ab 100644 --- a/.gitignore +++ b/.gitignore @@ -19,6 +19,5 @@ tags *~ env-riscv-tools.sh env-esp-tools.sh -.bloop/ .bsp/ *_TIMESTAMP diff --git a/common.mk b/common.mk index f149d1ae..159e7ea6 100644 --- a/common.mk +++ b/common.mk @@ -65,13 +65,6 @@ VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools) SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt $(base_dir)/project/build.properties -######################################################################################### -# Bloop Project Definitions -######################################################################################### -$(BLOOP_CONFIG_DIR)/TIMESTAMP: $(SBT_SOURCES) - cd $(base_dir) && $(SBT) ";project chipyardRoot; bloopInstall" - touch $@ - ######################################################################################### # SBT Server Setup (needed to rebuild project correctly) ######################################################################################### diff --git a/project/plugins.sbt b/project/plugins.sbt index fa2a1a57..7e6f3aa8 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -11,6 +11,5 @@ addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.2") addSbtPlugin("com.github.gseitz" % "sbt-protobuf" % "0.6.3") addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.21") addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "0.6.1") -addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.1") addSbtPlugin("com.eed3si9n" % "sbt-sriracha" % "0.1.0") addSbtPlugin("org.scalameta" % "sbt-mdoc" % "2.2.5" ) diff --git a/variables.mk b/variables.mk index 731b7e1e..6cc87bfc 100644 --- a/variables.mk +++ b/variables.mk @@ -168,28 +168,9 @@ endif SBT ?= java $(JAVA_OPTS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar $(SBT_OPTS) $(SBT_CLIENT_FLAG) -BLOOP ?= bloop -BLOOP_CONFIG_DIR ?= $(base_dir)/.bloop -# This mirrors the bloop default. Set to a system-unique port in a multi-user environment -BLOOP_NAILGUN_PORT ?= 8212 - -ifdef ENABLE_BLOOP -override SCALA_BUILDTOOL_DEPS += $(BLOOP_CONFIG_DIR)/TIMESTAMP -# Two notes about the bloop invocation: -# 1) the sed removes a leading {file:} that sometimes needs to be -# provided to SBT when a project but not for bloop. -# 2) Generally, one could could pass '--' to indicate all remaining arguments are -# destined for the scala Main, however a bug in Bloop's argument parsing causes the -# --nailgun-port argument to be lost in this case. Workaround this by prefixing -# every main-destined argument with "--args" -define run_scala_main - cd $(base_dir) && bloop --nailgun-port $(BLOOP_NAILGUN_PORT) run $(shell echo $(1) | sed 's/{.*}//') --main $(2) $(addprefix --args ,$3) -endef -else define run_scala_main cd $(base_dir) && $(SBT) ";project $(1); runMain $(2) $(3)" endef -endif FIRRTL_LOGLEVEL ?= error From 08f3dbc1d07580af3c94bb1f59290a866abb1fc0 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 2 Dec 2020 14:51:49 -0800 Subject: [PATCH 43/83] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 4752009e..bf05870d 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 4752009e98fdd0b1848c6a3cde21fee331885939 +Subproject commit bf05870d225564772c44cf5505a40b1a742aa5f7 From 145885390f4a6cdbe9a5cf76bc35aa92c1458d71 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 2 Dec 2020 15:08:06 -0800 Subject: [PATCH 44/83] Bump Hwacha --- generators/hwacha | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/hwacha b/generators/hwacha index e0109674..b67d8ed0 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit e0109674572f4b40641a89db9e0429e51b5cb73a +Subproject commit b67d8ed06172c2ecd76807d3ef2bd5c79903f182 From 3bc1bdb841b55b4d97ebba8fc6abd588c7ddab47 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 2 Dec 2020 15:49:35 -0800 Subject: [PATCH 45/83] Bump BOOM | Split JAVA/SBT options in CI --- .circleci/defaults.sh | 3 ++- .circleci/do-rtl-build.sh | 2 +- .circleci/run-firesim-scala-tests.sh | 2 +- generators/boom | 2 +- 4 files changed, 5 insertions(+), 4 deletions(-) diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index e9ccdfb5..02558101 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -33,8 +33,9 @@ REMOTE_ESP_DIR=$REMOTE_WORK_DIR/esp-tools-install REMOTE_CHIPYARD_DIR=$REMOTE_WORK_DIR/chipyard REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator REMOTE_FIRESIM_DIR=$REMOTE_CHIPYARD_DIR/sims/firesim/sim +REMOTE_JAVA_OPTS="-Xmx9G -Xss8M" # Disable the supershell to greatly improve the readability of SBT output when captured by Circle CI -REMOTE_JAVA_ARGS="-Xmx9G -Xss8M -Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" +REMOTE_SBT_ARGS="-Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" REMOTE_VERILATOR_DIR=$REMOTE_PREFIX-$CIRCLE_SHA1-verilator-install # local variables (aka within the docker container) diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index 784dbc04..1e065437 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -63,7 +63,7 @@ do export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ - make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR FIRRTL_LOGLEVEL=info JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$key]}" + make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR FIRRTL_LOGLEVEL=info JAVA_OPTS=\"$REMOTE_JAVA_OPTS\" SBT_OPTS=\"$REMOTE_SBT_OPTS\" ${mapping[$key]}" done run "rm -rf $REMOTE_CHIPYARD_DIR/project" diff --git a/.circleci/run-firesim-scala-tests.sh b/.circleci/run-firesim-scala-tests.sh index 8080a484..a2525297 100755 --- a/.circleci/run-firesim-scala-tests.sh +++ b/.circleci/run-firesim-scala-tests.sh @@ -49,4 +49,4 @@ run "export RISCV=\"$TOOLS_DIR\"; \ export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ - make -C $REMOTE_FIRESIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" testOnly ${mapping[$1]}" + make -C $REMOTE_FIRESIM_DIR JAVA_OPTS=\"$REMOTE_JAVA_OPTS\" SBT_OPTS=\"$REMOTE_SBT_OPTS\" testOnly ${mapping[$1]}" diff --git a/generators/boom b/generators/boom index 6198e335..a53372fc 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 6198e33545f2ec2c70a6ac9afba78c7023e9605b +Subproject commit a53372fcff4c1095a513eb8bb6e8a2b9cdb971a0 From eee0d58b5d6a8b368457873bd0fbc8b8f4b63d72 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 2 Dec 2020 15:53:11 -0800 Subject: [PATCH 46/83] Cleanup comment --- variables.mk | 2 -- 1 file changed, 2 deletions(-) diff --git a/variables.mk b/variables.mk index 6cc87bfc..c8f72b3f 100644 --- a/variables.mk +++ b/variables.mk @@ -161,8 +161,6 @@ SBT_THIN_CLIENT_TIMESTAMP = $(base_dir)/SBT_TIMESTAMP ifdef ENABLE_SBT_THIN_CLIENT override SCALA_BUILDTOOL_DEPS += $(SBT_THIN_CLIENT_TIMESTAMP) # enabling speeds up sbt loading -# however if build.sbt changes are done you need to -# "shutdown" the server (shutdown-sbt target) to reload build.sbt changes SBT_CLIENT_FLAG = --client endif From 41c710b6c8c4391381caffdea8509f7dcfdc77ba Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 2 Dec 2020 16:11:09 -0800 Subject: [PATCH 47/83] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index bf05870d..10f9e7ef 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit bf05870d225564772c44cf5505a40b1a742aa5f7 +Subproject commit 10f9e7efe0b4f532037575e114b8b5fbfb47d211 From d19bcaa765e4e0cf246fa4065ffbc70bacad0d25 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 2 Dec 2020 16:42:52 -0800 Subject: [PATCH 48/83] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 10f9e7ef..593596c5 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 10f9e7efe0b4f532037575e114b8b5fbfb47d211 +Subproject commit 593596c5a854f69d28d0c3b9389175a03fa4c696 From 7f9cd0f012e143229fc5022dd4f380b9ba772583 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 2 Dec 2020 21:51:58 -0800 Subject: [PATCH 49/83] Bump FireSim | CI Fix Attempt: Increase heap --- .circleci/defaults.sh | 2 +- sims/firesim | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 02558101..015aaee7 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -33,7 +33,7 @@ REMOTE_ESP_DIR=$REMOTE_WORK_DIR/esp-tools-install REMOTE_CHIPYARD_DIR=$REMOTE_WORK_DIR/chipyard REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator REMOTE_FIRESIM_DIR=$REMOTE_CHIPYARD_DIR/sims/firesim/sim -REMOTE_JAVA_OPTS="-Xmx9G -Xss8M" +REMOTE_JAVA_OPTS="-Xmx10G -Xss8M" # Disable the supershell to greatly improve the readability of SBT output when captured by Circle CI REMOTE_SBT_ARGS="-Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" REMOTE_VERILATOR_DIR=$REMOTE_PREFIX-$CIRCLE_SHA1-verilator-install diff --git a/sims/firesim b/sims/firesim index 593596c5..f9ca2f49 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 593596c5a854f69d28d0c3b9389175a03fa4c696 +Subproject commit f9ca2f49f95e2b51cf0e966ac13b1f285db341cf From f1df2ec69e1dab0666f8a2fb66849886a25717f1 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 3 Dec 2020 12:51:24 -0800 Subject: [PATCH 50/83] Bump FireSim/Hwacha | Cleanup linting --- build.sbt | 3 +++ generators/hwacha | 2 +- sims/firesim | 2 +- 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/build.sbt b/build.sbt index 1132dde1..b50bc200 100644 --- a/build.sbt +++ b/build.sbt @@ -1,5 +1,8 @@ import Tests._ +// Ignore linting for traceLevel +Global / excludeLintKeys += traceLevel + // This gives us a nicer handle to the root project instead of using the // implicit one lazy val chipyardRoot = Project("chipyardRoot", file(".")) diff --git a/generators/hwacha b/generators/hwacha index b67d8ed0..27e03b7e 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit b67d8ed06172c2ecd76807d3ef2bd5c79903f182 +Subproject commit 27e03b7e2694b4389c64c92a3518b1dba5304905 diff --git a/sims/firesim b/sims/firesim index f9ca2f49..515ac120 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit f9ca2f49f95e2b51cf0e966ac13b1f285db341cf +Subproject commit 515ac12059a347f34b13833888ace941a9629be5 From d0079a96599f2fa545e37e10ea459ba4e30fb672 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 3 Dec 2020 14:06:55 -0800 Subject: [PATCH 51/83] Cleanup helper sbt targets | Use project/target/active.json for SBT timestamp --- .gitignore | 1 - common.mk | 17 +++++++++++------ sims/firesim | 2 +- variables.mk | 3 ++- 4 files changed, 14 insertions(+), 9 deletions(-) diff --git a/.gitignore b/.gitignore index a80f88ab..257d2c58 100644 --- a/.gitignore +++ b/.gitignore @@ -20,4 +20,3 @@ tags env-riscv-tools.sh env-esp-tools.sh .bsp/ -*_TIMESTAMP diff --git a/common.mk b/common.mk index 159e7ea6..a474454a 100644 --- a/common.mk +++ b/common.mk @@ -66,14 +66,14 @@ SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools) SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt $(base_dir)/project/build.properties ######################################################################################### -# SBT Server Setup (needed to rebuild project correctly) +# SBT Server Setup (start server / rebuild proj. defs. if SBT_SOURCES change) ######################################################################################### $(SBT_THIN_CLIENT_TIMESTAMP): $(SBT_SOURCES) ifneq (,$(wildcard $(SBT_THIN_CLIENT_TIMESTAMP))) cd $(base_dir) && $(SBT) "reload" touch $@ else - touch $@ + cd $(base_dir) && $(SBT) "exit" endif ######################################################################################### @@ -223,18 +223,23 @@ $(dramsim_lib): $(MAKE) -C $(dramsim_dir) $(notdir $@) ################################################ -# Helper to run SBT or shutdown the SBT server +# Helper to run SBT or manage the SBT server ################################################ +SBT_COMMAND ?= shell .PHONY: launch-sbt launch-sbt: - cd $(base_dir) && $(SBT) + cd $(base_dir) && $(SBT_NON_THIN) "$(SBT_COMMAND)" -.PHONY: shutdown-sbt -shutdown-sbt: +.PHONY: shutdown-sbt-server +shutdown-sbt-server: cd $(base_dir) && $(SBT) "shutdown" rm -rf $(SBT_THIN_CLIENT_TIMESTAMP) +.PHONY: start-sbt-server +start-sbt-server: + cd $(base_dir) && $(SBT) "exit" + ######################################################################################### # print help text ######################################################################################### diff --git a/sims/firesim b/sims/firesim index 515ac120..6dc98f6c 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 515ac12059a347f34b13833888ace941a9629be5 +Subproject commit 6dc98f6cff25b348d3e2bf72fa17f2348c816b2f diff --git a/variables.mk b/variables.mk index c8f72b3f..88ba73ee 100644 --- a/variables.mk +++ b/variables.mk @@ -156,7 +156,7 @@ override SBT_OPTS += -Dsbt.sourcemode=true -Dsbt.workspace=$(base_dir)/tools SCALA_BUILDTOOL_DEPS = $(SBT_SOURCES) -SBT_THIN_CLIENT_TIMESTAMP = $(base_dir)/SBT_TIMESTAMP +SBT_THIN_CLIENT_TIMESTAMP = $(base_dir)/project/target/active.json ifdef ENABLE_SBT_THIN_CLIENT override SCALA_BUILDTOOL_DEPS += $(SBT_THIN_CLIENT_TIMESTAMP) @@ -165,6 +165,7 @@ SBT_CLIENT_FLAG = --client endif SBT ?= java $(JAVA_OPTS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar $(SBT_OPTS) $(SBT_CLIENT_FLAG) +SBT_NON_THIN ?= $(subst $(SBT_CLIENT_FLAG),,$(SBT)) define run_scala_main cd $(base_dir) && $(SBT) ";project $(1); runMain $(2) $(3)" From 70fa0a037dc2857980181592376aeea73223d9db Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 3 Dec 2020 14:57:05 -0800 Subject: [PATCH 52/83] Print full stack traces (default traceLevel = 0) | Bump FireSim --- build.sbt | 4 ---- sims/firesim | 2 +- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/build.sbt b/build.sbt index b50bc200..8856a20c 100644 --- a/build.sbt +++ b/build.sbt @@ -1,8 +1,5 @@ import Tests._ -// Ignore linting for traceLevel -Global / excludeLintKeys += traceLevel - // This gives us a nicer handle to the root project instead of using the // implicit one lazy val chipyardRoot = Project("chipyardRoot", file(".")) @@ -11,7 +8,6 @@ lazy val commonSettings = Seq( organization := "edu.berkeley.cs", version := "1.3", scalaVersion := "2.12.10", - traceLevel := 15, test in assembly := {}, assemblyMergeStrategy in assembly := { _ match { case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard diff --git a/sims/firesim b/sims/firesim index 6dc98f6c..2addd725 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 6dc98f6cff25b348d3e2bf72fa17f2348c816b2f +Subproject commit 2addd72598212424d8a4832b2d78b11c95d74337 From 714687c9622ff920e1b1e0eb542c63592572f2ef Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 4 Dec 2020 14:18:51 -0800 Subject: [PATCH 53/83] Add to help target | Cleanup build.sbt a bit more --- build.sbt | 21 ++++++++------------- common.mk | 7 +++++-- sims/firesim | 2 +- 3 files changed, 14 insertions(+), 16 deletions(-) diff --git a/build.sbt b/build.sbt index 8856a20c..b24fa748 100644 --- a/build.sbt +++ b/build.sbt @@ -13,7 +13,7 @@ lazy val commonSettings = Seq( case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard case _ => MergeStrategy.first}}, scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"), - addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), // TODO: Needed for just Rocket? + addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, allDependencies := { // drop dependencies (org, name) @@ -71,6 +71,7 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => // -- Rocket Chip -- +// This needs to stay in sync with the chisel3 and firrtl git submodules val chiselVersion = "3.4.0" lazy val chiselRef = ProjectRef(workspaceDirectory / "chisel3", "chisel") lazy val chiselLib = "edu.berkeley.cs" %% "chisel3" % chiselVersion @@ -83,16 +84,10 @@ lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion val firrtlVersion = "1.4.+" lazy val firrtlRef = ProjectRef(workspaceDirectory / "firrtl", "firrtl") lazy val firrtlLib = "edu.berkeley.cs" %% "firrtl" % firrtlVersion -//lazy val firrtlLibDeps = (firrtlRef / Keys.libraryDependencies) // TODO: Won't work because of antlr plugin -lazy val firrtlLibDeps = Seq( - "org.scalatest" %% "scalatest" % "3.2.0" % "test", - "org.scalatestplus" %% "scalacheck-1-14" % "3.1.3.0" % "test", - "com.github.scopt" %% "scopt" % "3.7.1", - "net.jcazevedo" %% "moultingyaml" % "0.4.2", - "org.json4s" %% "json4s-native" % "3.6.9", - "org.apache.commons" % "commons-text" % "1.8", - "org.antlr" % "antlr4-runtime" % "4.7.1" -) +val firrtlLibDeps = settingKey[Seq[sbt.librarymanagement.ModuleID]]("FIRRTL Library Dependencies sans antlr4") +Global / firrtlLibDeps := { + (firrtlRef / Keys.libraryDependencies).value.filterNot(_.name == "antlr4") +} // Rocket-chip dependencies (subsumes making RC a RootProject) lazy val hardfloat = (project in rocketChipDir / "hardfloat") @@ -153,14 +148,14 @@ lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies) lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) .sourceDependency(firrtlRef, firrtlLib) - .settings(libraryDependencies ++= firrtlLibDeps) .settings(commonSettings) + .settings(libraryDependencies ++= (Global / firrtlLibDeps).value) lazy val firrtlInterpreterLibDeps = (firrtl_interpreter / Keys.libraryDependencies) lazy val treadle = (project in file("tools/treadle")) .sourceDependency(firrtlRef, firrtlLib) - .settings(libraryDependencies ++= firrtlLibDeps) .settings(commonSettings) + .settings(libraryDependencies ++= (Global / firrtlLibDeps).value) lazy val treadleLibDeps = (treadle / Keys.libraryDependencies) lazy val chisel_testers = (project in file("tools/chisel-testers")) diff --git a/common.mk b/common.mk index a474454a..33c0137c 100644 --- a/common.mk +++ b/common.mk @@ -17,7 +17,8 @@ HELP_COMPILATION_VARIABLES += \ " EXTRA_SIM_CXXFLAGS = additional CXXFLAGS for building simulators" \ " EXTRA_SIM_LDFLAGS = additional LDFLAGS for building simulators" \ " EXTRA_SIM_SOURCES = additional simulation sources needed for simulator" \ -" EXTRA_SIM_REQS = additional make requirements to build the simulator" +" EXTRA_SIM_REQS = additional make requirements to build the simulator" \ +" ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client" EXTRA_GENERATOR_REQS ?= EXTRA_SIM_CXXFLAGS ?= @@ -41,7 +42,9 @@ HELP_COMMANDS += \ " run-binary-fast = run [./$(shell basename $(sim))] and don't log instructions" \ " run-binary-debug = run [./$(shell basename $(sim_debug))] and log instructions and waveform to files" \ " verilog = generate intermediate verilog files from chisel elaboration and firrtl passes" \ -" run-tests = run all assembly and benchmark tests" +" firrtl = generate intermediate firrtl files from chisel elaboration" \ +" run-tests = run all assembly and benchmark tests" \ +" launch-sbt = start sbt terminal" ######################################################################################### # include additional subproject make fragments diff --git a/sims/firesim b/sims/firesim index 2addd725..7ab7bc4a 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 2addd72598212424d8a4832b2d78b11c95d74337 +Subproject commit 7ab7bc4a2baaf04f5d8c03094c976e43dc1b2344 From 76ba68b02f6cc925772f7ac75925e21995b07caa Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 10 Dec 2020 06:34:30 +0000 Subject: [PATCH 54/83] Bump hwacha --- generators/hwacha | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/hwacha b/generators/hwacha index 27e03b7e..a354150c 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit 27e03b7e2694b4389c64c92a3518b1dba5304905 +Subproject commit a354150cb50fdc0c0ddd356e37850c8e36e02588 From 1787fda8c3ef936b59d50e040a93afe6355ab613 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 10 Dec 2020 06:34:39 +0000 Subject: [PATCH 55/83] Bump icenet --- generators/icenet | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/icenet b/generators/icenet index 277a9080..084ca507 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit 277a9080fe92afb25d942f3207252e0ddea1b864 +Subproject commit 084ca5070605ea7919358f917289cca240d0289a From ee436c9b3f73c239ce3b80726a3094225f3e3b56 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 10 Dec 2020 07:18:12 +0000 Subject: [PATCH 56/83] [firechip] Fix a uart multiclock bug --- generators/firechip/src/main/scala/BridgeBinders.scala | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 0572fabd..cdb026e1 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -4,12 +4,13 @@ package firesim.firesim import chisel3._ import chisel3.experimental.annotate +import chisel3.util.experimental.BoringUtils import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp} import freechips.rocketchip.amba.axi4.{AXI4Bundle} -import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem, HasTilesModuleImp, ExtMem} +import freechips.rocketchip.subsystem._ import freechips.rocketchip.tile.{RocketTile} import sifive.blocks.devices.uart._ @@ -86,7 +87,12 @@ class WithNICBridge extends OverrideHarnessBinder({ class WithUARTBridge extends OverrideHarnessBinder({ (system: HasPeripheryUARTModuleImp, th: FireSim, ports: Seq[UARTPortIO]) => - ports.map { p => UARTBridge(th.harnessClock, p)(system.p) }; Nil + val uartSyncClock = Wire(Clock()) + uartSyncClock := false.B.asClock + val pbusClockNode = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(PBUS).fixedClockNode + val pbusClock = pbusClockNode.in.head._1.clock + BoringUtils.bore(pbusClock, Seq(uartSyncClock)) + ports.map { p => UARTBridge(uartSyncClock, p)(system.p) }; Nil }) class WithBlockDeviceBridge extends OverrideHarnessBinder({ From f1f479912c85d1938d47b3f63d52647e1e365f6b Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 11 Dec 2020 03:22:59 +0000 Subject: [PATCH 57/83] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 7ab7bc4a..e43828a1 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 7ab7bc4a2baaf04f5d8c03094c976e43dc1b2344 +Subproject commit e43828a1fc9608123ae94abc40dfe813ccf23860 From db15419e1092e4475cd7b0b921b9b690b2644838 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 11 Dec 2020 03:55:49 +0000 Subject: [PATCH 58/83] Bump barstools --- tools/barstools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/barstools b/tools/barstools index 3a29f535..15fa68b3 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 3a29f535726a191d09164470eb1ce1a1ddd5bf9a +Subproject commit 15fa68b3a40addc5ac77a78ced37497dbce3f687 From d4d483c081869185f4e24063f17430b31ac98add Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 11 Dec 2020 10:19:02 -0800 Subject: [PATCH 59/83] Bump BOOM | Use ucb-bar fork chisel-testers --- .gitmodules | 2 +- generators/boom | 2 +- tools/chisel-testers | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/.gitmodules b/.gitmodules index 55b4be56..bb803d98 100644 --- a/.gitmodules +++ b/.gitmodules @@ -76,7 +76,7 @@ url = https://github.com/ucb-bar/dsptools.git [submodule "tools/chisel-testers"] path = tools/chisel-testers - url = https://github.com/abejgonzalez/chisel-testers.git + url = https://github.com/ucb-bar/chisel-testers.git [submodule "tools/treadle"] path = tools/treadle url = https://github.com/freechipsproject/treadle.git diff --git a/generators/boom b/generators/boom index a53372fc..eab35947 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit a53372fcff4c1095a513eb8bb6e8a2b9cdb971a0 +Subproject commit eab359478622cb089ac3164e8efc158a9b0b5028 diff --git a/tools/chisel-testers b/tools/chisel-testers index 5b9cc56d..461e8d3a 160000 --- a/tools/chisel-testers +++ b/tools/chisel-testers @@ -1 +1 @@ -Subproject commit 5b9cc56dd80c8d3bce67d54385d769037e2481d8 +Subproject commit 461e8d3a3e2f2e4c78d60c239428214cf8c7d773 From 5c7c1295a1ea5f1184121944c61be090260682b1 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 11 Dec 2020 11:37:25 -0800 Subject: [PATCH 60/83] Bump Gemmini+Dsptools | Fix SBT_OPTs in CI --- .circleci/defaults.sh | 2 +- generators/gemmini | 2 +- tools/dsptools | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 015aaee7..12c4531f 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -35,7 +35,7 @@ REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator REMOTE_FIRESIM_DIR=$REMOTE_CHIPYARD_DIR/sims/firesim/sim REMOTE_JAVA_OPTS="-Xmx10G -Xss8M" # Disable the supershell to greatly improve the readability of SBT output when captured by Circle CI -REMOTE_SBT_ARGS="-Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" +REMOTE_SBT_OPTS="-Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" REMOTE_VERILATOR_DIR=$REMOTE_PREFIX-$CIRCLE_SHA1-verilator-install # local variables (aka within the docker container) diff --git a/generators/gemmini b/generators/gemmini index eb719930..70517c52 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit eb7199307d3adf994c78b02a54859f3e37ac7012 +Subproject commit 70517c52f2d36c0fc1370b3b9836297646a70289 diff --git a/tools/dsptools b/tools/dsptools index 27304bde..aad6a3db 160000 --- a/tools/dsptools +++ b/tools/dsptools @@ -1 +1 @@ -Subproject commit 27304bdeae3e4fb969c7cac1e0bda358be7cdb12 +Subproject commit aad6a3db1520a05ae668681941a19bdcc40aec03 From 939e3a9f94d5bfef9671f49c37cd3acd5fc26128 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 11 Dec 2020 14:18:18 -0800 Subject: [PATCH 61/83] Bump paradise plugin | Remove extra rm for SBT-server timestamp | Small bump for barstools --- build.sbt | 2 +- common.mk | 1 - sims/firesim | 2 +- tools/barstools | 2 +- 4 files changed, 3 insertions(+), 4 deletions(-) diff --git a/build.sbt b/build.sbt index b24fa748..e984de86 100644 --- a/build.sbt +++ b/build.sbt @@ -13,7 +13,7 @@ lazy val commonSettings = Seq( case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard case _ => MergeStrategy.first}}, scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"), - addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), + addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.1" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, allDependencies := { // drop dependencies (org, name) diff --git a/common.mk b/common.mk index 33c0137c..24ab5687 100644 --- a/common.mk +++ b/common.mk @@ -237,7 +237,6 @@ launch-sbt: .PHONY: shutdown-sbt-server shutdown-sbt-server: cd $(base_dir) && $(SBT) "shutdown" - rm -rf $(SBT_THIN_CLIENT_TIMESTAMP) .PHONY: start-sbt-server start-sbt-server: diff --git a/sims/firesim b/sims/firesim index e43828a1..52a9d0fd 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit e43828a1fc9608123ae94abc40dfe813ccf23860 +Subproject commit 52a9d0fd2fd3f4ef32337ebd07e36e7ec16d906a diff --git a/tools/barstools b/tools/barstools index 15fa68b3..62f31165 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 15fa68b3a40addc5ac77a78ced37497dbce3f687 +Subproject commit 62f311654a4b31ccbc2839beaee64cd770ecd4a0 From fe4aa6cade03840b80c32911873c9586cce224f4 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 11 Dec 2020 14:20:09 -0800 Subject: [PATCH 62/83] Bump BOOM/Gemmini --- generators/boom | 2 +- generators/gemmini | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/boom b/generators/boom index eab35947..4bb6464f 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit eab359478622cb089ac3164e8efc158a9b0b5028 +Subproject commit 4bb6464ff392cf75e9caf8c06bc252b4f1ac8a28 diff --git a/generators/gemmini b/generators/gemmini index 70517c52..e6e14f71 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 70517c52f2d36c0fc1370b3b9836297646a70289 +Subproject commit e6e14f711760b976d8eb00c32d0fe2423aeda211 From f1e3117ae38f1f41d56a696d5c7bd89c4d93d146 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 11 Dec 2020 15:02:43 -0800 Subject: [PATCH 63/83] Bump barstools for test fixes | Small bump FireSim --- sims/firesim | 2 +- tools/barstools | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/sims/firesim b/sims/firesim index 52a9d0fd..f1dafa1b 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 52a9d0fd2fd3f4ef32337ebd07e36e7ec16d906a +Subproject commit f1dafa1bae05b8e4d752843ab489fd85e6df75bc diff --git a/tools/barstools b/tools/barstools index 62f31165..689ebdc0 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 62f311654a4b31ccbc2839beaee64cd770ecd4a0 +Subproject commit 689ebdc06e29028861f3282d9af6f2304541c9db From 8f1e20936fbc515875b24c11367343aed9748dba Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 12 Dec 2020 13:41:32 -0800 Subject: [PATCH 64/83] Update FireSim CI. Push threading into test context --- .../src/test/scala/ScalaTestSuite.scala | 23 +++++++++++-------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 64b9b4ba..51695690 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -42,10 +42,9 @@ abstract class FireSimTestSuite( } def runTest(backend: String, name: String, debug: Boolean, additionalArgs: Seq[String] = Nil) = { - behavior of s"${name} running on ${backend} in MIDAS-level simulation" compileMlSimulator(backend, debug) if (isCmdAvailable(backend)) { - it should s"pass" in { + it should s"pass in ML simualtion on ${backend}" in { assert(invokeMlSimulator(backend, name, debug, additionalArgs) == 0) } } @@ -59,13 +58,15 @@ abstract class FireSimTestSuite( case _: BenchmarkTestSuite | _: BlockdevTestSuite | _: NICTestSuite => ".riscv" case _ => "" } - val results = suite.names.toSeq sliding (N, N) map { t => - val subresults = t map (name => - Future(name -> invokeMlSimulator(backend, s"$name$postfix", debug))) - Await result (Future sequence subresults, Duration.Inf) - } - results.flatten foreach { case (name, exitcode) => - it should s"pass $name" in { assert(exitcode == 0) } + it should s"pass all tests in ${suite.makeTargetName}" in { + val results = suite.names.toSeq sliding (N, N) map { t => + val subresults = t map (name => + Future(name -> invokeMlSimulator(backend, s"$name$postfix", debug))) + Await result (Future sequence subresults, Duration.Inf) + } + results.flatten foreach { case (name, exitcode) => + assert(exitcode == 0, "Failed $name") + } } } else { ignore should s"pass $backend" @@ -96,7 +97,9 @@ abstract class FireSimTestSuite( } } - clean + mkdirs + behavior of s"Tuple: ${targetTuple}" + elaborateAndCompile() runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-humanreadable0""")) runSuite("verilator")(benchmarks) } From 1bd51447fe890cd0a6450bb655dc6d84c79fe851 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 13 Dec 2020 10:45:51 -0500 Subject: [PATCH 65/83] [ci skip] Fix Typo in firechip/src/test/scala/ScalaTestSuite.scala Co-authored-by: Abraham Gonzalez --- generators/firechip/src/test/scala/ScalaTestSuite.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 51695690..64b217b8 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -44,7 +44,7 @@ abstract class FireSimTestSuite( def runTest(backend: String, name: String, debug: Boolean, additionalArgs: Seq[String] = Nil) = { compileMlSimulator(backend, debug) if (isCmdAvailable(backend)) { - it should s"pass in ML simualtion on ${backend}" in { + it should s"pass in ML simulation on ${backend}" in { assert(invokeMlSimulator(backend, name, debug, additionalArgs) == 0) } } From a8d6daef93a6e17dab181de3f8875743e93ef58f Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 13 Dec 2020 09:32:44 -0800 Subject: [PATCH 66/83] Small build.sbt comments --- build.sbt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/build.sbt b/build.sbt index e984de86..e80b2a5e 100644 --- a/build.sbt +++ b/build.sbt @@ -16,7 +16,7 @@ lazy val commonSettings = Seq( addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.1" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, allDependencies := { - // drop dependencies (org, name) + // drop specific maven dependencies in subprojects in favor of Chipyard's version val dropDeps = Seq( ("edu.berkeley.cs", "firrtl"), ("edu.berkeley.cs", "chisel3"), @@ -86,6 +86,7 @@ lazy val firrtlRef = ProjectRef(workspaceDirectory / "firrtl", "firrtl") lazy val firrtlLib = "edu.berkeley.cs" %% "firrtl" % firrtlVersion val firrtlLibDeps = settingKey[Seq[sbt.librarymanagement.ModuleID]]("FIRRTL Library Dependencies sans antlr4") Global / firrtlLibDeps := { + // drop antlr4 compile dep. but keep antlr4-runtime dep. (compile needs the plugin to be setup) (firrtlRef / Keys.libraryDependencies).value.filterNot(_.name == "antlr4") } @@ -144,7 +145,7 @@ lazy val rocketchip = freshProject("rocketchip", rocketChipDir) ) lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies) -// -- "Problematic" Projects -- +// -- Chipyard-managed External Projects -- lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter")) .sourceDependency(firrtlRef, firrtlLib) @@ -168,7 +169,7 @@ lazy val chisel_testers = (project in file("tools/chisel-testers")) .settings(commonSettings) lazy val chiselTestersLibDeps = (chisel_testers / Keys.libraryDependencies) -// -- UCB-controlled Projects -- +// -- Normal Projects -- // Contains annotations & firrtl passes you may wish to use in rocket-chip without // introducing a circular dependency between RC and MIDAS From 02f22e0061ee475103d8b34a2ad6da26dad072ba Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 13 Dec 2020 09:37:48 -0800 Subject: [PATCH 67/83] Bump build.sbt.patch [ci skip] --- scripts/tutorial-patches/build.sbt.patch | 26 ++++++++++++++---------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch index cb289b6f..62cecb8d 100644 --- a/scripts/tutorial-patches/build.sbt.patch +++ b/scripts/tutorial-patches/build.sbt.patch @@ -1,26 +1,30 @@ diff --git a/build.sbt b/build.sbt -index 5d642c1..56f6fda 100644 +index e80b2a5..b1989d9 100644 --- a/build.sbt +++ b/build.sbt -@@ -130,7 +130,7 @@ lazy val iocell = (project in file("./tools/barstools/iocell/")) - - lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) - .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, +@@ -184,7 +184,7 @@ lazy val testchipipLib = "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHO + lazy val chipyard = (project in file("generators/chipyard")) + .sourceDependency(testchipip, testchipipLib) + .dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, - sha3, // On separate line to allow for cleaner tutorial-setup patches +// sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsptools`, gemmini, icenet, tracegen, cva6, nvdla, sodor) + .settings(libraryDependencies ++= rocketLibDeps.value) +@@ -227,11 +227,11 @@ lazy val sodor = (project in file("generators/riscv-sodor")) + .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) -@@ -158,9 +158,9 @@ lazy val cva6 = (project in file("generators/cva6")) - .dependsOn(rocketchip) - .settings(commonSettings) - + -lazy val sha3 = (project in file("generators/sha3")) - .dependsOn(rocketchip, chisel_testers, midasTargetUtils) +- .settings(libraryDependencies ++= rocketLibDeps.value) +- .settings(libraryDependencies ++= chiselTestersLibDeps.value) - .settings(commonSettings) +//lazy val sha3 = (project in file("generators/sha3")) +// .dependsOn(rocketchip, chisel_testers, midasTargetUtils) ++// .settings(libraryDependencies ++= rocketLibDeps.value) ++// .settings(libraryDependencies ++= chiselTestersLibDeps.value) +// .settings(commonSettings) - + lazy val gemmini = (project in file("generators/gemmini")) - .dependsOn(rocketchip, chisel_testers, testchipip) + .sourceDependency(testchipip, testchipipLib) From 8836f84c79772e2cf9b8fc9118fb862ed2cce9a7 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 15 Dec 2020 16:49:01 -0800 Subject: [PATCH 68/83] [vlsi] Add USE_SRAM_COMPILER Makefile flag to use memory compiler defined in tech library (#740) --- vlsi/Makefile | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index 0e1989dd..06f1a1b4 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -25,9 +25,15 @@ tech_dir ?= $(if $(filter $(tech_name),asap7 nangate45),\ SMEMS_COMP ?= $(tech_dir)/sram-compiler.json SMEMS_CACHE ?= $(tech_dir)/sram-cache.json SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json -MACROCOMPILER_MODE ?= $(if $(filter $(tech_name),asap7),\ - --mode synflops,\ - -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict) + +ifeq ($(tech_name),asap7) + MACROCOMPILER_MODE ?= --mode synflops +else ifdef USE_SRAM_COMPILER + MACROCOMPILER_MODE ?= -l $(SMEMS_COMP) --use-compiler -hir $(SMEMS_HAMMER) --mode strict +else + MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict +endif + ENV_YML ?= $(vlsi_dir)/env.yml INPUT_CONFS ?= $(if $(filter $(tech_name),nangate45),\ example-nangate45.yml,\ From f693972e1249aaac5d882d6e55e4eb5a81a99bd0 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 17:56:01 +0000 Subject: [PATCH 69/83] Start RC bump Bump to pre-merge chipsalliance/rocket-chip#2764 to get it going while picking up the chisel/firrtl bugfixes in 3/1.4.1+ --- build.sbt | 4 ++-- generators/rocket-chip | 2 +- tools/chisel3 | 2 +- tools/firrtl | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/build.sbt b/build.sbt index e80b2a5e..c3aa9515 100644 --- a/build.sbt +++ b/build.sbt @@ -72,7 +72,7 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => // -- Rocket Chip -- // This needs to stay in sync with the chisel3 and firrtl git submodules -val chiselVersion = "3.4.0" +val chiselVersion = "3.4.1" lazy val chiselRef = ProjectRef(workspaceDirectory / "chisel3", "chisel") lazy val chiselLib = "edu.berkeley.cs" %% "chisel3" % chiselVersion lazy val chiselLibDeps = (chiselRef / Keys.libraryDependencies) @@ -81,7 +81,7 @@ lazy val chiselLibDeps = (chiselRef / Keys.libraryDependencies) // keeping scalaVersion in sync with chisel3 to the minor version lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full -val firrtlVersion = "1.4.+" +val firrtlVersion = "1.4.1" lazy val firrtlRef = ProjectRef(workspaceDirectory / "firrtl", "firrtl") lazy val firrtlLib = "edu.berkeley.cs" %% "firrtl" % firrtlVersion val firrtlLibDeps = settingKey[Seq[sbt.librarymanagement.ModuleID]]("FIRRTL Library Dependencies sans antlr4") diff --git a/generators/rocket-chip b/generators/rocket-chip index 577994e3..a7b016e4 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 577994e38e3115cafa3a232b0fc60584aacb996e +Subproject commit a7b016e46e22e4fdc013357051e30511f80df082 diff --git a/tools/chisel3 b/tools/chisel3 index d379dca4..58d38f96 160000 --- a/tools/chisel3 +++ b/tools/chisel3 @@ -1 +1 @@ -Subproject commit d379dca4413d4cb08b02165a493faff01f3ddbb9 +Subproject commit 58d38f9620e7e91e4668266686484073c0ba7d2e diff --git a/tools/firrtl b/tools/firrtl index 05d047a9..7756f8f9 160000 --- a/tools/firrtl +++ b/tools/firrtl @@ -1 +1 @@ -Subproject commit 05d047a9befda3877f5d8a0a9e1076ffd520ddf9 +Subproject commit 7756f8f9634b68a1375d2c2ca13abc5742234201 From 95420baccfd1ce26354d6af70a09c7f3b50d448b Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 17:57:05 +0000 Subject: [PATCH 70/83] Bump boom for riscv-boom/riscv-boom#508 non-master pre-merge bump --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 4bb6464f..1899670a 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 4bb6464ff392cf75e9caf8c06bc252b4f1ac8a28 +Subproject commit 1899670ad92e402e7a5d21c13bdf025f546bb779 From c6dfa1d8c5de36bedfc6e3119ae2394fae2ded86 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 18:03:51 +0000 Subject: [PATCH 71/83] Bump testchipip for ucb-bar/testchipip#111 --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index 6fbb1b77..ca67a843 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 6fbb1b77b90da5e88bfde8e504595a332cca0e0b +Subproject commit ca67a843bd8f568e205981380c11d321d1bad677 From 5ff5b4e8b7601b461e5d222856ea1a2aaabdab0b Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 20:05:29 +0000 Subject: [PATCH 72/83] Bump sifive-cache for sifive/block-inclusivecache-sifive#18 --- generators/sifive-cache | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/sifive-cache b/generators/sifive-cache index d4db623f..b1160adc 160000 --- a/generators/sifive-cache +++ b/generators/sifive-cache @@ -1 +1 @@ -Subproject commit d4db623ff534f775ffc49f59c4a9ef24d5d759d0 +Subproject commit b1160adce09a73df6f5bd40f1e111ab3cefd7300 From f7a372153acf34416f9c6f9c6a10afb95675ab43 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 20:52:00 +0000 Subject: [PATCH 73/83] Bump hwacha for ucb-bar/hwacha#24 --- generators/hwacha | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/hwacha b/generators/hwacha index a354150c..62c01f5a 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit a354150cb50fdc0c0ddd356e37850c8e36e02588 +Subproject commit 62c01f5a8858aa1b827f0f9372a4392d7b596fca From 022dbf976ff6f389b40a9e058a2406945b88670e Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 20:52:30 +0000 Subject: [PATCH 74/83] Bump boom along in the same PR --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 1899670a..ad27160f 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 1899670ad92e402e7a5d21c13bdf025f546bb779 +Subproject commit ad27160f2a6f17bb91c70d570299a066b17255a7 From 2ce5f6a40723200761506be0c23042597d1a0045 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 20:54:31 +0000 Subject: [PATCH 75/83] Bump cva6 for ucb-bar/cva6-wrapper#11 --- generators/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/cva6 b/generators/cva6 index d40a8f5c..139741a5 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit d40a8f5c844f4169c8e74d3fa05f36286f9e4bb6 +Subproject commit 139741a584d7e3c0446db592b5d99529bd6cf9fa From a2ce14f8d3528cb2e86c990a35d82655c3f4cc9e Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 21:03:12 +0000 Subject: [PATCH 76/83] Bump sodor for ucb-bar/riscv-sodor#60 --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index cca8a7aa..8fc51640 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit cca8a7aa5743b9f9bf25779b87b464187c5c3fbc +Subproject commit 8fc516409fde12e447ad78f9d13962b5451c4485 From cb558b59529a328164e7f96bbcba21629df4fc11 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 23:20:31 +0000 Subject: [PATCH 77/83] bump boom along same PR --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index ad27160f..e250c70f 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit ad27160f2a6f17bb91c70d570299a066b17255a7 +Subproject commit e250c70fade22134fe9dc3347cfb5f608e1ee80e From a7e6de835ad5c641c516dc310269a0b921e24452 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 23:22:03 +0000 Subject: [PATCH 78/83] rm *XTypeKey. upstreamed to RC --- .../chipyard/src/main/scala/CustomBusTopologies.scala | 8 -------- 1 file changed, 8 deletions(-) diff --git a/generators/chipyard/src/main/scala/CustomBusTopologies.scala b/generators/chipyard/src/main/scala/CustomBusTopologies.scala index ee694d22..0a5c1c30 100644 --- a/generators/chipyard/src/main/scala/CustomBusTopologies.scala +++ b/generators/chipyard/src/main/scala/CustomBusTopologies.scala @@ -13,14 +13,6 @@ import freechips.rocketchip.subsystem._ // For subsystem/BusTopology.scala -/** - * Keys that serve as a means to define crossing types from a Parameters instance - */ -case object SbusToMbusXTypeKey extends Field[ClockCrossingType](NoCrossing) -case object SbusToCbusXTypeKey extends Field[ClockCrossingType](NoCrossing) -case object CbusToPbusXTypeKey extends Field[ClockCrossingType](SynchronousCrossing()) -case object FbusToSbusXTypeKey extends Field[ClockCrossingType](SynchronousCrossing()) - // Biancolin: This, modified from Henry's email /** Parameterization of a topology containing a banked coherence manager and a bus for attaching memory devices. */ case class CoherentMulticlockBusTopologyParams( From 72d084da8f8244e29420dfff0a95494d06489562 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 23:24:19 +0000 Subject: [PATCH 79/83] update parameter classes for RC additions --- generators/chipyard/src/main/scala/example/TutorialTile.scala | 4 ++++ generators/tracegen/src/main/scala/Tile.scala | 2 ++ 2 files changed, 6 insertions(+) diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala index 23b05f76..fad51c01 100644 --- a/generators/chipyard/src/main/scala/example/TutorialTile.scala +++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala @@ -15,6 +15,7 @@ import freechips.rocketchip.interrupts._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.amba.axi4._ +import freechips.rocketchip.prci.ClockSinkParameters // Example parameter class copied from CVA6, not included in documentation but for compile check only // If you are here for documentation, DO NOT copy MyCoreParams and MyTileParams directly - always figure @@ -39,6 +40,7 @@ case class MyCoreParams( val mulDiv: Option[MulDivParams] = Some(MulDivParams()) // copied from Rocket val fpu: Option[FPUParams] = Some(FPUParams()) // copied fma latencies from Rocket val nLocalInterrupts: Int = 0 + val useNMI: Boolean = false val nPMPs: Int = 0 // TODO: Check val pmpGranularity: Int = 4 // copied from Rocket val nBreakpoints: Int = 0 // TODO: Check @@ -51,6 +53,7 @@ case class MyCoreParams( val misaWritable: Boolean = false val haveCFlush: Boolean = false val nL2TLBEntries: Int = 512 // copied from Rocket + val nL2TLBWays: Int = 1 val mtvecInit: Option[BigInt] = Some(BigInt(0)) // copied from Rocket val mtvecWritable: Boolean = true // copied from Rocket val instBits: Int = if (useCompressed) 16 else 32 @@ -83,6 +86,7 @@ case class MyTileParams( val boundaryBuffers: Boolean = false val dcache: Option[DCacheParams] = Some(DCacheParams()) val icache: Option[ICacheParams] = Some(ICacheParams()) + val clockSinkParams: ClockSinkParameters = ClockSinkParameters() def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): MyTile = { new MyTile(this, crossing, lookup) } diff --git a/generators/tracegen/src/main/scala/Tile.scala b/generators/tracegen/src/main/scala/Tile.scala index 5ff9af56..712cffc1 100644 --- a/generators/tracegen/src/main/scala/Tile.scala +++ b/generators/tracegen/src/main/scala/Tile.scala @@ -13,6 +13,7 @@ import freechips.rocketchip.interrupts._ import freechips.rocketchip.subsystem._ import boom.lsu.{BoomNonBlockingDCache, LSU, LSUCoreIO} import boom.common.{BoomTileParams, MicroOp, BoomCoreParams, BoomModule} +import freechips.rocketchip.prci.ClockSinkParameters class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p) @@ -190,6 +191,7 @@ case class BoomTraceGenParams( val blockerCtrlAddr = None val name = None val traceParams = TraceGenParams(wordBits, addrBits, addrBag, maxRequests, memStart, numGens, dcache, hartId) + val clockSinkParams: ClockSinkParameters = ClockSinkParameters() } class BoomTraceGenTile private( From 29ab6301e0786def4608f7ad3d6456ae36b93c8f Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Mon, 21 Dec 2020 18:15:49 +0000 Subject: [PATCH 80/83] bump sifive-cache for merged sifive/block-inclusivecache-sifive#15 my previous bump duplicated an earlier PR --- generators/sifive-cache | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/sifive-cache b/generators/sifive-cache index b1160adc..e3a3000c 160000 --- a/generators/sifive-cache +++ b/generators/sifive-cache @@ -1 +1 @@ -Subproject commit b1160adce09a73df6f5bd40f1e111ab3cefd7300 +Subproject commit e3a3000cc1fd4cdf3a4e638e4d081b8aae94ebf0 From e22350092bdcb11c1f303cf7205eb6caec77efff Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Mon, 21 Dec 2020 18:27:47 +0000 Subject: [PATCH 81/83] bump boom along same PR --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index e250c70f..75399e3c 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit e250c70fade22134fe9dc3347cfb5f608e1ee80e +Subproject commit 75399e3cd94e4ad64f007f9d8ba0f39e6ff7ec16 From 36b9bf86ff9b0aec442be5d0f415e5e45924e76b Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 22 Dec 2020 22:45:58 -0800 Subject: [PATCH 82/83] Update MINGIT version to 1.8.5 (#745) 1.8.5 is necessary for `git -C` to work. --- scripts/init-submodules-no-riscv-tools-nolog.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index c861658d..803e9889 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -11,7 +11,7 @@ case ${MYGIT} in [1-9]*) ;; *) echo 'warning: unknown git version' ;; esac -MINGIT="1.7.8" +MINGIT="1.8.5" if [ "$MINGIT" != "$(echo -e "$MINGIT\n$MYGIT" | sort -V | head -n1)" ]; then echo "This script requires git version $MINGIT or greater. Exiting." false From 0f47d80edb350ec41d96586d57b886f50882af2b Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Wed, 23 Dec 2020 15:00:57 +0000 Subject: [PATCH 83/83] bump boom along same PR --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 75399e3c..e1a70afe 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 75399e3cd94e4ad64f007f9d8ba0f39e6ff7ec16 +Subproject commit e1a70afed7de77f6ba9f6e501de71f7f41afc47c