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Give HarnessRAM implicit clock/reset in SerialTiedOff

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This commit is contained in:
Jerry Zhao
2021-03-15 15:35:41 -07:00
parent a013f0d561
commit c5e7d8a9b2
1 changed files with 7 additions and 13 deletions
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20
generators/chipyard/src/main/scala/HarnessBinders.scala
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@@ -238,30 +238,24 @@ class WithTiedOffDebug extends OverrideHarnessBinder({
})
class WithSerialAdapterTiedOff(asyncQueue: Boolean = false) extends OverrideHarnessBinder({
class WithSerialAdapterTiedOff extends OverrideHarnessBinder({
(system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
implicit val p = chipyard.iobinders.GetSystemParameters(system)
ports.map({ port =>
val bits = if (asyncQueue) {
SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset)
} else {
port.bits
val bits = SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset)
withClockAndReset(th.harnessClock, th.harnessReset) {
val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset)
SerialAdapter.tieoff(ram.module.io.tsi_ser)
}
val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset)
SerialAdapter.tieoff(ram.module.io.tsi_ser)
})
}
})
class WithSimSerial(asyncQueue: Boolean = false) extends OverrideHarnessBinder({
class WithSimSerial extends OverrideHarnessBinder({
(system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
implicit val p = chipyard.iobinders.GetSystemParameters(system)
ports.map({ port =>
val bits = if (asyncQueue) {
SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset)
} else {
port.bits
}
val bits = SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset)
withClockAndReset(th.harnessClock, th.harnessReset) {
val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset)
val success = SerialAdapter.connectSimSerial(ram.module.io.tsi_ser, th.harnessClock, th.harnessReset.asBool)