From c5e7d8a9b2d6f4321a94cc041e51919bb4209973 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 15 Mar 2021 15:35:41 -0700 Subject: [PATCH] Give HarnessRAM implicit clock/reset in SerialTiedOff --- .../src/main/scala/HarnessBinders.scala | 20 +++++++------------ 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index fe03f951..9159873d 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -238,30 +238,24 @@ class WithTiedOffDebug extends OverrideHarnessBinder({ }) -class WithSerialAdapterTiedOff(asyncQueue: Boolean = false) extends OverrideHarnessBinder({ +class WithSerialAdapterTiedOff extends OverrideHarnessBinder({ (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => - val bits = if (asyncQueue) { - SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset) - } else { - port.bits + val bits = SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset) + withClockAndReset(th.harnessClock, th.harnessReset) { + val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset) + SerialAdapter.tieoff(ram.module.io.tsi_ser) } - val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset) - SerialAdapter.tieoff(ram.module.io.tsi_ser) }) } }) -class WithSimSerial(asyncQueue: Boolean = false) extends OverrideHarnessBinder({ +class WithSimSerial extends OverrideHarnessBinder({ (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => - val bits = if (asyncQueue) { - SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset) - } else { - port.bits - } + val bits = SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset) withClockAndReset(th.harnessClock, th.harnessReset) { val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset) val success = SerialAdapter.connectSimSerial(ram.module.io.tsi_ser, th.harnessClock, th.harnessReset.asBool)