Small cleanup to CY DigitalTop | Move E300 configs to unique folder
This commit is contained in:
@@ -23,7 +23,7 @@ MODEL := ArtyFPGATestHarness
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VLOG_MODEL := ArtyFPGATestHarness
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VLOG_MODEL := ArtyFPGATestHarness
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MODEL_PACKAGE := chipyard.fpga.arty
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MODEL_PACKAGE := chipyard.fpga.arty
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CONFIG := E300ArtyDevKitConfig
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CONFIG := E300ArtyDevKitConfig
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CONFIG_PACKAGE := chipyard.fpga.arty
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CONFIG_PACKAGE := chipyard.fpga.arty.e300
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GENERATOR_PACKAGE := chipyard
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GENERATOR_PACKAGE := chipyard
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TB := none # unused
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TB := none # unused
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TOP := ChipTop
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TOP := ChipTop
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@@ -1,5 +1,5 @@
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// See LICENSE for license details.
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// See LICENSE for license details.
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package chipyard.fpga.arty
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package chipyard.fpga.arty.e300
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import freechips.rocketchip.config._
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import freechips.rocketchip.config._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.subsystem._
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@@ -16,6 +16,8 @@ import sifive.blocks.devices.spi._
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import sifive.blocks.devices.uart._
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import sifive.blocks.devices.uart._
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import sifive.blocks.devices.i2c._
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import sifive.blocks.devices.i2c._
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import chipyard.{BuildSystem}
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class E300DevKitExtra extends Config((site, here, up) => {
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class E300DevKitExtra extends Config((site, here, up) => {
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case PeripheryGPIOKey => List(
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case PeripheryGPIOKey => List(
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GPIOParams(address = 0x10012000, width = 32, includeIOF = true))
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GPIOParams(address = 0x10012000, width = 32, includeIOF = true))
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@@ -46,7 +48,12 @@ class E300DevKitExtra extends Config((site, here, up) => {
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debugIdleCycles = 5)
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debugIdleCycles = 5)
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})
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})
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class WithE300System extends Config((site, here, up) => {
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case BuildSystem => (p: Parameters) => new E300DigitalTop()(p)
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})
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class E300ArtyDevKitConfig extends Config(
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class E300ArtyDevKitConfig extends Config(
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new WithE300System ++
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new WithE300Connections ++
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new WithE300Connections ++
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new E300DevKitExtra ++
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new E300DevKitExtra ++
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new chipyard.config.WithBootROM ++
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new chipyard.config.WithBootROM ++
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23
fpga/src/main/scala/arty/e300/DigitalTop.scala
Normal file
23
fpga/src/main/scala/arty/e300/DigitalTop.scala
Normal file
@@ -0,0 +1,23 @@
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package chipyard.fpga.arty.e300
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import chisel3._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.system._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.devices.tilelink._
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import chipyard.{DigitalTop, DigitalTopModule}
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// ------------------------------------
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// E300 DigitalTop
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// ------------------------------------
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class E300DigitalTop(implicit p: Parameters) extends DigitalTop
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with sifive.blocks.devices.mockaon.HasPeripheryMockAON
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{
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override lazy val module = new E300DigitalTopModule(this)
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}
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class E300DigitalTopModule[+L <: E300DigitalTop](l: L) extends DigitalTopModule(l)
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with sifive.blocks.devices.mockaon.HasPeripheryMockAONModuleImp
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@@ -1,4 +1,4 @@
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package chipyard.fpga.arty
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package chipyard.fpga.arty.e300
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import chisel3._
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import chisel3._
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import chisel3.experimental.{attach, IO}
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import chisel3.experimental.{attach, IO}
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@@ -13,10 +13,6 @@ import freechips.rocketchip.devices.tilelink._
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// DOC include start: DigitalTop
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// DOC include start: DigitalTop
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class DigitalTop(implicit p: Parameters) extends ChipyardSystem
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class DigitalTop(implicit p: Parameters) extends ChipyardSystem
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with sifive.blocks.devices.mockaon.HasPeripheryMockAON
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with sifive.blocks.devices.spi.HasPeripherySPI
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with sifive.blocks.devices.pwm.HasPeripheryPWM
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with sifive.blocks.devices.i2c.HasPeripheryI2C
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with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
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with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
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with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad
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with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad
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with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
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with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
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@@ -24,6 +20,9 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
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with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
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with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
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with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
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with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
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with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller
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with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller
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with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI
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with sifive.blocks.devices.pwm.HasPeripheryPWM // Enables optionally adding the sifive PWM
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with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C
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with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim
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with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim
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with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget
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with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget
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with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget
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with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget
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@@ -35,16 +34,15 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
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}
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}
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class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l)
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class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l)
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with sifive.blocks.devices.mockaon.HasPeripheryMockAONModuleImp
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with sifive.blocks.devices.spi.HasPeripherySPIModuleImp
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with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp
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with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp
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with testchipip.CanHaveTraceIOModuleImp
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with testchipip.CanHaveTraceIOModuleImp
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with testchipip.CanHavePeripheryBlockDeviceModuleImp
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with testchipip.CanHavePeripheryBlockDeviceModuleImp
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with testchipip.CanHavePeripherySerialModuleImp
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with testchipip.CanHavePeripherySerialModuleImp
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with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
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with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
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with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp
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with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp
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with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp
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with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp
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with sifive.blocks.devices.spi.HasPeripherySPIModuleImp
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with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp
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with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp
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with icenet.CanHavePeripheryIceNICModuleImp
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with icenet.CanHavePeripheryIceNICModuleImp
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with chipyard.example.CanHavePeripheryGCDModuleImp
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with chipyard.example.CanHavePeripheryGCDModuleImp
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with freechips.rocketchip.util.DontTouch
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with freechips.rocketchip.util.DontTouch
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