diff --git a/fpga/Makefile b/fpga/Makefile index 0110bb10..c1e4fb2d 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -23,7 +23,7 @@ MODEL := ArtyFPGATestHarness VLOG_MODEL := ArtyFPGATestHarness MODEL_PACKAGE := chipyard.fpga.arty CONFIG := E300ArtyDevKitConfig -CONFIG_PACKAGE := chipyard.fpga.arty +CONFIG_PACKAGE := chipyard.fpga.arty.e300 GENERATOR_PACKAGE := chipyard TB := none # unused TOP := ChipTop diff --git a/fpga/src/main/scala/arty/Config.scala b/fpga/src/main/scala/arty/e300/Configs.scala similarity index 92% rename from fpga/src/main/scala/arty/Config.scala rename to fpga/src/main/scala/arty/e300/Configs.scala index bcea7c78..dd9213fc 100644 --- a/fpga/src/main/scala/arty/Config.scala +++ b/fpga/src/main/scala/arty/e300/Configs.scala @@ -1,5 +1,5 @@ // See LICENSE for license details. -package chipyard.fpga.arty +package chipyard.fpga.arty.e300 import freechips.rocketchip.config._ import freechips.rocketchip.subsystem._ @@ -16,6 +16,8 @@ import sifive.blocks.devices.spi._ import sifive.blocks.devices.uart._ import sifive.blocks.devices.i2c._ +import chipyard.{BuildSystem} + class E300DevKitExtra extends Config((site, here, up) => { case PeripheryGPIOKey => List( GPIOParams(address = 0x10012000, width = 32, includeIOF = true)) @@ -46,7 +48,12 @@ class E300DevKitExtra extends Config((site, here, up) => { debugIdleCycles = 5) }) +class WithE300System extends Config((site, here, up) => { + case BuildSystem => (p: Parameters) => new E300DigitalTop()(p) +}) + class E300ArtyDevKitConfig extends Config( + new WithE300System ++ new WithE300Connections ++ new E300DevKitExtra ++ new chipyard.config.WithBootROM ++ diff --git a/fpga/src/main/scala/arty/e300/DigitalTop.scala b/fpga/src/main/scala/arty/e300/DigitalTop.scala new file mode 100644 index 00000000..1bda2680 --- /dev/null +++ b/fpga/src/main/scala/arty/e300/DigitalTop.scala @@ -0,0 +1,23 @@ +package chipyard.fpga.arty.e300 + +import chisel3._ + +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.system._ +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.devices.tilelink._ + +import chipyard.{DigitalTop, DigitalTopModule} + +// ------------------------------------ +// E300 DigitalTop +// ------------------------------------ + +class E300DigitalTop(implicit p: Parameters) extends DigitalTop + with sifive.blocks.devices.mockaon.HasPeripheryMockAON +{ + override lazy val module = new E300DigitalTopModule(this) +} + +class E300DigitalTopModule[+L <: E300DigitalTop](l: L) extends DigitalTopModule(l) + with sifive.blocks.devices.mockaon.HasPeripheryMockAONModuleImp diff --git a/fpga/src/main/scala/arty/IOBinders.scala b/fpga/src/main/scala/arty/e300/IOBinders.scala similarity index 99% rename from fpga/src/main/scala/arty/IOBinders.scala rename to fpga/src/main/scala/arty/e300/IOBinders.scala index e8833827..d9a2e1cc 100644 --- a/fpga/src/main/scala/arty/IOBinders.scala +++ b/fpga/src/main/scala/arty/e300/IOBinders.scala @@ -1,4 +1,4 @@ -package chipyard.fpga.arty +package chipyard.fpga.arty.e300 import chisel3._ import chisel3.experimental.{attach, IO} diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 160e6acf..9e40cfab 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -13,10 +13,6 @@ import freechips.rocketchip.devices.tilelink._ // DOC include start: DigitalTop class DigitalTop(implicit p: Parameters) extends ChipyardSystem - with sifive.blocks.devices.mockaon.HasPeripheryMockAON - with sifive.blocks.devices.spi.HasPeripherySPI - with sifive.blocks.devices.pwm.HasPeripheryPWM - with sifive.blocks.devices.i2c.HasPeripheryI2C with testchipip.CanHaveTraceIO // Enables optionally adding trace IO with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device @@ -24,6 +20,9 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller + with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI + with sifive.blocks.devices.pwm.HasPeripheryPWM // Enables optionally adding the sifive PWM + with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget @@ -35,16 +34,15 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem } class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l) - with sifive.blocks.devices.mockaon.HasPeripheryMockAONModuleImp - with sifive.blocks.devices.spi.HasPeripherySPIModuleImp - with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp - with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp with testchipip.CanHaveTraceIOModuleImp with testchipip.CanHavePeripheryBlockDeviceModuleImp with testchipip.CanHavePeripherySerialModuleImp with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp + with sifive.blocks.devices.spi.HasPeripherySPIModuleImp + with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp + with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp with icenet.CanHavePeripheryIceNICModuleImp with chipyard.example.CanHavePeripheryGCDModuleImp with freechips.rocketchip.util.DontTouch