wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Fix VCS build.

Browse Source 
VCS doesn't use the same arguments for C headers that verilator uses.
Generate the dot-f file differently for the different simulators.
This commit is contained in:
Paul Rigge
2019-03-06 23:06:24 -08:00
parent 467fdd06e9
commit bf23d7aa6c
2 changed files with 12 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
src/main/scala/example/Simulator.scala
View File

@@ -41,11 +41,16 @@ trait HasGenerateSimConfig {
} }
object GenerateSimFiles extends App with HasGenerateSimConfig { object GenerateSimFiles extends App with HasGenerateSimConfig {
def addOption(file: File): String = { def addOption(file: File, cfg: GenerateSimConfig): String = {
val fname = file.getCanonicalPath val fname = file.getCanonicalPath
// add -FI flag for header files // deal with header files
if (fname.takeRight(2) == ".h") { if (fname.takeRight(2) == ".h") {
s"-FI ${fname}" cfg.simulator match {
// verilator needs to explicitly include verilator.h, so use the -FI option
case VerilatorSimulator => s"-FI ${fname}"
// vcs pulls headers in with +incdir, doesn't have anything like verilator.h
case VCSSimulator => ""
}
} else { // do nothing otherwise } else { // do nothing otherwise
fname fname
} }
@@ -101,7 +106,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
writeBootrom() writeBootrom()
firrtl.FileUtils.makeDirectory(cfg.targetDir) firrtl.FileUtils.makeDirectory(cfg.targetDir)
val files = resources(cfg.simulator).map { writeResource(_, cfg.targetDir) } val files = resources(cfg.simulator).map { writeResource(_, cfg.targetDir) }
writeDotF(files.map(addOption), cfg) writeDotF(files.map(addOption(_, cfg)), cfg)
} }
parser.parse(args, GenerateSimConfig()) match { parser.parse(args, GenerateSimConfig()) match {

6
vsim/Makefile
View File

@@ -41,7 +41,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
$(RISCV)/lib/libfesvr.so \ $(RISCV)/lib/libfesvr.so \
-sverilog \ -sverilog \
+incdir+$(generated_dir) \ +incdir+$(generated_dir) \
+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \ +define+CLOCK_PERIOD=1.0 $(sim_vsrcs) \
+define+PRINTF_COND=$(TB).printf_cond \ +define+PRINTF_COND=$(TB).printf_cond \
+define+STOP_COND=!$(TB).reset \ +define+STOP_COND=!$(TB).reset \
+define+RANDOMIZE_MEM_INIT \ +define+RANDOMIZE_MEM_INIT \
@@ -52,11 +52,11 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
verilog: $(sim_vsrcs) verilog: $(sim_vsrcs)
$(simv): $(sim_vsrcs) $(sim_csrcs) $(simv): $(sim_vsrcs) $(sim_dotf)
rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
-debug_pp -debug_pp
$(simv_debug) : $(sim_vsrcs) $(sim_csrcs) $(simv_debug) : $(sim_vsrcs) $(sim_dotf)
rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
+define+DEBUG -debug_pp +define+DEBUG -debug_pp