diff --git a/src/main/scala/example/Simulator.scala b/src/main/scala/example/Simulator.scala
index c66fcc02..0f142fd7 100644
--- a/src/main/scala/example/Simulator.scala
+++ b/src/main/scala/example/Simulator.scala
@@ -41,11 +41,16 @@ trait HasGenerateSimConfig {
 }
 
 object GenerateSimFiles extends App with HasGenerateSimConfig {
-  def addOption(file: File): String = {
+  def addOption(file: File, cfg: GenerateSimConfig): String = {
     val fname = file.getCanonicalPath
-    // add -FI flag for header files
+    // deal with header files
     if (fname.takeRight(2) == ".h") {
-      s"-FI ${fname}"
+      cfg.simulator match {
+        // verilator needs to explicitly include verilator.h, so use the -FI option
+        case VerilatorSimulator => s"-FI ${fname}"
+        // vcs pulls headers in with +incdir, doesn't have anything like verilator.h
+        case VCSSimulator => ""
+      }
     } else { // do nothing otherwise
       fname
     }
@@ -101,7 +106,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
     writeBootrom()
     firrtl.FileUtils.makeDirectory(cfg.targetDir)
     val files = resources(cfg.simulator).map { writeResource(_, cfg.targetDir) }
-    writeDotF(files.map(addOption), cfg)
+    writeDotF(files.map(addOption(_, cfg)), cfg)
   }
 
   parser.parse(args, GenerateSimConfig()) match {
diff --git a/vsim/Makefile b/vsim/Makefile
index ef5f1070..2f6a8488 100644
--- a/vsim/Makefile
+++ b/vsim/Makefile
@@ -41,7 +41,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
 	$(RISCV)/lib/libfesvr.so \
 	-sverilog \
 	+incdir+$(generated_dir) \
-	+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \
+	+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) \
 	+define+PRINTF_COND=$(TB).printf_cond \
 	+define+STOP_COND=!$(TB).reset \
 	+define+RANDOMIZE_MEM_INIT \
@@ -52,11 +52,11 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
 
 verilog: $(sim_vsrcs)
 
-$(simv): $(sim_vsrcs) $(sim_csrcs)
+$(simv): $(sim_vsrcs) $(sim_dotf)
 	rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
 	-debug_pp
 
-$(simv_debug) : $(sim_vsrcs) $(sim_csrcs)
+$(simv_debug) : $(sim_vsrcs) $(sim_dotf)
 	rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
 	+define+DEBUG -debug_pp