wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

[Firechip] Add support for Tile <-> Uncore rational division

Browse Source
This commit is contained in:
David Biancolin
2019-11-22 16:29:55 -08:00
parent 12485b8e5c
commit bcddd6e0f6
5 changed files with 35 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
generators/firechip/src/test/scala/ScalaTestSuite.scala
View File

@@ -139,6 +139,9 @@ class RocketNICF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_Fir
class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "BaseF1Config_MCRams")
class RamModelBoomF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimBoomConfig", "BaseF1Config_MCRams")
// Multiclock tests
class RocketMulticlockF1Tests extends FireSimTestSuite("FireSimNoNIC", "HalfRateUncore_DDR3FRFCFSLLC4MB_FireSimRocketChipQuadCoreConfig", "BaseF1Config")
abstract class FireSimTraceGenTest(targetConfig: String, platformConfig: String)
extends firesim.TestSuiteCommon with IsFireSimGeneratorLike {
val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs