From bcddd6e0f66c26f0fed18bb7f80b89384c5bca1f Mon Sep 17 00:00:00 2001
From: David Biancolin <david.biancolin@gmail.com>
Date: Fri, 22 Nov 2019 16:29:55 -0800
Subject: [PATCH] [Firechip] Add support for Tile <-> Uncore rational division

---
 .../example/src/main/scala/ConfigMixins.scala  |  1 +
 .../src/main/scala/TargetConfigs.scala         | 18 ++++++++++++++++--
 .../firechip/src/main/scala/TargetMixins.scala | 13 +++++++++++++
 .../firechip/src/main/scala/Targets.scala      |  2 ++
 .../src/test/scala/ScalaTestSuite.scala        |  3 +++
 5 files changed, 35 insertions(+), 2 deletions(-)

diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala
index 7d7e74af..dc9eed36 100644
--- a/generators/example/src/main/scala/ConfigMixins.scala
+++ b/generators/example/src/main/scala/ConfigMixins.scala
@@ -182,3 +182,4 @@ class WithInitZeroTop extends Config((site, here, up) => {
     Module(LazyModule(new TopWithInitZero()(p)).module)
 })
 // DOC include end: WithInitZero
+
diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala
index 37df3799..f7b70322 100644
--- a/generators/firechip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -11,7 +11,8 @@ import freechips.rocketchip.rocket.DCacheParams
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.tilelink.BootROMParams
 import freechips.rocketchip.devices.debug.DebugModuleParams
-import boom.common.BoomTilesKey
+import freechips.rocketchip.diplomacy.{RationalCrossing}
+import boom.common.{BoomCrossingKey, BoomTilesKey}
 import testchipip.{BlockDeviceKey, BlockDeviceConfig}
 import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
 import scala.math.{min, max}
@@ -19,7 +20,7 @@ import tracegen.TraceGenKey
 import icenet._
 
 import firesim.bridges._
-import firesim.util.{WithNumNodes}
+import firesim.util.{WithNumNodes, FireSimClockKey, FireSimClockParameters}
 import firesim.configs._
 
 class WithBootROM extends Config((site, here, up) => {
@@ -320,3 +321,16 @@ class FireSimTraceGenL2Config extends Config(
     outerLatencyCycles = 50) ++
   new WithTraceGenBridge ++
   new FireSimRocketChipConfig)
+
+
+class WithRationalTiles(multiplier: Int, divisor: Int) extends Config((site, here, up) => {
+  case FireSimClockKey => FireSimClockParameters(Seq(multiplier -> divisor))
+  case RocketCrossingKey => up(RocketCrossingKey, site) map { r =>
+    r.copy(crossingType = RationalCrossing())
+  }
+  case BoomCrossingKey => up(BoomCrossingKey, site) map { r =>
+    r.copy(crossingType = RationalCrossing())
+  }
+})
+
+class HalfRateUncore extends WithRationalTiles(2,1)
diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala
index b96a6606..6320038a 100644
--- a/generators/firechip/src/main/scala/TargetMixins.scala
+++ b/generators/firechip/src/main/scala/TargetMixins.scala
@@ -13,6 +13,7 @@ import freechips.rocketchip.tile.RocketTile
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.rocket.TracedInstruction
 import firesim.bridges.{TraceOutputTop, DeclockedTracedInstruction}
+import firesim.util.{HasAdditionalClocks, FireSimClockKey}
 
 import midas.targetutils.MemModelAnnotation
 
@@ -73,3 +74,15 @@ trait CanHaveMultiCycleRegfileImp {
   }
 }
 
+trait HasFireSimClockingImp extends HasAdditionalClocks {
+  val outer: HasTiles
+  val (tileClock, tileReset) = p(FireSimClockKey).additionalClocks.headOption match {
+    case Some((numer, denom)) if numer != denom => (clocks(1), ResetCatchAndSync(clocks(1), reset.toBool))
+    case None => (clocks(0), reset)
+  }
+
+  outer.tiles.foreach({ case tile =>
+    tile.module.clock := tileClock
+    tile.module.reset := tileReset
+  })
+}
diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala
index 4c790195..3a73b0d9 100644
--- a/generators/firechip/src/main/scala/Targets.scala
+++ b/generators/firechip/src/main/scala/Targets.scala
@@ -60,6 +60,7 @@ class FireSimModuleImp[+L <: FireSimDUT](l: L) extends SubsystemModuleImp(l)
     with HasPeripheryIceNICModuleImpValidOnly
     with HasPeripheryBlockDeviceModuleImp
     with HasTraceIOImp
+    with HasFireSimClockingImp
     with CanHaveMultiCycleRegfileImp
 
 class FireSim(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimDUT)
@@ -84,6 +85,7 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends SubsystemModule
     with HasPeripheryUARTModuleImp
     with HasPeripheryBlockDeviceModuleImp
     with HasTraceIOImp
+    with HasFireSimClockingImp
     with CanHaveMultiCycleRegfileImp
 
 class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimNoNICDUT)
diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala
index f4f55cd9..74af7fcb 100644
--- a/generators/firechip/src/test/scala/ScalaTestSuite.scala
+++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala
@@ -139,6 +139,9 @@ class RocketNICF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_Fir
 class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "BaseF1Config_MCRams")
 class RamModelBoomF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimBoomConfig", "BaseF1Config_MCRams")
 
+// Multiclock tests
+class RocketMulticlockF1Tests extends FireSimTestSuite("FireSimNoNIC", "HalfRateUncore_DDR3FRFCFSLLC4MB_FireSimRocketChipQuadCoreConfig", "BaseF1Config")
+
 abstract class FireSimTraceGenTest(targetConfig: String, platformConfig: String)
     extends firesim.TestSuiteCommon with IsFireSimGeneratorLike {
   val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs