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ADD: add inline comment for UART

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-T.K.-
2023-12-18 13:57:36 -08:00
parent af87056768
commit b3c97868e1
2 changed files with 9 additions and 6 deletions
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12
generators/chipyard/src/main/scala/config/SpikeConfigs.scala
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@@ -18,8 +18,8 @@ class dmiSpikeConfig extends Config(
// Avoids polling on the UART registers // Avoids polling on the UART registers
class SpikeFastUARTConfig extends Config( class SpikeFastUARTConfig extends Config(
new chipyard.WithNSpikeCores(1) ++ new chipyard.WithNSpikeCores(1) ++
new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ // Spike sim requires a larger UART FIFO buffer,
new chipyard.config.WithNoUART() ++ new chipyard.config.WithNoUART() ++ // so we overwrite the default one
new chipyard.config.WithMemoryBusFrequency(2) ++ new chipyard.config.WithMemoryBusFrequency(2) ++
new chipyard.config.WithPeripheryBusFrequency(2) ++ new chipyard.config.WithPeripheryBusFrequency(2) ++
new chipyard.config.AbstractConfig) new chipyard.config.AbstractConfig)
@@ -28,8 +28,8 @@ class SpikeFastUARTConfig extends Config(
class SpikeUltraFastConfig extends Config( class SpikeUltraFastConfig extends Config(
new chipyard.WithSpikeTCM ++ new chipyard.WithSpikeTCM ++
new chipyard.WithNSpikeCores(1) ++ new chipyard.WithNSpikeCores(1) ++
new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ // Spike sim requires a larger UART FIFO buffer,
new chipyard.config.WithNoUART() ++ new chipyard.config.WithNoUART() ++ // so we overwrite the default one
new chipyard.config.WithMemoryBusFrequency(2) ++ new chipyard.config.WithMemoryBusFrequency(2) ++
new chipyard.config.WithPeripheryBusFrequency(2) ++ new chipyard.config.WithPeripheryBusFrequency(2) ++
new chipyard.config.WithBroadcastManager ++ new chipyard.config.WithBroadcastManager ++
@@ -49,8 +49,8 @@ class SpikeUltraFastDevicesConfig extends Config(
new chipyard.WithSpikeTCM ++ new chipyard.WithSpikeTCM ++
new chipyard.WithNSpikeCores(1) ++ new chipyard.WithNSpikeCores(1) ++
new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ // Spike sim requires a larger UART FIFO buffer,
new chipyard.config.WithNoUART() ++ new chipyard.config.WithNoUART() ++ // so we overwrite the default one
new chipyard.config.WithMemoryBusFrequency(2) ++ new chipyard.config.WithMemoryBusFrequency(2) ++
new chipyard.config.WithPeripheryBusFrequency(2) ++ new chipyard.config.WithPeripheryBusFrequency(2) ++
new chipyard.config.WithBroadcastManager ++ new chipyard.config.WithBroadcastManager ++

3
generators/firechip/src/main/scala/TargetConfigs.scala
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@@ -135,6 +135,9 @@ class WithFireSimHighPerfClocking extends Config(
// Tweaks that are generally applied to all firesim configs setting a single clock domain at 1000 MHz // Tweaks that are generally applied to all firesim configs setting a single clock domain at 1000 MHz
class WithFireSimConfigTweaks extends Config( class WithFireSimConfigTweaks extends Config(
new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ // FireSim requires a larger UART FIFO buffer,
new chipyard.config.WithNoUART() ++ // so we overwrite the default one
// 1 GHz matches the FASED default (DRAM modeli realistically configured for that frequency) // 1 GHz matches the FASED default (DRAM modeli realistically configured for that frequency)
// Using some other frequency will require runnings the FASED runtime configuration generator // Using some other frequency will require runnings the FASED runtime configuration generator
// to generate faithful DDR3 timing values. // to generate faithful DDR3 timing values.