From b3c97868e106536eda5d28480b83c23a5feea089 Mon Sep 17 00:00:00 2001
From: "-T.K.-" <t_k_233@outlook.com>
Date: Mon, 18 Dec 2023 13:57:36 -0800
Subject: [PATCH] ADD: add inline comment for UART

---
 .../src/main/scala/config/SpikeConfigs.scala         | 12 ++++++------
 .../firechip/src/main/scala/TargetConfigs.scala      |  3 +++
 2 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala
index d221b41c..ba7a1fb2 100644
--- a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala
@@ -18,8 +18,8 @@ class dmiSpikeConfig extends Config(
 // Avoids polling on the UART registers
 class SpikeFastUARTConfig extends Config(
   new chipyard.WithNSpikeCores(1) ++
-  new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++
-  new chipyard.config.WithNoUART() ++
+  new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ // Spike sim requires a larger UART FIFO buffer, 
+  new chipyard.config.WithNoUART() ++                           // so we overwrite the default one
   new chipyard.config.WithMemoryBusFrequency(2) ++
   new chipyard.config.WithPeripheryBusFrequency(2) ++
   new chipyard.config.AbstractConfig)
@@ -28,8 +28,8 @@ class SpikeFastUARTConfig extends Config(
 class SpikeUltraFastConfig extends Config(
   new chipyard.WithSpikeTCM ++
   new chipyard.WithNSpikeCores(1) ++
-  new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++
-  new chipyard.config.WithNoUART() ++
+  new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ // Spike sim requires a larger UART FIFO buffer, 
+  new chipyard.config.WithNoUART() ++                           // so we overwrite the default one
   new chipyard.config.WithMemoryBusFrequency(2) ++
   new chipyard.config.WithPeripheryBusFrequency(2) ++
   new chipyard.config.WithBroadcastManager ++
@@ -49,8 +49,8 @@ class SpikeUltraFastDevicesConfig extends Config(
 
   new chipyard.WithSpikeTCM ++
   new chipyard.WithNSpikeCores(1) ++
-  new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++
-  new chipyard.config.WithNoUART() ++
+  new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ // Spike sim requires a larger UART FIFO buffer, 
+  new chipyard.config.WithNoUART() ++                           // so we overwrite the default one
   new chipyard.config.WithMemoryBusFrequency(2) ++
   new chipyard.config.WithPeripheryBusFrequency(2) ++
   new chipyard.config.WithBroadcastManager ++
diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala
index 944fe9cf..67313b08 100644
--- a/generators/firechip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -135,6 +135,9 @@ class WithFireSimHighPerfClocking extends Config(
 
 // Tweaks that are generally applied to all firesim configs setting a single clock domain at 1000 MHz
 class WithFireSimConfigTweaks extends Config(
+  new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ // FireSim requires a larger UART FIFO buffer, 
+  new chipyard.config.WithNoUART() ++                           // so we overwrite the default one
+
   // 1 GHz matches the FASED default (DRAM modeli realistically configured for that frequency)
   // Using some other frequency will require runnings the FASED runtime configuration generator
   // to generate faithful DDR3 timing values.