Merge branch 'graphics' of https://github.com/hansungk/chipyard into graphics

common.mk

@@ -16,6 +16,7 @@ HELP_COMPILATION_VARIABLES += \
 "   EXTRA_SIM_LDFLAGS         = additional LDFLAGS for building simulators" \
 "   EXTRA_SIM_SOURCES         = additional simulation sources needed for simulator" \
 "   EXTRA_SIM_REQS            = additional make requirements to build the simulator" \
+"   EXTRA_SIM_OUT_NAME        = additional suffix appended to the simulation .out log filename" \
 "   ENABLE_CUSTOM_FIRRTL_PASS = if set, enable custom firrtl passes (SFC lowers to LowFIRRTL & MFC converts to Verilog)" \
 "   ENABLE_YOSYS_FLOW         = if set, add compilation flags to enable the vlsi flow for yosys(tutorial flow)" \
 "   EXTRA_CHISEL_OPTIONS      = additional options to pass to the Chisel compiler" \

sims/vcs/vcs.mk

@@ -36,6 +36,7 @@ VCS_CC_OPTS = \
 	$(filter -l%,$(VCS_LDFLAGS))
 
 VCS_NONCC_OPTS = \
+	-j36 \
 	-notice \
 	-line \
 	+lint=all,noVCDE,noONGS,noUI,noPCTIO-L,noPCTI-L \

sims/verilator/Makefile

@@ -195,13 +195,13 @@ model_mk_debug = $(model_dir_debug)/V$(TB).mk
 $(model_mk): $(sim_common_files) $(EXTRA_SIM_REQS)
 	rm -rf $(model_dir)
 	mkdir -p $(model_dir)
-	$(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim) -Mdir $(model_dir)
+	$(VERILATOR) -j 36 $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim) -Mdir $(model_dir)
 	touch $@
 
 $(model_mk_debug): $(sim_common_files) $(EXTRA_SIM_REQS)
 	rm -rf $(model_dir_debug)
 	mkdir -p $(model_dir_debug)
-	$(VERILATOR) $(VERILATOR_OPTS) +define+DEBUG $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug)
+	$(VERILATOR) -j 36 $(VERILATOR_OPTS) +define+DEBUG $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug)
 	touch $@
 
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