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[temp] start integrating tsi host widget

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This commit is contained in:
Abraham Gonzalez
2020-11-06 10:57:55 -08:00
parent c721d897f3
commit b0eed5075f
5 changed files with 101 additions and 2 deletions
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14
fpga/src/main/scala/vcu118/bringup/IOBinders.scala
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@@ -3,9 +3,14 @@ package chipyard.fpga.vcu118.bringup
import chisel3._
import chisel3.experimental.{IO, DataMirror}
import freechips.rocketchip.util.{HeterogeneousBag}
import freechips.rocketchip.tilelink.{TLBundle}
import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp}
import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp}
import testchipip.{HasPeripheryTSIHostWidget}
import chipyard.iobinders.{OverrideIOBinder}
class WithGPIOIOPassthrough extends OverrideIOBinder({
@@ -27,3 +32,12 @@ class WithI2CIOPassthrough extends OverrideIOBinder({
(io_i2c_pins_temp, Nil)
}
})
class WithTSITLIOPassthrough extends OverrideIOBinder({
(system: HasPeripheryTSIHostWidget) => {
require(system.tsiMem.size == 1)
val io_tsi_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.tsiMem.head)).suggestName("tsi_tl_slave")
io_tsi_tl_mem_pins_temp <> system.tsiMem.head
(Seq(io_tsi_tl_mem_pins_temp), Nil)
}
})