From b0eed5075f804990deb8346e33db6ab87aebed55 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Fri, 6 Nov 2020 10:57:55 -0800 Subject: [PATCH] [temp] start integrating tsi host widget --- .../main/scala/vcu118/bringup/Configs.scala | 29 ++++++++++ .../scala/vcu118/bringup/CustomOverlays.scala | 56 ++++++++++++++++++- .../scala/vcu118/bringup/DigitalTop.scala | 2 + .../main/scala/vcu118/bringup/IOBinders.scala | 14 +++++ generators/testchipip | 2 +- 5 files changed, 101 insertions(+), 2 deletions(-) diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index 133d2ae2..4c6cd5ad 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -4,6 +4,8 @@ import math.min import freechips.rocketchip.config.{Config, Parameters} import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress} +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.diplomacy._ import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams} import sifive.blocks.devices.i2c.{PeripheryI2CKey, I2CParams} @@ -13,6 +15,8 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import sifive.fpgashells.shell.{DesignKey} import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} +import testchipip.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams} + import chipyard.{BuildSystem} import chipyard.fpga.vcu118.{WithVCU118Tweaks, WithFPGAFrequency} @@ -34,6 +38,30 @@ class WithBringupPeripherals extends Config((site, here, up) => { List.empty[GPIOParams] } } + case PeripheryTSIHostKey => List( + TSIHostParams( + serialIfWidth = 4, + mmioBaseAddress = BigInt(0x64006000), + mmioSourceId = 1 << 13, // manager source + serdesParams = TSIHostSerdesParams( + clientPortParams = TLMasterPortParameters.v1( + clients = Seq(TLMasterParameters.v1( + name = "tl-tsi-host-serdes", + sourceId = IdRange(0, (1 << 13))))), + managerPortParams = TLSlavePortParameters.v1( + managers = Seq(TLSlaveParameters.v1( + address = Seq(AddressSet(0, BigInt("FFFFFFFF", 16))), + regionType = RegionType.UNCACHED, + executable = true, + supportsGet = TransferSizes(1, 64), + supportsPutFull = TransferSizes(1, 64), + supportsPutPartial = TransferSizes(1, 64), + supportsAcquireT = TransferSizes(1, 64), + supportsAcquireB = TransferSizes(1, 64), + supportsArithmetic = TransferSizes(1, 64), + supportsLogical = TransferSizes(1, 64))), + endSinkId = 1 << 6, // manager sink + beatBytes = 8)))) }) class WithBringupVCU118System extends Config((site, here, up) => { @@ -45,6 +73,7 @@ class WithBringupAdditions extends Config( new WithBringupSPI ++ new WithBringupI2C ++ new WithBringupGPIO ++ + new WithTSITLIOPassthrough ++ new WithI2CIOPassthrough ++ new WithGPIOIOPassthrough ++ new WithBringupPeripherals ++ diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala index c0a96d3c..30a25afe 100644 --- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala +++ b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala @@ -144,4 +144,58 @@ class BringupGPIOVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInp def place(designInput: GPIODesignInput) = new BringupGPIOVCU118PlacedOverlay(shell, valName.name, designInput, shellInput, gpioNames) } - +//case class TSIShellInput() +//case class TSIDesignInput( +// +// )( +// implicit val p: Parameters)extends DDRDesignInput +// +//abstract class TSIOverlay(val params: TSIOverlayParams) +// extends IOOverlay[TLTSIWithDDRIO, TLTSIHostWidget] +//{ +// implicit val p = params.p +// +// // instantiate the tsi host widget and setup necessary connections +// val (tlTsiHost, tlTsiMemNode) = TLTSIHostWidget.attach(TSIHostWidgetAttachParams(params.tsiHostParams, params.controlBus)) +// val tlTsiHostIONodeSink = tlTsiHost.ioNode.makeSink +// +// // instantiate the DDR +// val size = p(TSIMigDDRSize) +// val migParams = XilinxVCU118MIGParams(address = AddressSet.misaligned(params.tsiHostParams.targetBaseAddress, size)) +// val mig = LazyModule(new XilinxVCU118MIG(migParams)) +// val tsiIONode = BundleBridgeSource(() => new TSIHostWidgetIO(params.tsiHostParams.serialIfWidth)) +// val topTSIIONode = shell { tsiIONode.makeSink() } +// val ddrIONode = BundleBridgeSource(() => mig.module.io.cloneType) +// val topDDRIONode = shell { ddrIONode.makeSink() } +// val ddrUI = shell { ClockSourceNode(freqMHz = 200) } +// val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) } +// areset := params.ddrParams.wrangler := ddrUI +// val asyncSink = LazyModule(new TLAsyncCrossingSink) +// val migClockReset = BundleBridgeSource(() => new Bundle { +// val clock = Output(Clock()) +// val reset = Output(Bool()) +// }) +// val migClockResetTop = shell { migClockReset.makeSink() } +// +// // connect them +// (mig.node := TLFragmenter(32,64,holdFirstDeny=true) := TLCacheCork() := TLSinkSetter(1 << 1) := TLSourceShrinker(1 << 4) := tlTsiMemNode) +// +// def designOutput = tlTsiHost +// def ioFactory = new TLTSIWithDDRIO(params.tsiHostParams.serialIfWidth, size) // top level io of the shell +// +// InModuleBody { +// val (t, _) = tsiIONode.out(0) +// val tsi = tlTsiHostIONodeSink.bundle +// tsi.serial_clock := t.serial_clock +// tsi.serial.in.bits := t.serial.in.bits +// tsi.serial.in.valid := t.serial.in.valid +// tsi.serial.out.ready := t.serial.out.ready +// t.serial.out.bits := tsi.serial.out.bits +// t.serial.out.valid := tsi.serial.out.valid +// t.serial.in.ready := tsi.serial.in.ready +// ddrIONode.bundle <> mig.module.io +// asyncSink.module.clock := migClockReset.bundle.clock +// asyncSink.module.reset := migClockReset.bundle.reset +// } +//} +// diff --git a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala index ddcfe163..a9105e26 100644 --- a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala +++ b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala @@ -17,9 +17,11 @@ import chipyard.fpga.vcu118.{VCU118DigitalTop, VCU118DigitalTopModule} class BringupVCU118DigitalTop(implicit p: Parameters) extends VCU118DigitalTop with sifive.blocks.devices.i2c.HasPeripheryI2C + with testchipip.HasPeripheryTSIHostWidget { override lazy val module = new BringupVCU118DigitalTopModule(this) } class BringupVCU118DigitalTopModule[+L <: BringupVCU118DigitalTop](l: L) extends VCU118DigitalTopModule(l) with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp + with testchipip.HasPeripheryTSIHostWidgetModuleImp diff --git a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala index 168933f7..32badd2a 100644 --- a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala @@ -3,9 +3,14 @@ package chipyard.fpga.vcu118.bringup import chisel3._ import chisel3.experimental.{IO, DataMirror} +import freechips.rocketchip.util.{HeterogeneousBag} +import freechips.rocketchip.tilelink.{TLBundle} + import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp} import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp} +import testchipip.{HasPeripheryTSIHostWidget} + import chipyard.iobinders.{OverrideIOBinder} class WithGPIOIOPassthrough extends OverrideIOBinder({ @@ -27,3 +32,12 @@ class WithI2CIOPassthrough extends OverrideIOBinder({ (io_i2c_pins_temp, Nil) } }) + +class WithTSITLIOPassthrough extends OverrideIOBinder({ + (system: HasPeripheryTSIHostWidget) => { + require(system.tsiMem.size == 1) + val io_tsi_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.tsiMem.head)).suggestName("tsi_tl_slave") + io_tsi_tl_mem_pins_temp <> system.tsiMem.head + (Seq(io_tsi_tl_mem_pins_temp), Nil) + } +}) diff --git a/generators/testchipip b/generators/testchipip index 03af7aa5..5dae68ef 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 03af7aa53988dd96dffd613d1d50a5c6661e0a82 +Subproject commit 5dae68efbc925d09c6a8758064e88f6a3661baa2