removing seemingly useless override
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@@ -90,12 +90,7 @@ class GCDMMIOChiselModule(val w: Int) extends Module {
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// DOC include start: GCD router
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class GCDTL(params: GCDParams, beatBytes: Int)(implicit p: Parameters) extends ClockSinkDomain(ClockSinkParameters())(p) {
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val device = new SimpleDevice("gcd", Seq("ucbbar,gcd")) {
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override def describe(resources: ResourceBindings): Description = {
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val Description(name, mapping) = super.describe(resources)
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Description(name, mapping)
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}
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}
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val device = new SimpleDevice("gcd", Seq("ucbbar,gcd"))
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val node = TLRegisterNode(Seq(AddressSet(params.address, 4096-1)), device, "reg/control", beatBytes=beatBytes)
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override lazy val module = new GCDImpl
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