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Colin's fixes

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Donggyu Kim
2017-07-21 00:27:48 -07:00
committed by edwardcwang
parent 2fd928fbe0
commit aeb303a61b
3 changed files with 15 additions and 16 deletions
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10
tapeout/src/main/scala/transforms/macros/MacroCompiler.scala
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@@ -36,7 +36,7 @@ class MacroCompilerPass(mems: Option[Seq[Macro]],
for (i <- 0 until mem.width.toInt) { for (i <- 0 until mem.width.toInt) {
if (i <= last + 1) { if (i <= last + 1) {
/* Palmer: Every memory is going to have to fit at least a single bit. */ /* Palmer: Every memory is going to have to fit at least a single bit. */
// coninue // continue
} else if ((i - last) % lib.width.toInt == 0) { } else if ((i - last) % lib.width.toInt == 0) {
/* Palmer: It's possible that we rolled over a memory's width here, /* Palmer: It's possible that we rolled over a memory's width here,
if so generate one. */ if so generate one. */
@@ -53,7 +53,7 @@ class MacroCompilerPass(mems: Option[Seq[Macro]],
case (_, None) => // continue case (_, None) => // continue
case (_, Some(p)) if p == lib.width => // continue case (_, Some(p)) if p == lib.width => // continue
case _ => case _ =>
System.err println "Bit-mask (or unmasked) target memories are suppored only" System.err println "Bit-mask (or unmasked) target memories are supported only"
return None return None
} }
} }
@@ -198,7 +198,7 @@ class MacroCompilerPass(mems: Option[Seq[Macro]],
* there isn't a write enable port. */ * there isn't a write enable port. */
WRef(mem) WRef(mem)
case None => case None =>
/* Palemr: If there is no input port on the source memory port /* Palmer: If there is no input port on the source memory port
* then we don't ever want to turn on this write * then we don't ever want to turn on this write
* enable. Otherwise, we just _always_ turn on the * enable. Otherwise, we just _always_ turn on the
* write enable port on the inner memory. */ * write enable port on the inner memory. */
@@ -316,9 +316,7 @@ class MacroCompilerPass(mems: Option[Seq[Macro]],
} }
case _ => c.modules case _ => c.modules
} }
val circuit = c.copy(modules = modules) c.copy(modules = modules)
// print(circuit.serialize)
circuit
} }
} }

4
tapeout/src/main/scala/transforms/macros/SynFlops.scala
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@@ -54,9 +54,9 @@ class SynFlopsPass(synflops: Boolean, libs: Seq[Macro]) extends firrtl.passes.Pa
WSubIndex(data, k, tpe, UNKNOWNGENDER))).reverse) WSubIndex(data, k, tpe, UNKNOWNGENDER))).reverse)
case _: UIntType => data case _: UIntType => data
} }
val addrReg = WRef(s"R_${i}_addr_reg", r.AddrType, RegKind) val addrReg = WRef(s"R_${i}_addr_reg", r.addrType, RegKind)
Seq( Seq(
DefRegister(NoInfo, addrReg.name, r.AddrType, clock, zero, addrReg), DefRegister(NoInfo, addrReg.name, r.addrType, clock, zero, addrReg),
Connect(NoInfo, memPortField(mem, s"R_$i", "clk"), clock), Connect(NoInfo, memPortField(mem, s"R_$i", "clk"), clock),
Connect(NoInfo, memPortField(mem, s"R_$i", "addr"), addrReg), Connect(NoInfo, memPortField(mem, s"R_$i", "addr"), addrReg),
Connect(NoInfo, memPortField(mem, s"R_$i", "en"), enable), Connect(NoInfo, memPortField(mem, s"R_$i", "en"), enable),

17
tapeout/src/main/scala/transforms/macros/Utils.scala
View File

@@ -17,11 +17,12 @@ case object NegativeEdge extends PortPolarity
case object PositiveEdge extends PortPolarity case object PositiveEdge extends PortPolarity
object PortPolarity { object PortPolarity {
implicit def toPortPolarity(s: Any): PortPolarity = implicit def toPortPolarity(s: Any): PortPolarity =
(s: @unchecked) match { s match {
case "active low" => ActiveLow case "active low" => ActiveLow
case "active high" => ActiveHigh case "active high" => ActiveHigh
case "negative edge" => NegativeEdge case "negative edge" => NegativeEdge
case "positive edge" => PositiveEdge case "positive edge" => PositiveEdge
case _ => throw new firrtl.passes.PassException(s"Wrong port polarity: ${s.toString}")
} }
implicit def toPortPolarity(s: Option[Any]): Option[PortPolarity] = implicit def toPortPolarity(s: Option[Any]): Option[PortPolarity] =
s map toPortPolarity s map toPortPolarity
@@ -48,18 +49,18 @@ case class MacroPort(
width: BigInt, width: BigInt,
depth: BigInt) { depth: BigInt) {
val effectiveMaskGran = maskGran.getOrElse(width) val effectiveMaskGran = maskGran.getOrElse(width)
val AddrType = UIntType(IntWidth(ceilLog2(depth) max 1)) val addrType = UIntType(IntWidth(ceilLog2(depth) max 1))
val DataType = UIntType(IntWidth(width)) val dataType = UIntType(IntWidth(width))
val MaskType = UIntType(IntWidth(width / effectiveMaskGran)) val maskType = UIntType(IntWidth(width / effectiveMaskGran))
val tpe = BundleType(Seq( val tpe = BundleType(Seq(
Field(clockName, Flip, ClockType), Field(clockName, Flip, ClockType),
Field(addressName, Flip, AddrType)) ++ Field(addressName, Flip, addrType)) ++
(inputName map (Field(_, Flip, DataType))) ++ (inputName map (Field(_, Flip, dataType))) ++
(outputName map (Field(_, Default, DataType))) ++ (outputName map (Field(_, Default, dataType))) ++
(chipEnableName map (Field(_, Flip, BoolType))) ++ (chipEnableName map (Field(_, Flip, BoolType))) ++
(readEnableName map (Field(_, Flip, BoolType))) ++ (readEnableName map (Field(_, Flip, BoolType))) ++
(writeEnableName map (Field(_, Flip, BoolType))) ++ (writeEnableName map (Field(_, Flip, BoolType))) ++
(maskName map (Field(_, Flip, MaskType))) (maskName map (Field(_, Flip, maskType)))
) )
val ports = tpe.fields map (f => Port( val ports = tpe.fields map (f => Port(
NoInfo, f.name, f.flip match { case Default => Output case Flip => Input }, f.tpe)) NoInfo, f.name, f.flip match { case Default => Output case Flip => Input }, f.tpe))