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Colin's fixes

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Donggyu Kim
2017-07-21 00:27:48 -07:00
committed by edwardcwang
parent 2fd928fbe0
commit aeb303a61b
3 changed files with 15 additions and 16 deletions
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4
tapeout/src/main/scala/transforms/macros/SynFlops.scala
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@@ -54,9 +54,9 @@ class SynFlopsPass(synflops: Boolean, libs: Seq[Macro]) extends firrtl.passes.Pa
WSubIndex(data, k, tpe, UNKNOWNGENDER))).reverse)
case _: UIntType => data
}
val addrReg = WRef(s"R_${i}_addr_reg", r.AddrType, RegKind)
val addrReg = WRef(s"R_${i}_addr_reg", r.addrType, RegKind)
Seq(
DefRegister(NoInfo, addrReg.name, r.AddrType, clock, zero, addrReg),
DefRegister(NoInfo, addrReg.name, r.addrType, clock, zero, addrReg),
Connect(NoInfo, memPortField(mem, s"R_$i", "clk"), clock),
Connect(NoInfo, memPortField(mem, s"R_$i", "addr"), addrReg),
Connect(NoInfo, memPortField(mem, s"R_$i", "en"), enable),