Some Revisions

generators/chipyard/src/main/scala/ConfigFragments.scala

@@ -147,21 +147,14 @@ class WithControlCore extends Config((site, here, up) => {
   case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1)
 })
 
-trait TraceIOMatch {
-  this: CoreRegisterEntryBase =>
-  val matchTile: (View, View, View) => PartialFunction[Field[Seq[TileParams]],Any] = ((site, here, up) => {
-    // TODO: XXX What's the "tile" here?
-    case tilesKey => up(tilesKey) map (tile => tile.copy(trace = true))
-  })
-}
-
 class WithTraceIO extends Config((site, here, up) => {
-  val coreMatch = (coreList: List[CoreRegisterEntryBase]) => coreList match {
+  val coreMatch: List[CoreRegisterEntryBase] => PartialFunction[Any,Any] =
-    case coreEntry :: tail => coreEntry.matchTile(site, here, up) orElse coreMatch(tail)
+    coreList => coreList match {
-    case Nil => {
+      case coreEntry :: tail => coreEntry.enableTileTrace(site, here, up) orElse coreMatch(tail)
-      case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
+      case Nil => {
-      case TracePortKey => Some(TracePortParams())
+        case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
+        case TracePortKey => Some(TracePortParams())
+      }
     }
-  }
   coreMatch(CoreRegistrar.cores)
 })

generators/chipyard/src/main/scala/CoreRegistrar.scala

@@ -2,36 +2,43 @@ package chipyard
 
 import chisel3._
 
-import freechips.rocketchip.config.{Parameters, Config, Field}
+import freechips.rocketchip.config.{Parameters, Config, Field, View}
 import freechips.rocketchip.subsystem.{SystemBusKey, RocketTilesKey, RocketCrossingParams}
-import freechips.rocketchip.devices.tilelink.{BootROMParams}
+import freechips.rocketchip.diplomacy.LazyModule
-import freechips.rocketchip.diplomacy.{SynchronousCrossing, AsynchronousCrossing, RationalCrossing}
+import freechips.rocketchip.diplomaticobjectmodel.logicaltree.LogicalTreeNode
 import freechips.rocketchip.rocket._
 import freechips.rocketchip.tile._
 
 import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams}
 
-import chipyard.config.TraceIOMatch
-
 // Third-party core entries
 sealed trait CoreRegisterEntryBase {
-  type Tile
+  type TileParams <: CoreParams
-  type TitleParams
+  def tilesKey: Field[Seq[TileParams]]
-  def tilesKey: Field[Seq[TitleParams]]
   def crossingKey: Field[Seq[RocketCrossingParams]]
+  def enableTileTrace(site: View, here: View, up: View): PartialFunction[Any, Any]
+  def instantiateTile(param: TileParams, crossing: RocketCrossingParams,
+    logicalTreeNode: LogicalTreeNode, p: Parameters): Option[BaseTile]
 }
 
-class CoreRegisterEntry[TileT <: BaseTile, TileParamsT <: CoreParams](tk: Field[Seq[TileParamsT]], ck: Field[Seq[RocketCrossingParams]]) 
+class CoreRegisterEntry[TileParamsT <: CoreParams, TileT <: BaseTile](tk: Field[Seq[TileParamsT]], ck: Field[Seq[RocketCrossingParams]],
-  extends CoreRegisterEntryBase with TraceIOMatch {
+  tileInstantiator: (TileParamsT, RocketCrossingParams, LookupByHartIdImpl, LogicalTreeNode, Parameters) => TileT) extends CoreRegisterEntryBase {
-  type Tile = TileT
   type TileParams = TileParamsT
   def tilesKey = tk
   def crossingKey = ck
+  def enableTileTrace(site: View, here: View, up: View): PartialFunction[Any, Any] = {
+    case in if in == tilesKey => up(this.tilesKey) map (tile => tile.copy(trace = true))
+  }
+  def instantiateTile(param: TileParams, crossing: RocketCrossingParams, 
+    logicalTreeNode: LogicalTreeNode, p: Parameters): Option[BaseTile] = param match {
+    case a: TileParams => Some(tileInstantiator(a, crossing, PriorityMuxHartIdFromSeq(p(tilesKey)), logicalTreeNode, p))
+    case _ => None
+  }
 }
 
 object CoreRegistrar {
   val cores: List[CoreRegisterEntryBase] = List(
     // ADD YOUR CORE DEFINITION HERE
-    new CoreRegisterEntry[ArianeTile, ArianeTileParams](ArianeTilesKey, ArianeCrossingKey)
+    new CoreRegisterEntry[ArianeTileParams, ArianeTile](ArianeTilesKey, ArianeCrossingKey, ((a, b, c, d, p) => {new ArianeTile(a, b, c, d)}))
   )
 }

generators/chipyard/src/main/scala/Subsystem.scala

@@ -40,12 +40,13 @@ trait HasChipyardTiles extends HasTiles
   // crossing can either be per tile or global (aka only 1 crossing specified)
   private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size)
   private val boomCrossings = perTileOrGlobalSetting(p(BoomCrossingKey), boomTileParams.size)
-  private val coreCrossings = (CoreRegistrar.cores zip coreTileParams) map ((coreType, tileParams) =>
+  private val coreCrossings = (CoreRegistrar.cores zip coreTileParams) map (_ match {
-    perTileOrGlobalSetting(p(coreType.crossingKey), tileParams.size))
+    case (coreType, tileParams) => perTileOrGlobalSetting(p(coreType.crossingKey), tileParams.size)
+  })
 
   // TODO: XXX The "tiles" below scan for hartId but it is not in CoreParams. Should that be added in later 
   // revision, or I have to use reflection to get that parameter?
-  val allTilesInfo = (rocketTileParams ++ boomTileParams ++ coreTileParams) zip (rocketCrossings ++ boomCrossings ++ coreCrossings)
+  val allTilesInfo = (rocketTileParams ++ boomTileParams ++ coreTileParams.flatten) zip (rocketCrossings ++ boomCrossings ++ coreCrossings.flatten)
 
   // Make a tile and wire its nodes into the system,
   // according to the specified type of clock crossing.
@@ -57,22 +58,17 @@ trait HasChipyardTiles extends HasTiles
   val tiles = allTilesInfo.sortWith(_._1.hartId < _._1.hartId).map {
     case (param, crossing) => {
 
-      val tileMatch = coreAndtileParamsList => {
+      val tile = param match {
-        case (coreType, tileParams) :: tail => (param => {
+        case r: RocketTileParams => {
-          case a: coreType.TileParams => {
+          LazyModule(new RocketTile(r, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode))
-            LazyModule(new coreType.Tile(a, crossing, PriorityMuxHartIdFromSeq(tileParams), logicalTreeNode))
-          }
-        }) orElse tileMatch(tail)
-        case Nil => param => {
-          case r: RocketTileParams => {
-            LazyModule(new RocketTile(r, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode))
-          }
-          case b: BoomTileParams => {
-            LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode))
-          }
         }
+        case b: BoomTileParams => {
+          LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode))
+        }
+        case _ => LazyModule(
+          (CoreRegistrar.cores collect (core => core.instantiateTile(param, crossing, paramList, logicalTreeNode, p)).unlift()) (0)
+        )
       }
-      val tile = tileMatch(CoreRegistrar.cores zip coreTileParams)
       connectMasterPortsToSBus(tile, crossing)
       connectSlavePortsToCBus(tile, crossing)
       connectInterrupts(tile, debugOpt, clintOpt, plicOpt)