wu-arch/chipyard
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This commit is contained in:
Zitao Fang
2020-05-21 12:35:26 -07:00
parent ff583e9e1f
commit adb85c98ca
3 changed files with 39 additions and 43 deletions
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21
generators/chipyard/src/main/scala/ConfigFragments.scala
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@@ -147,21 +147,14 @@ class WithControlCore extends Config((site, here, up) => {
case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1)
})
trait TraceIOMatch {
this: CoreRegisterEntryBase =>
val matchTile: (View, View, View) => PartialFunction[Field[Seq[TileParams]],Any] = ((site, here, up) => {
// TODO: XXX What's the "tile" here?
case tilesKey => up(tilesKey) map (tile => tile.copy(trace = true))
})
}
class WithTraceIO extends Config((site, here, up) => {
val coreMatch = (coreList: List[CoreRegisterEntryBase]) => coreList match {
case coreEntry :: tail => coreEntry.matchTile(site, here, up) orElse coreMatch(tail)
case Nil => {
case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
case TracePortKey => Some(TracePortParams())
val coreMatch: List[CoreRegisterEntryBase] => PartialFunction[Any,Any] =
coreList => coreList match {
case coreEntry :: tail => coreEntry.enableTileTrace(site, here, up) orElse coreMatch(tail)
case Nil => {
case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
case TracePortKey => Some(TracePortParams())
}
}
}
coreMatch(CoreRegistrar.cores)
})