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update verilator so that plusarg_reader works

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Howard Mao
2017-07-20 20:19:02 +00:00
parent fae57b6daa
commit ada96f3724
3 changed files with 2 additions and 3 deletions
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1
src/main/scala/example/Configs.scala
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@@ -50,7 +50,6 @@ class WithSimNetwork extends Config((site, here, up) => {
}) })
class BaseExampleConfig extends Config( class BaseExampleConfig extends Config(
new WithoutTLMonitors ++
new WithSerialAdapter ++ new WithSerialAdapter ++
new freechips.rocketchip.chip.DefaultConfig) new freechips.rocketchip.chip.DefaultConfig)

2
verisim/Makefile
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@@ -69,4 +69,4 @@ $(sim_debug): $(model_mk_debug) $(sim_csrcs)
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(MODEL).mk $(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(MODEL).mk
clean: clean:
rm -rf generated-src rm -rf generated-src ./simulator-*

2
verisim/Makefrag-verilator
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@@ -1,5 +1,5 @@
# Build and install our own Verilator, to work around versionining issues. # Build and install our own Verilator, to work around versionining issues.
VERILATOR_VERSION=3.884 VERILATOR_VERSION=3.904
VERILATOR_SRCDIR=verilator/src/verilator-$(VERILATOR_VERSION) VERILATOR_SRCDIR=verilator/src/verilator-$(VERILATOR_VERSION)
INSTALLED_VERILATOR=$(abspath verilator/install/bin/verilator) INSTALLED_VERILATOR=$(abspath verilator/install/bin/verilator)
$(INSTALLED_VERILATOR): $(VERILATOR_SRCDIR)/bin/verilator $(INSTALLED_VERILATOR): $(VERILATOR_SRCDIR)/bin/verilator