update verilator so that plusarg_reader works

2017-07-20 20:19:02 +00:00
parent fae57b6daa
commit ada96f3724
3 changed files with 2 additions and 3 deletions
--- a/verisim/Makefile
+++ b/verisim/Makefile
@@ -69,4 +69,4 @@ $(sim_debug): $(model_mk_debug) $(sim_csrcs)
 	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(MODEL).mk

 clean:
-	rm -rf generated-src
+	rm -rf generated-src ./simulator-*