[firechip] Remove unneeded FASED target Mixin

generators/firechip/src/main/scala/TargetMixins.scala

@@ -38,60 +38,6 @@ trait HasDefaultBusConfiguration {
   }
 }
 
-
-/** Copied from RC and modified to change the IO type of the Imp to include the Diplomatic edges
-  *  associated with each port. This drives FASED functional model sizing
-  */
-trait CanHaveFASEDOptimizedMasterAXI4MemPort { this: BaseSubsystem =>
-  val module: CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
-
-  val memAXI4Node = p(ExtMem).map { case MemoryPortParams(memPortParams, nMemoryChannels) =>
-    val portName = "axi4"
-    val device = new MemoryDevice
-
-    val memAXI4Node = AXI4SlaveNode(Seq.tabulate(nMemoryChannels) { channel =>
-      val base = AddressSet.misaligned(memPortParams.base, memPortParams.size)
-      val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes))
-
-      AXI4SlavePortParameters(
-        slaves = Seq(AXI4SlaveParameters(
-          address       = base.flatMap(_.intersect(filter)),
-          resources     = device.reg,
-          regionType    = RegionType.UNCACHED, // cacheable
-          executable    = true,
-          supportsWrite = TransferSizes(1, mbus.blockBytes),
-          supportsRead  = TransferSizes(1, mbus.blockBytes),
-          interleavedId = Some(0))), // slave does not interleave read responses
-        beatBytes = memPortParams.beatBytes)
-    })
-
-    memAXI4Node := mbus.toDRAMController(Some(portName)) {
-      AXI4UserYanker() := AXI4IdIndexer(memPortParams.idBits) := TLToAXI4()
-    }
-
-    memAXI4Node
-  }
-}
-
-/** Actually generates the corresponding IO in the concrete Module */
-trait CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp extends LazyModuleImp {
-  val outer: CanHaveFASEDOptimizedMasterAXI4MemPort
-
-  val mem_axi4 = outer.memAXI4Node.map(x => IO(HeterogeneousBag(AXI4BundleWithEdge.fromNode(x.in))))
-  (mem_axi4 zip outer.memAXI4Node) foreach { case (io, node) =>
-    (io zip node.in).foreach { case (io, (bundle, _)) => io <> bundle }
-  }
-
-  def connectSimAXIMem() {
-    (mem_axi4 zip outer.memAXI4Node).foreach { case (io, node) =>
-      (io zip node.in).foreach { case (io, (_, edge)) =>
-        val mem = LazyModule(new SimAXIMem(edge, size = p(ExtMem).get.master.size))
-        Module(mem.module).io.axi4.head <> io
-      }
-    }
-  }
-}
-
 /* Wires out tile trace ports to the top; and wraps them in a Bundle that the
  * TracerV endpoint can match on.
  */