101 lines
3.4 KiB
Scala
101 lines
3.4 KiB
Scala
package firesim.firesim
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import chisel3._
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import chisel3.experimental.annotate
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.amba.axi4._
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import freechips.rocketchip.util._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.rocket.TracedInstruction
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import firesim.endpoints.{TraceOutputTop, DeclockedTracedInstruction}
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import midas.models.AXI4BundleWithEdge
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import midas.targetutils.{ExcludeInstanceAsserts, MemModelAnnotation}
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/** Ties together Subsystem buses in the same fashion done in the example top of Rocket Chip */
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trait HasDefaultBusConfiguration {
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this: BaseSubsystem =>
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// The sbus masters the cbus; here we convert TL-UH -> TL-UL
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sbus.crossToBus(cbus, NoCrossing)
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// The cbus masters the pbus; which might be clocked slower
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cbus.crossToBus(pbus, SynchronousCrossing())
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// The fbus masters the sbus; both are TL-UH or TL-C
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FlipRendering { implicit p =>
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sbus.crossFromBus(fbus, SynchronousCrossing())
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}
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// The sbus masters the mbus; here we convert TL-C -> TL-UH
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private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key)
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private val (in, out, halt) = coherenceManager(this)
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if (nBanks != 0) {
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sbus.coupleTo("coherence_manager") { in :*= _ }
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mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out }
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}
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}
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/* Wires out tile trace ports to the top; and wraps them in a Bundle that the
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* TracerV endpoint can match on.
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*/
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object PrintTracePort extends Field[Boolean](false)
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trait HasTraceIO {
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this: HasTiles =>
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val module: HasTraceIOImp
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// Bind all the trace nodes to a BB; we'll use this to generate the IO in the imp
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val traceNexus = BundleBridgeNexus[Vec[TracedInstruction]]
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val tileTraceNodes = tiles.map(tile => tile.traceNode)
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tileTraceNodes foreach { traceNexus := _ }
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}
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trait HasTraceIOImp extends LazyModuleImp {
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val outer: HasTraceIO
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val traceIO = IO(Output(new TraceOutputTop(
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DeclockedTracedInstruction.fromNode(outer.traceNexus.in))))
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(traceIO.traces zip outer.traceNexus.in).foreach({ case (port, (tileTrace, _)) =>
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port := DeclockedTracedInstruction.fromVec(tileTrace)
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})
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// Enabled to test TracerV trace capture
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if (p(PrintTracePort)) {
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val traceprint = Wire(UInt(512.W))
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traceprint := traceIO.asUInt
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printf("TRACEPORT: %x\n", traceprint)
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}
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}
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// Prevent MIDAS from synthesizing assertions in the dummy TLB included in BOOM
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trait ExcludeInvalidBoomAssertions extends LazyModuleImp {
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ExcludeInstanceAsserts(("NonBlockingDCache", "dtlb"))
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}
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trait CanHaveBoomMultiCycleRegfileImp {
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val outer: boom.system.BoomRocketSubsystem
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val cores = outer.boomTiles.map(tile => tile.module.core)
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cores.foreach({ core =>
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core.iregfile match {
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case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
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case _ => Nil
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}
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if (core.fp_pipeline != null) core.fp_pipeline.fregfile match {
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case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
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case _ => Nil
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}
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})
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}
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trait CanHaveRocketMultiCycleRegfileImp {
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val outer: RocketSubsystem
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outer.rocketTiles.foreach({ tile =>
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annotate(MemModelAnnotation(tile.module.core.rocketImpl.rf.rf))
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tile.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile)))
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})
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}
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