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[firechip] Remove unneeded FASED target Mixin

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This commit is contained in:
David Biancolin
2019-09-13 00:40:50 -07:00
parent 9285155476
commit ac8385a0c5
3 changed files with 10 additions and 63 deletions
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3
generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala
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@@ -6,6 +6,7 @@ import chisel3.experimental.RawModule
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp
import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp}
import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp}
@@ -55,7 +56,7 @@ class DefaultFireSimEnvironment[T <: LazyModule](dutGen: () => T)(implicit val p
{ case t: HasPeripheryIceNICModuleImpValidOnly => Seq(NICEndpoint(t.net)) },
{ case t: HasPeripheryUARTModuleImp => t.uart.map(u => UARTEndpoint(u)) },
{ case t: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevEndpoint(t.bdev, reset)) },
{ case t: CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp =>
{ case t: CanHaveMasterAXI4MemPortModuleImp =>
(t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) =>
(io zip node.in).map({ case (axi4Bundle, (_, edge)) =>
val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth,

54
generators/firechip/src/main/scala/TargetMixins.scala
View File

@@ -38,60 +38,6 @@ trait HasDefaultBusConfiguration {
}
}
/** Copied from RC and modified to change the IO type of the Imp to include the Diplomatic edges
* associated with each port. This drives FASED functional model sizing
*/
trait CanHaveFASEDOptimizedMasterAXI4MemPort { this: BaseSubsystem =>
val module: CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
val memAXI4Node = p(ExtMem).map { case MemoryPortParams(memPortParams, nMemoryChannels) =>
val portName = "axi4"
val device = new MemoryDevice
val memAXI4Node = AXI4SlaveNode(Seq.tabulate(nMemoryChannels) { channel =>
val base = AddressSet.misaligned(memPortParams.base, memPortParams.size)
val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes))
AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
address = base.flatMap(_.intersect(filter)),
resources = device.reg,
regionType = RegionType.UNCACHED, // cacheable
executable = true,
supportsWrite = TransferSizes(1, mbus.blockBytes),
supportsRead = TransferSizes(1, mbus.blockBytes),
interleavedId = Some(0))), // slave does not interleave read responses
beatBytes = memPortParams.beatBytes)
})
memAXI4Node := mbus.toDRAMController(Some(portName)) {
AXI4UserYanker() := AXI4IdIndexer(memPortParams.idBits) := TLToAXI4()
}
memAXI4Node
}
}
/** Actually generates the corresponding IO in the concrete Module */
trait CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp extends LazyModuleImp {
val outer: CanHaveFASEDOptimizedMasterAXI4MemPort
val mem_axi4 = outer.memAXI4Node.map(x => IO(HeterogeneousBag(AXI4BundleWithEdge.fromNode(x.in))))
(mem_axi4 zip outer.memAXI4Node) foreach { case (io, node) =>
(io zip node.in).foreach { case (io, (bundle, _)) => io <> bundle }
}
def connectSimAXIMem() {
(mem_axi4 zip outer.memAXI4Node).foreach { case (io, node) =>
(io zip node.in).foreach { case (io, (_, edge)) =>
val mem = LazyModule(new SimAXIMem(edge, size = p(ExtMem).get.master.size))
Module(mem.module).io.axi4.head <> io
}
}
}
}
/* Wires out tile trace ports to the top; and wraps them in a Bundle that the
* TracerV endpoint can match on.
*/

16
generators/firechip/src/main/scala/Targets.scala
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@@ -38,7 +38,7 @@ import FireSimValName._
class FireSimDUT(implicit p: Parameters) extends RocketSubsystem
with HasDefaultBusConfiguration
with CanHaveFASEDOptimizedMasterAXI4MemPort
with CanHaveMasterAXI4MemPort
with HasPeripheryBootROM
with HasPeripherySerial
with HasPeripheryUART
@@ -51,7 +51,7 @@ class FireSimDUT(implicit p: Parameters) extends RocketSubsystem
class FireSimModuleImp[+L <: FireSimDUT](l: L) extends RocketSubsystemModuleImp(l)
with HasRTCModuleImp
with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
with CanHaveMasterAXI4MemPortModuleImp
with HasPeripheryBootROMModuleImp
with HasPeripherySerialModuleImp
with HasPeripheryUARTModuleImp
@@ -64,7 +64,7 @@ class FireSim(implicit p: Parameters) extends DefaultFireSimEnvironment(() => ne
class FireSimNoNICDUT(implicit p: Parameters) extends RocketSubsystem
with HasDefaultBusConfiguration
with CanHaveFASEDOptimizedMasterAXI4MemPort
with CanHaveMasterAXI4MemPort
with HasPeripheryBootROM
with HasPeripherySerial
with HasPeripheryUART
@@ -76,7 +76,7 @@ class FireSimNoNICDUT(implicit p: Parameters) extends RocketSubsystem
class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends RocketSubsystemModuleImp(l)
with HasRTCModuleImp
with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
with CanHaveMasterAXI4MemPortModuleImp
with HasPeripheryBootROMModuleImp
with HasPeripherySerialModuleImp
with HasPeripheryUARTModuleImp
@@ -89,7 +89,7 @@ class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimEnvironment(()
class FireBoomDUT(implicit p: Parameters) extends BoomRocketSubsystem
with HasDefaultBusConfiguration
with CanHaveFASEDOptimizedMasterAXI4MemPort
with CanHaveMasterAXI4MemPort
with HasPeripheryBootROM
with HasPeripherySerial
with HasPeripheryUART
@@ -102,7 +102,7 @@ class FireBoomDUT(implicit p: Parameters) extends BoomRocketSubsystem
class FireBoomModuleImp[+L <: FireBoomDUT](l: L) extends BoomRocketSubsystemModuleImp(l)
with HasRTCModuleImp
with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
with CanHaveMasterAXI4MemPortModuleImp
with HasPeripheryBootROMModuleImp
with HasPeripherySerialModuleImp
with HasPeripheryUARTModuleImp
@@ -116,7 +116,7 @@ class FireBoom(implicit p: Parameters) extends DefaultFireSimEnvironment(() => n
class FireBoomNoNICDUT(implicit p: Parameters) extends BoomRocketSubsystem
with HasDefaultBusConfiguration
with CanHaveFASEDOptimizedMasterAXI4MemPort
with CanHaveMasterAXI4MemPort
with HasPeripheryBootROM
with HasPeripherySerial
with HasPeripheryUART
@@ -128,7 +128,7 @@ class FireBoomNoNICDUT(implicit p: Parameters) extends BoomRocketSubsystem
class FireBoomNoNICModuleImp[+L <: FireBoomNoNICDUT](l: L) extends BoomRocketSubsystemModuleImp(l)
with HasRTCModuleImp
with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
with CanHaveMasterAXI4MemPortModuleImp
with HasPeripheryBootROMModuleImp
with HasPeripherySerialModuleImp
with HasPeripheryUARTModuleImp