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Move TestHarness to chipyard.harness, make chipyard/harness directory

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This commit is contained in:
Jerry Zhao
2023-05-07 23:16:35 -07:00
parent 352cc773b5
commit ac281daa78
23 changed files with 38 additions and 38 deletions
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3
fpga/src/main/scala/arty/TestHarness.scala
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@@ -7,8 +7,7 @@ import org.chipsalliance.cde.config.{Parameters}
import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}
import chipyard.{BuildTop, HasHarnessSignalReferences}
import chipyard.harness.{ApplyHarnessBinders}
import chipyard.harness.{ApplyHarnessBinders, BuildTop, HasHarnessSignalReferences}
import chipyard.iobinders.{HasIOBinders}
class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences {

4
fpga/src/main/scala/arty100t/Harness.scala
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@@ -13,8 +13,8 @@ import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly}
import sifive.blocks.devices.uart._
import chipyard._
import chipyard.harness.{ApplyHarnessBinders}
import chipyard.{ChipTop, CanHaveMasterTLMemPort, ExtTLMem}
import chipyard.harness._
import chipyard.iobinders.{HasIOBinders}
class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell with HasHarnessSignalReferences

3
fpga/src/main/scala/vc707/Configs.scala
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@@ -17,7 +17,8 @@ import sifive.fpgashells.shell.xilinx.{VC7074GDDRSize}
import testchipip.{SerialTLKey}
import chipyard.{BuildSystem, ExtTLMem, DefaultClockFrequencyKey}
import chipyard.{BuildSystem, ExtTLMem}
import chipyard.harness.{DefaultClockFrequencyKey}
class WithDefaultPeripherals extends Config((site, here, up) => {
case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L)))

4
fpga/src/main/scala/vc707/TestHarness.scala
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@@ -16,9 +16,9 @@ import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1.{XilinxVC707PCIeX1IO}
import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO}
import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO}
import chipyard.{HasHarnessSignalReferences, BuildTop, ChipTop, ExtTLMem, CanHaveMasterTLMemPort, DefaultClockFrequencyKey}
import chipyard.{ChipTop, ExtTLMem, CanHaveMasterTLMemPort}
import chipyard.iobinders.{HasIOBinders}
import chipyard.harness.{ApplyHarnessBinders}
import chipyard.harness.{ApplyHarnessBinders, HasHarnessSignalReferences, BuildTop, DefaultClockFrequencyKey}
class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707Shell { outer =>

3
fpga/src/main/scala/vcu118/Configs.scala
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@@ -17,7 +17,8 @@ import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize}
import testchipip.{SerialTLKey}
import chipyard.{BuildSystem, ExtTLMem, DefaultClockFrequencyKey}
import chipyard.{BuildSystem, ExtTLMem}
import chipyard.harness.{DefaultClockFrequencyKey}
class WithDefaultPeripherals extends Config((site, here, up) => {
case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L)))

4
fpga/src/main/scala/vcu118/HarnessBinders.scala
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@@ -9,8 +9,8 @@ import freechips.rocketchip.tilelink.{TLBundle}
import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO}
import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO}
import chipyard.{HasHarnessSignalReferences, CanHaveMasterTLMemPort}
import chipyard.harness.{OverrideHarnessBinder}
import chipyard.{CanHaveMasterTLMemPort}
import chipyard.harness.{HasHarnessSignalReferences, OverrideHarnessBinder}
/*** UART ***/
class WithUART extends OverrideHarnessBinder({

2
fpga/src/main/scala/vcu118/TestHarness.scala
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@@ -17,7 +17,7 @@ import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO}
import chipyard._
import chipyard.iobinders.{HasIOBinders}
import chipyard.harness.{ApplyHarnessBinders}
import chipyard.harness._
class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118ShellBasicOverlays {

3
fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala
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@@ -13,8 +13,7 @@ import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp, GPIOPortIO}
import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
import chipyard.{HasHarnessSignalReferences}
import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder}
import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder, HasHarnessSignalReferences}
/*** UART ***/
class WithBringupUART extends ComposeHarnessBinder({