wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

fix top/model separation for rtl vs. post-syn/par sim

Browse Source
This commit is contained in:
Harrison Liew
2023-02-24 20:37:36 -08:00
parent 58590f2abe
commit a681bedae0
2 changed files with 7 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
vlsi/Makefile
View File

@@ -118,6 +118,12 @@ endif
$(SYN_CONF): $(VLSI_RTL)
mkdir -p $(dir $@)
echo "sim.inputs:" > $@
echo " input_files:" >> $@
for x in $(VLSI_RTL); do \
echo ' - "'$$x'"' >> $@; \
done
echo " input_files_meta: 'append'" >> $@
echo "synthesis.inputs:" >> $@
echo " top_module: $(VLSI_TOP)" >> $@
echo " input_files:" >> $@

2
vlsi/sim.mk
View File

@@ -10,7 +10,7 @@ $(SIM_CONF): $(sim_common_files)
echo " top_module: $(VLSI_TOP)" >> $@
echo " tb_name: ''" >> $@ # don't specify -top
echo " input_files:" >> $@
for x in $$(cat $(sim_common_files)); do \
for x in $$(cat $(MODEL_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) | sort -u) $(MODEL_SMEMS_FILE); do \
echo ' - "'$$x'"' >> $@; \
done
echo " input_files_meta: 'append'" >> $@