From a681bedae05fb9ae9d0d5302a9a4a5b3128eebf7 Mon Sep 17 00:00:00 2001
From: Harrison Liew <harrisonliew@gmail.com>
Date: Fri, 24 Feb 2023 20:37:36 -0800
Subject: [PATCH] fix top/model separation for rtl vs. post-syn/par sim

---
 vlsi/Makefile | 6 ++++++
 vlsi/sim.mk   | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/vlsi/Makefile b/vlsi/Makefile
index ab8438d5..97fba910 100644
--- a/vlsi/Makefile
+++ b/vlsi/Makefile
@@ -118,6 +118,12 @@ endif
 
 $(SYN_CONF): $(VLSI_RTL)
 	mkdir -p $(dir $@)
+	echo "sim.inputs:" > $@
+	echo "  input_files:" >> $@
+	for x in $(VLSI_RTL); do \
+		echo '    - "'$$x'"' >> $@; \
+	done
+	echo "  input_files_meta: 'append'" >> $@
 	echo "synthesis.inputs:" >> $@
 	echo "  top_module: $(VLSI_TOP)" >> $@
 	echo "  input_files:" >> $@
diff --git a/vlsi/sim.mk b/vlsi/sim.mk
index 5623f9d3..b487657c 100644
--- a/vlsi/sim.mk
+++ b/vlsi/sim.mk
@@ -10,7 +10,7 @@ $(SIM_CONF): $(sim_common_files)
 	echo "  top_module: $(VLSI_TOP)" >> $@
 	echo "  tb_name: ''" >> $@  # don't specify -top
 	echo "  input_files:" >> $@
-	for x in $$(cat $(sim_common_files)); do \
+	for x in $$(cat $(MODEL_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) | sort -u) $(MODEL_SMEMS_FILE); do \
 		echo '    - "'$$x'"' >> $@; \
 	done
 	echo "  input_files_meta: 'append'" >> $@