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Add more arty100t configs with configurable TSI-UART baudrate

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This commit is contained in:
Jerry Zhao
2023-02-15 21:45:09 -08:00
parent fe51a1c7ce
commit a50e7d3117
3 changed files with 23 additions and 22 deletions
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37
fpga/src/main/scala/arty100t/Configs.scala
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@@ -27,32 +27,33 @@ class WithArty100TTweaks extends Config(
new WithNoDesignKey ++ new WithNoDesignKey ++
new chipyard.config.WithNoDebug ++ // no jtag new chipyard.config.WithNoDebug ++ // no jtag
new chipyard.config.WithNoUART ++ // use UART for the UART-TSI thing instad new chipyard.config.WithNoUART ++ // use UART for the UART-TSI thing instad
new chipyard.config.WithTLBackingMemory ++ new chipyard.config.WithTLBackingMemory ++ // FPGA-shells converts the AXI to TL for us
new freechips.rocketchip.subsystem.WithExtMemSize(BigInt(256) << 20) ++ // 256mb on ARTY new freechips.rocketchip.subsystem.WithExtMemSize(BigInt(256) << 20) ++ // 256mb on ARTY
new freechips.rocketchip.subsystem.WithoutTLMonitors new freechips.rocketchip.subsystem.WithoutTLMonitors)
)
class RocketArty100TConfig extends Config( class RocketArty100TConfig extends Config(
new WithArty100TTweaks ++ new WithArty100TTweaks ++
new chipyard.config.WithMemoryBusFrequency(10.0) ++ new chipyard.config.WithMemoryBusFrequency(50.0) ++
new chipyard.config.WithPeripheryBusFrequency(10.0) ++ // Match the sbus and pbus frequency new chipyard.config.WithPeripheryBusFrequency(50.0) ++ // Match the sbus and pbus frequency
new chipyard.config.WithBroadcastManager ++ // no l2 new chipyard.config.WithBroadcastManager ++ // no l2
new chipyard.RocketConfig new chipyard.RocketConfig)
)
class UART230400RocketArty100TConfig extends Config(
new WithArty100TUARTTSI(uartBaudRate = 230400) ++
new RocketArty100TConfig)
class UART460800RocketArty100TConfig extends Config(
new WithArty100TUARTTSI(uartBaudRate = 460800) ++
new RocketArty100TConfig)
class UART921600RocketArty100TConfig extends Config(
new WithArty100TUARTTSI(uartBaudRate = 921600) ++
new RocketArty100TConfig)
class NoCoresArty100TConfig extends Config( class NoCoresArty100TConfig extends Config(
new WithArty100TTweaks ++ new WithArty100TTweaks ++
new chipyard.config.WithMemoryBusFrequency(10.0) ++ new chipyard.config.WithMemoryBusFrequency(10.0) ++
new chipyard.config.WithPeripheryBusFrequency(10.0) ++ // Match the sbus and pbus frequency new chipyard.config.WithPeripheryBusFrequency(10.0) ++ // Match the sbus and pbus frequency
new chipyard.config.WithBroadcastManager ++ // no l2 new chipyard.config.WithBroadcastManager ++ // no l2
new chipyard.NoCoresConfig new chipyard.NoCoresConfig)
)
class InitZeroNoCoresArty100TConfig extends Config(
new WithArty100TTweaks ++
new chipyard.example.WithInitZero(0x80000000L, 0x1000L) ++
new chipyard.config.WithMemoryBusFrequency(10.0) ++
new chipyard.config.WithPeripheryBusFrequency(10.0) ++ // Match the sbus and pbus frequency
new chipyard.config.WithBroadcastManager ++ // no l2
new chipyard.NoCoresConfig
)

6
fpga/src/main/scala/arty100t/HarnessBinders.scala
View File

@@ -8,7 +8,7 @@ import freechips.rocketchip.subsystem.{PeripheryBusKey}
import freechips.rocketchip.tilelink.{TLBundle} import freechips.rocketchip.tilelink.{TLBundle}
import freechips.rocketchip.util.{HeterogeneousBag} import freechips.rocketchip.util.{HeterogeneousBag}
import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp} import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp, UARTParams}
import sifive.blocks.devices.jtag.{JTAGPins, JTAGPinsFromPort} import sifive.blocks.devices.jtag.{JTAGPins, JTAGPinsFromPort}
import sifive.blocks.devices.pinctrl.{BasePin} import sifive.blocks.devices.pinctrl.{BasePin}
@@ -20,7 +20,7 @@ import chipyard.iobinders.JTAGChipIO
import testchipip._ import testchipip._
class WithArty100TUARTTSI extends OverrideHarnessBinder({ class WithArty100TUARTTSI(uartBaudRate: BigInt = 115200) extends OverrideHarnessBinder({
(system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
implicit val p = chipyard.iobinders.GetSystemParameters(system) implicit val p = chipyard.iobinders.GetSystemParameters(system)
ports.map({ port => ports.map({ port =>
@@ -29,7 +29,7 @@ class WithArty100TUARTTSI extends OverrideHarnessBinder({
val bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset) val bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset)
withClockAndReset(th.buildtopClock, th.buildtopReset) { withClockAndReset(th.buildtopClock, th.buildtopReset) {
val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset) val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset)
val uart_to_tsi = Module(new UARTToTSI(freq)) val uart_to_tsi = Module(new UARTToTSI(freq, UARTParams(0, initBaudRate=uartBaudRate)))
ram.module.io.tsi_ser.flipConnect(uart_to_tsi.io.serial) ram.module.io.tsi_ser.flipConnect(uart_to_tsi.io.serial)
ath.io_uart_bb.bundle <> uart_to_tsi.io.uart ath.io_uart_bb.bundle <> uart_to_tsi.io.uart

2
generators/testchipip

Submodule generators/testchipip updated: bfb18c3f77...4720c94e45