diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala
index af1c128f..999612fd 100644
--- a/fpga/src/main/scala/arty100t/Configs.scala
+++ b/fpga/src/main/scala/arty100t/Configs.scala
@@ -27,32 +27,33 @@ class WithArty100TTweaks extends Config(
   new WithNoDesignKey ++
   new chipyard.config.WithNoDebug ++ // no jtag
   new chipyard.config.WithNoUART ++ // use UART for the UART-TSI thing instad
-  new chipyard.config.WithTLBackingMemory ++
+  new chipyard.config.WithTLBackingMemory ++ // FPGA-shells converts the AXI to TL for us
   new freechips.rocketchip.subsystem.WithExtMemSize(BigInt(256) << 20) ++ // 256mb on ARTY
-  new freechips.rocketchip.subsystem.WithoutTLMonitors
-)
+  new freechips.rocketchip.subsystem.WithoutTLMonitors)
 
 class RocketArty100TConfig extends Config(
   new WithArty100TTweaks ++
-  new chipyard.config.WithMemoryBusFrequency(10.0) ++
-  new chipyard.config.WithPeripheryBusFrequency(10.0) ++  // Match the sbus and pbus frequency
+  new chipyard.config.WithMemoryBusFrequency(50.0) ++
+  new chipyard.config.WithPeripheryBusFrequency(50.0) ++  // Match the sbus and pbus frequency
   new chipyard.config.WithBroadcastManager ++ // no l2
-  new chipyard.RocketConfig
-)
+  new chipyard.RocketConfig)
+
+class UART230400RocketArty100TConfig extends Config(
+  new WithArty100TUARTTSI(uartBaudRate = 230400) ++
+  new RocketArty100TConfig)
+
+class UART460800RocketArty100TConfig extends Config(
+  new WithArty100TUARTTSI(uartBaudRate = 460800) ++
+  new RocketArty100TConfig)
+
+class UART921600RocketArty100TConfig extends Config(
+  new WithArty100TUARTTSI(uartBaudRate = 921600) ++
+  new RocketArty100TConfig)
+
 
 class NoCoresArty100TConfig extends Config(
   new WithArty100TTweaks ++
   new chipyard.config.WithMemoryBusFrequency(10.0) ++
   new chipyard.config.WithPeripheryBusFrequency(10.0) ++  // Match the sbus and pbus frequency
   new chipyard.config.WithBroadcastManager ++ // no l2
-  new chipyard.NoCoresConfig
-)
-
-class InitZeroNoCoresArty100TConfig extends Config(
-  new WithArty100TTweaks ++
-  new chipyard.example.WithInitZero(0x80000000L, 0x1000L) ++
-  new chipyard.config.WithMemoryBusFrequency(10.0) ++
-  new chipyard.config.WithPeripheryBusFrequency(10.0) ++  // Match the sbus and pbus frequency
-  new chipyard.config.WithBroadcastManager ++ // no l2
-  new chipyard.NoCoresConfig
-)
+  new chipyard.NoCoresConfig)
diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala
index e0b39704..567c3c29 100644
--- a/fpga/src/main/scala/arty100t/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala
@@ -8,7 +8,7 @@ import freechips.rocketchip.subsystem.{PeripheryBusKey}
 import freechips.rocketchip.tilelink.{TLBundle}
 import freechips.rocketchip.util.{HeterogeneousBag}
 
-import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp}
+import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp, UARTParams}
 import sifive.blocks.devices.jtag.{JTAGPins, JTAGPinsFromPort}
 import sifive.blocks.devices.pinctrl.{BasePin}
 
@@ -20,7 +20,7 @@ import chipyard.iobinders.JTAGChipIO
 
 import testchipip._
 
-class WithArty100TUARTTSI extends OverrideHarnessBinder({
+class WithArty100TUARTTSI(uartBaudRate: BigInt = 115200) extends OverrideHarnessBinder({
   (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
     implicit val p = chipyard.iobinders.GetSystemParameters(system)
     ports.map({ port =>
@@ -29,7 +29,7 @@ class WithArty100TUARTTSI extends OverrideHarnessBinder({
       val bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset)
       withClockAndReset(th.buildtopClock, th.buildtopReset) {
         val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset)
-        val uart_to_tsi = Module(new UARTToTSI(freq))
+        val uart_to_tsi = Module(new UARTToTSI(freq, UARTParams(0, initBaudRate=uartBaudRate)))
         ram.module.io.tsi_ser.flipConnect(uart_to_tsi.io.serial)
 
         ath.io_uart_bb.bundle <> uart_to_tsi.io.uart
diff --git a/generators/testchipip b/generators/testchipip
index bfb18c3f..4720c94e 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit bfb18c3f77e351f95c2d41002763a9941640df98
+Subproject commit 4720c94e45803a00c08136bf7f762abab892a864