Update CI

This commit is contained in:
Zitao Fang
2020-09-18 15:36:14 -07:00
parent 1543acfacd
commit a43400acb9
5 changed files with 124 additions and 22 deletions

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@@ -262,11 +262,31 @@ jobs:
steps: steps:
- prepare-rtl: - prepare-rtl:
project-key: "chipyard-ariane" project-key: "chipyard-ariane"
prepare-chipyard-sodor: prepare-chipyard-sodor-stage1:
executor: main-env executor: main-env
steps: steps:
- prepare-rtl: - prepare-rtl:
project-key: "chipyard-sodor" project-key: "chipyard-sodor-stage1"
prepare-chipyard-sodor-stage2:
executor: main-env
steps:
- prepare-rtl:
project-key: "chipyard-sodor-stage2"
prepare-chipyard-sodor-stage3:
executor: main-env
steps:
- prepare-rtl:
project-key: "chipyard-sodor-stage3"
prepare-chipyard-sodor-stage5:
executor: main-env
steps:
- prepare-rtl:
project-key: "chipyard-sodor-stage5"
prepare-chipyard-sodor-ucode:
executor: main-env
steps:
- prepare-rtl:
project-key: "chipyard-sodor-ucode"
prepare-icenet: prepare-icenet:
executor: main-env executor: main-env
steps: steps:
@@ -395,11 +415,35 @@ jobs:
- run-tests: - run-tests:
project-key: "chipyard-ariane" project-key: "chipyard-ariane"
timeout: "30m" timeout: "30m"
chipyard-sodor-run-tests: chipyard-sodor-stage1-run-tests:
executor: main-env executor: main-env
steps: steps:
- run-tests: - run-tests:
project-key: "chipyard-sodor" project-key: "chipyard-sodor-stage1"
timeout: "20m"
chipyard-sodor-stage2-run-tests:
executor: main-env
steps:
- run-tests:
project-key: "chipyard-sodor-stage2"
timeout: "20m"
chipyard-sodor-stage3-run-tests:
executor: main-env
steps:
- run-tests:
project-key: "chipyard-sodor-stage3"
timeout: "20m"
chipyard-sodor-stage5-run-tests:
executor: main-env
steps:
- run-tests:
project-key: "chipyard-sodor-stage5"
timeout: "20m"
chipyard-sodor-ucode-run-tests:
executor: main-env
steps:
- run-tests:
project-key: "chipyard-sodor-ucode"
timeout: "20m" timeout: "20m"
chipyard-nvdla-run-tests: chipyard-nvdla-run-tests:
executor: main-env executor: main-env
@@ -522,7 +566,27 @@ workflows:
- install-riscv-toolchain - install-riscv-toolchain
- install-verilator - install-verilator
- prepare-chipyard-sodor: - prepare-chipyard-sodor-stage1:
requires:
- install-riscv-toolchain
- install-verilator
- prepare-chipyard-sodor-stage2:
requires:
- install-riscv-toolchain
- install-verilator
- prepare-chipyard-sodor-stage3:
requires:
- install-riscv-toolchain
- install-verilator
- prepare-chipyard-sodor-stage5:
requires:
- install-riscv-toolchain
- install-verilator
- prepare-chipyard-sodor-ucode:
requires: requires:
- install-riscv-toolchain - install-riscv-toolchain
- install-verilator - install-verilator
@@ -632,9 +696,25 @@ workflows:
requires: requires:
- prepare-chipyard-ariane - prepare-chipyard-ariane
- chipyard-sodor-run-tests: - chipyard-sodor-stage1-run-tests:
requires: requires:
- prepare-chipyard-sodor - prepare-chipyard-sodor-stage1
- chipyard-sodor-stage2-run-tests:
requires:
- prepare-chipyard-sodor-stage2
- chipyard-sodor-stage3-run-tests:
requires:
- prepare-chipyard-sodor-stage3
- chipyard-sodor-stage5-run-tests:
requires:
- prepare-chipyard-sodor-stage5
- chipyard-sodor-ucode-run-tests:
requires:
- prepare-chipyard-sodor-ucode
- chipyard-nvdla-run-tests: - chipyard-nvdla-run-tests:
requires: requires:

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@@ -69,4 +69,8 @@ mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Test
mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests" mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests"
mapping["icenet"]="SUB_PROJECT=icenet" mapping["icenet"]="SUB_PROJECT=icenet"
mapping["testchipip"]="SUB_PROJECT=testchipip" mapping["testchipip"]="SUB_PROJECT=testchipip"
mapping["chipyard-sodor-stage1"]="SUB_PROJEET=Sodor1StageConfig"
mapping["chipyard-sodor-stage2"]="SUB_PROJEET=Sodor2StageConfig"
mapping["chipyard-sodor-stage3"]="SUB_PROJEET=Sodor3StageSinglePortConfig"
mapping["chipyard-sodor-stage5"]="SUB_PROJEET=Sodor5StageConfig"
mapping["chipyard-sodor-ucode"]="SUB_PROJEET=SodorUCodeConfig"

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@@ -91,7 +91,19 @@ case $1 in
chipyard-ariane) chipyard-ariane)
make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv
;; ;;
chipyard-sodor) chipyard-sodor-stage1)
run_asm ${mapping[$1]}
;;
chipyard-sodor-stage2)
run_asm ${mapping[$1]}
;;
chipyard-sodor-stage3)
run_asm ${mapping[$1]}
;;
chipyard-sodor-stage5)
run_asm ${mapping[$1]}
;;
chipyard-sodor-ucode)
run_asm ${mapping[$1]} run_asm ${mapping[$1]}
;; ;;
chipyard-nvdla) chipyard-nvdla)

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@@ -5,43 +5,49 @@ import chisel3._
import freechips.rocketchip.config.{Config} import freechips.rocketchip.config.{Config}
class Sodor1StageConfig extends Config( class Sodor1StageConfig extends Config(
// Create a Sodor 1-stage core
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++ new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory
new freechips.rocketchip.subsystem.WithNBanks(0) ++ new freechips.rocketchip.subsystem.WithNBanks(0) ++
new chipyard.config.AbstractConfig) new chipyard.config.AbstractConfig)
class Sodor2StageConfig extends Config( class Sodor2StageConfig extends Config(
// Create a Sodor 2-stage core
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++ new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory
new freechips.rocketchip.subsystem.WithNBanks(0) ++ new freechips.rocketchip.subsystem.WithNBanks(0) ++
new chipyard.config.AbstractConfig) new chipyard.config.AbstractConfig)
class Sodor3StageConfig extends Config( class Sodor3StageConfig extends Config(
// Create a Sodor 1-stage core with two ports
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++ new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory
new freechips.rocketchip.subsystem.WithNBanks(0) ++ new freechips.rocketchip.subsystem.WithNBanks(0) ++
new chipyard.config.AbstractConfig) new chipyard.config.AbstractConfig)
class Sodor3StageSinglePortConfig extends Config( class Sodor3StageSinglePortConfig extends Config(
// Create a Sodor 3-stage core with one ports (instruction and data memory access controlled by arbiter)
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++ new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory
new freechips.rocketchip.subsystem.WithNBanks(0) ++ new freechips.rocketchip.subsystem.WithNBanks(0) ++
new chipyard.config.AbstractConfig) new chipyard.config.AbstractConfig)
class Sodor5StageConfig extends Config( class Sodor5StageConfig extends Config(
// Create a Sodor 5-stage core
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++ new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory
new freechips.rocketchip.subsystem.WithNBanks(0) ++ new freechips.rocketchip.subsystem.WithNBanks(0) ++
new chipyard.config.AbstractConfig) new chipyard.config.AbstractConfig)
class SodorUCodeConfig extends Config( class SodorUCodeConfig extends Config(
// Construct a Sodor microcode-based single-bus core
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++ new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory
new freechips.rocketchip.subsystem.WithNBanks(0) ++ new freechips.rocketchip.subsystem.WithNBanks(0) ++
new chipyard.config.AbstractConfig) new chipyard.config.AbstractConfig)