From a43400acb9f0397c18c510d72827933fb1e65991 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 18 Sep 2020 15:36:14 -0700 Subject: [PATCH] Update CI --- .circleci/config.yml | 94 +++++++++++++++++-- .circleci/defaults.sh | 6 +- .circleci/run-tests.sh | 14 ++- .../src/main/scala/config/SodorConfigs.scala | 30 +++--- generators/riscv-sodor | 2 +- 5 files changed, 124 insertions(+), 22 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 7b09791c..a695cf28 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -262,11 +262,31 @@ jobs: steps: - prepare-rtl: project-key: "chipyard-ariane" - prepare-chipyard-sodor: + prepare-chipyard-sodor-stage1: executor: main-env steps: - prepare-rtl: - project-key: "chipyard-sodor" + project-key: "chipyard-sodor-stage1" + prepare-chipyard-sodor-stage2: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-sodor-stage2" + prepare-chipyard-sodor-stage3: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-sodor-stage3" + prepare-chipyard-sodor-stage5: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-sodor-stage5" + prepare-chipyard-sodor-ucode: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-sodor-ucode" prepare-icenet: executor: main-env steps: @@ -395,11 +415,35 @@ jobs: - run-tests: project-key: "chipyard-ariane" timeout: "30m" - chipyard-sodor-run-tests: + chipyard-sodor-stage1-run-tests: executor: main-env steps: - run-tests: - project-key: "chipyard-sodor" + project-key: "chipyard-sodor-stage1" + timeout: "20m" + chipyard-sodor-stage2-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-sodor-stage2" + timeout: "20m" + chipyard-sodor-stage3-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-sodor-stage3" + timeout: "20m" + chipyard-sodor-stage5-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-sodor-stage5" + timeout: "20m" + chipyard-sodor-ucode-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-sodor-ucode" timeout: "20m" chipyard-nvdla-run-tests: executor: main-env @@ -522,7 +566,27 @@ workflows: - install-riscv-toolchain - install-verilator - - prepare-chipyard-sodor: + - prepare-chipyard-sodor-stage1: + requires: + - install-riscv-toolchain + - install-verilator + + - prepare-chipyard-sodor-stage2: + requires: + - install-riscv-toolchain + - install-verilator + + - prepare-chipyard-sodor-stage3: + requires: + - install-riscv-toolchain + - install-verilator + + - prepare-chipyard-sodor-stage5: + requires: + - install-riscv-toolchain + - install-verilator + + - prepare-chipyard-sodor-ucode: requires: - install-riscv-toolchain - install-verilator @@ -632,9 +696,25 @@ workflows: requires: - prepare-chipyard-ariane - - chipyard-sodor-run-tests: + - chipyard-sodor-stage1-run-tests: requires: - - prepare-chipyard-sodor + - prepare-chipyard-sodor-stage1 + + - chipyard-sodor-stage2-run-tests: + requires: + - prepare-chipyard-sodor-stage2 + + - chipyard-sodor-stage3-run-tests: + requires: + - prepare-chipyard-sodor-stage3 + + - chipyard-sodor-stage5-run-tests: + requires: + - prepare-chipyard-sodor-stage5 + + - chipyard-sodor-ucode-run-tests: + requires: + - prepare-chipyard-sodor-ucode - chipyard-nvdla-run-tests: requires: diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 703737cd..62b9ceb4 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -69,4 +69,8 @@ mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Test mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests" mapping["icenet"]="SUB_PROJECT=icenet" mapping["testchipip"]="SUB_PROJECT=testchipip" - +mapping["chipyard-sodor-stage1"]="SUB_PROJEET=Sodor1StageConfig" +mapping["chipyard-sodor-stage2"]="SUB_PROJEET=Sodor2StageConfig" +mapping["chipyard-sodor-stage3"]="SUB_PROJEET=Sodor3StageSinglePortConfig" +mapping["chipyard-sodor-stage5"]="SUB_PROJEET=Sodor5StageConfig" +mapping["chipyard-sodor-ucode"]="SUB_PROJEET=SodorUCodeConfig" diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index c0b932b6..cd4afd23 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -91,7 +91,19 @@ case $1 in chipyard-ariane) make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv ;; - chipyard-sodor) + chipyard-sodor-stage1) + run_asm ${mapping[$1]} + ;; + chipyard-sodor-stage2) + run_asm ${mapping[$1]} + ;; + chipyard-sodor-stage3) + run_asm ${mapping[$1]} + ;; + chipyard-sodor-stage5) + run_asm ${mapping[$1]} + ;; + chipyard-sodor-ucode) run_asm ${mapping[$1]} ;; chipyard-nvdla) diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala index df386dd9..eb7b4086 100644 --- a/generators/chipyard/src/main/scala/config/SodorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala @@ -5,43 +5,49 @@ import chisel3._ import freechips.rocketchip.config.{Config} class Sodor1StageConfig extends Config( + // Create a Sodor 1-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ new chipyard.config.AbstractConfig) class Sodor2StageConfig extends Config( + // Create a Sodor 2-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ new chipyard.config.AbstractConfig) class Sodor3StageConfig extends Config( + // Create a Sodor 1-stage core with two ports new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ new chipyard.config.AbstractConfig) class Sodor3StageSinglePortConfig extends Config( + // Create a Sodor 3-stage core with one ports (instruction and data memory access controlled by arbiter) new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ new chipyard.config.AbstractConfig) class Sodor5StageConfig extends Config( + // Create a Sodor 5-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ new chipyard.config.AbstractConfig) class SodorUCodeConfig extends Config( + // Construct a Sodor microcode-based single-bus core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ new chipyard.config.AbstractConfig) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 43985218..69df2b01 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 43985218b8c91c9206018177d81e37e27267dbf6 +Subproject commit 69df2b013f162cf4c450cdc3e7bbd6e7b9f2de16