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@@ -262,11 +262,31 @@ jobs:
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steps:
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steps:
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- prepare-rtl:
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- prepare-rtl:
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project-key: "chipyard-ariane"
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project-key: "chipyard-ariane"
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prepare-chipyard-sodor:
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prepare-chipyard-sodor-stage1:
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executor: main-env
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executor: main-env
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steps:
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steps:
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- prepare-rtl:
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- prepare-rtl:
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project-key: "chipyard-sodor"
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project-key: "chipyard-sodor-stage1"
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prepare-chipyard-sodor-stage2:
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executor: main-env
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steps:
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- prepare-rtl:
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project-key: "chipyard-sodor-stage2"
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prepare-chipyard-sodor-stage3:
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executor: main-env
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steps:
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- prepare-rtl:
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project-key: "chipyard-sodor-stage3"
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prepare-chipyard-sodor-stage5:
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executor: main-env
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steps:
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- prepare-rtl:
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project-key: "chipyard-sodor-stage5"
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prepare-chipyard-sodor-ucode:
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executor: main-env
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steps:
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- prepare-rtl:
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project-key: "chipyard-sodor-ucode"
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prepare-icenet:
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prepare-icenet:
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executor: main-env
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executor: main-env
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steps:
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steps:
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@@ -395,11 +415,35 @@ jobs:
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- run-tests:
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- run-tests:
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project-key: "chipyard-ariane"
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project-key: "chipyard-ariane"
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timeout: "30m"
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timeout: "30m"
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chipyard-sodor-run-tests:
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chipyard-sodor-stage1-run-tests:
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executor: main-env
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executor: main-env
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steps:
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steps:
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- run-tests:
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- run-tests:
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project-key: "chipyard-sodor"
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project-key: "chipyard-sodor-stage1"
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timeout: "20m"
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chipyard-sodor-stage2-run-tests:
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executor: main-env
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steps:
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- run-tests:
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project-key: "chipyard-sodor-stage2"
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timeout: "20m"
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chipyard-sodor-stage3-run-tests:
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executor: main-env
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steps:
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- run-tests:
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project-key: "chipyard-sodor-stage3"
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timeout: "20m"
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chipyard-sodor-stage5-run-tests:
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executor: main-env
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steps:
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- run-tests:
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project-key: "chipyard-sodor-stage5"
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timeout: "20m"
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chipyard-sodor-ucode-run-tests:
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executor: main-env
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steps:
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- run-tests:
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project-key: "chipyard-sodor-ucode"
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timeout: "20m"
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timeout: "20m"
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chipyard-nvdla-run-tests:
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chipyard-nvdla-run-tests:
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executor: main-env
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executor: main-env
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@@ -522,7 +566,27 @@ workflows:
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- install-riscv-toolchain
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- install-riscv-toolchain
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- install-verilator
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- install-verilator
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- prepare-chipyard-sodor:
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- prepare-chipyard-sodor-stage1:
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requires:
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- install-riscv-toolchain
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- install-verilator
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- prepare-chipyard-sodor-stage2:
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requires:
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- install-riscv-toolchain
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- install-verilator
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- prepare-chipyard-sodor-stage3:
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requires:
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- install-riscv-toolchain
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- install-verilator
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- prepare-chipyard-sodor-stage5:
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requires:
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- install-riscv-toolchain
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- install-verilator
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- prepare-chipyard-sodor-ucode:
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requires:
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requires:
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- install-riscv-toolchain
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- install-riscv-toolchain
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- install-verilator
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- install-verilator
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@@ -632,9 +696,25 @@ workflows:
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requires:
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requires:
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- prepare-chipyard-ariane
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- prepare-chipyard-ariane
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- chipyard-sodor-run-tests:
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- chipyard-sodor-stage1-run-tests:
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requires:
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requires:
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- prepare-chipyard-sodor
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- prepare-chipyard-sodor-stage1
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- chipyard-sodor-stage2-run-tests:
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requires:
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- prepare-chipyard-sodor-stage2
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- chipyard-sodor-stage3-run-tests:
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requires:
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- prepare-chipyard-sodor-stage3
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- chipyard-sodor-stage5-run-tests:
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requires:
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- prepare-chipyard-sodor-stage5
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- chipyard-sodor-ucode-run-tests:
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requires:
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- prepare-chipyard-sodor-ucode
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- chipyard-nvdla-run-tests:
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- chipyard-nvdla-run-tests:
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requires:
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requires:
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@@ -69,4 +69,8 @@ mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Test
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mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests"
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mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests"
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mapping["icenet"]="SUB_PROJECT=icenet"
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mapping["icenet"]="SUB_PROJECT=icenet"
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mapping["testchipip"]="SUB_PROJECT=testchipip"
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mapping["testchipip"]="SUB_PROJECT=testchipip"
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mapping["chipyard-sodor-stage1"]="SUB_PROJEET=Sodor1StageConfig"
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mapping["chipyard-sodor-stage2"]="SUB_PROJEET=Sodor2StageConfig"
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mapping["chipyard-sodor-stage3"]="SUB_PROJEET=Sodor3StageSinglePortConfig"
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mapping["chipyard-sodor-stage5"]="SUB_PROJEET=Sodor5StageConfig"
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mapping["chipyard-sodor-ucode"]="SUB_PROJEET=SodorUCodeConfig"
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@@ -91,7 +91,19 @@ case $1 in
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chipyard-ariane)
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chipyard-ariane)
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make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv
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make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv
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;;
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;;
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chipyard-sodor)
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chipyard-sodor-stage1)
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run_asm ${mapping[$1]}
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;;
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chipyard-sodor-stage2)
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run_asm ${mapping[$1]}
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;;
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chipyard-sodor-stage3)
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run_asm ${mapping[$1]}
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;;
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chipyard-sodor-stage5)
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run_asm ${mapping[$1]}
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;;
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chipyard-sodor-ucode)
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run_asm ${mapping[$1]}
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run_asm ${mapping[$1]}
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;;
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;;
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chipyard-nvdla)
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chipyard-nvdla)
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@@ -5,43 +5,49 @@ import chisel3._
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import freechips.rocketchip.config.{Config}
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import freechips.rocketchip.config.{Config}
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class Sodor1StageConfig extends Config(
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class Sodor1StageConfig extends Config(
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// Create a Sodor 1-stage core
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new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++
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new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++
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new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad
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new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
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new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++
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new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory
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new freechips.rocketchip.subsystem.WithNBanks(0) ++
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new freechips.rocketchip.subsystem.WithNBanks(0) ++
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new chipyard.config.AbstractConfig)
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new chipyard.config.AbstractConfig)
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class Sodor2StageConfig extends Config(
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class Sodor2StageConfig extends Config(
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// Create a Sodor 2-stage core
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new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++
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new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++
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new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad
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new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
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new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++
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new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory
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new freechips.rocketchip.subsystem.WithNBanks(0) ++
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new freechips.rocketchip.subsystem.WithNBanks(0) ++
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new chipyard.config.AbstractConfig)
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new chipyard.config.AbstractConfig)
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class Sodor3StageConfig extends Config(
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class Sodor3StageConfig extends Config(
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// Create a Sodor 1-stage core with two ports
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new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++
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new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++
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new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad
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new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
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new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++
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new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory
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new freechips.rocketchip.subsystem.WithNBanks(0) ++
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new freechips.rocketchip.subsystem.WithNBanks(0) ++
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new chipyard.config.AbstractConfig)
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new chipyard.config.AbstractConfig)
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class Sodor3StageSinglePortConfig extends Config(
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class Sodor3StageSinglePortConfig extends Config(
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// Create a Sodor 3-stage core with one ports (instruction and data memory access controlled by arbiter)
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new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++
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new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++
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new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad
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new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
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new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++
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new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory
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new freechips.rocketchip.subsystem.WithNBanks(0) ++
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new freechips.rocketchip.subsystem.WithNBanks(0) ++
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new chipyard.config.AbstractConfig)
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new chipyard.config.AbstractConfig)
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class Sodor5StageConfig extends Config(
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class Sodor5StageConfig extends Config(
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// Create a Sodor 5-stage core
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new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++
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new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++
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new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad
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new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
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new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++
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new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory
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new freechips.rocketchip.subsystem.WithNBanks(0) ++
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new freechips.rocketchip.subsystem.WithNBanks(0) ++
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new chipyard.config.AbstractConfig)
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new chipyard.config.AbstractConfig)
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class SodorUCodeConfig extends Config(
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class SodorUCodeConfig extends Config(
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// Construct a Sodor microcode-based single-bus core
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new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++
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new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++
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new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad
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new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
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new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++
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new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory
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new freechips.rocketchip.subsystem.WithNBanks(0) ++
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new freechips.rocketchip.subsystem.WithNBanks(0) ++
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new chipyard.config.AbstractConfig)
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new chipyard.config.AbstractConfig)
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Submodule generators/riscv-sodor updated: 43985218b8...69df2b013f
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Block a user