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Merge pull request #69 from ucb-bar/rebar-dev-boom

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[rebar] add sifive blocks | add rebar configs for boom
This commit is contained in:
Abraham Gonzalez
2019-04-23 15:46:44 -07:00
committed by GitHub
parent b65c2a6704 978832df93
commit a3516a3fce
15 changed files with 590 additions and 113 deletions
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3
.gitmodules vendored
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@@ -25,3 +25,6 @@
[submodule "generators/boom"]
path = generators/boom
url = git@github.com:riscv-boom/riscv-boom.git
[submodule "generators/sifive-blocks"]
path = generators/sifive-blocks
url = git@github.com:sifive/sifive-blocks.git

2
README.md
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@@ -2,7 +2,7 @@
**This branch is under development**
**It currently has many submodules**
**Please run ./scripts/init-submodules-no-riscv-tools.sh to update submodules, unless you want to spend a long time waiting for submodule to clone**
**Please run ./scripts/init-submodules-no-riscv-tools.sh to update submodules, unless you want to spend a long time waiting for submodules to clone**
This is a starter template for your custom RISC-V project. It will allow you
to leverage the Chisel HDL and RocketChip SoC generator to produce a

15
build.sbt
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@@ -24,10 +24,14 @@ lazy val rebarFirrtl = (project in file("tools/firrtl"))
lazy val rocketchip = RootProject(file("generators/rocket-chip"))
lazy val testchipip = (project in file("generators/testchipip"))
lazy val rebarrocketchip = project
.dependsOn(rocketchip)
.settings(commonSettings)
lazy val testchipip = (project in file("generators/testchipip"))
.dependsOn(rebarrocketchip)
.settings(commonSettings)
// Checks for -DROCKET_USE_MAVEN.
// If it's there, use a maven dependency.
// Else, depend on subprojects in git submodules.
@@ -42,10 +46,11 @@ def conditionalDependsOn(prj: Project): Project = {
}
lazy val example = conditionalDependsOn(project in file("."))
.dependsOn(boom, sifive_blocks)
.settings(commonSettings)
lazy val boom = (project in file("generators/boom"))
.dependsOn(rocketchip)
.dependsOn(rebarrocketchip)
.settings(commonSettings)
lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/"))
@@ -56,6 +61,10 @@ lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/"))
.settings(commonSettings)
lazy val `barstools-macros` = (project in file("./tools/barstools/macros/"))
.dependsOn(mdf, rocketchip, rebarFirrtl)
.dependsOn(mdf, rebarrocketchip, rebarFirrtl)
.enablePlugins(sbtassembly.AssemblyPlugin)
.settings(commonSettings)
lazy val sifive_blocks = (project in file("generators/sifive-blocks"))
.dependsOn(rebarrocketchip)
.settings(commonSettings)

2
common.mk
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@@ -53,7 +53,7 @@ $(VERILOG_FILE) $(SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FI
cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_top_blackboxes)
$(HARNESS_FILE) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes)
cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) -td $(build_dir)"
cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) -td $(build_dir)"
grep -v "SimSerial.cc\|SimDTM.cc\|SimJTAG.cc" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes)
# This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs

1
generators/sifive-blocks Submodule

Submodule generators/sifive-blocks added at 24dd537894

12
sims/verisim/Makefile
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@@ -41,11 +41,11 @@ include $(sim_dir)/verilator.mk
model_dir = $(build_dir)/$(long_name)
model_dir_debug = $(build_dir)/$(long_name).debug
model_header = $(model_dir)/V$(MODEL).h
model_header_debug = $(model_dir_debug)/V$(MODEL).h
model_header = $(model_dir)/V$(VLOG_MODEL).h
model_header_debug = $(model_dir_debug)/V$(VLOG_MODEL).h
model_mk = $(model_dir)/V$(MODEL).mk
model_mk_debug = $(model_dir_debug)/V$(MODEL).mk
model_mk = $(model_dir)/V$(VLOG_MODEL).mk
model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk
#########################################################################################
# build makefile fragment that builds the verilator sim rules
@@ -72,10 +72,10 @@ $(model_mk_debug): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
# invoke make to make verilator sim rules
#########################################################################################
$(sim): $(model_mk)
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name) -f V$(MODEL).mk
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name) -f V$(VLOG_MODEL).mk
$(sim_debug): $(model_mk_debug)
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(MODEL).mk
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(VLOG_MODEL).mk
#########################################################################################
# create a vcs vpd rule

4
sims/verisim/verilator.mk
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@@ -39,9 +39,9 @@ verilator/verilator-$(VERILATOR_VERSION).tar.gz:
#########################################################################################
VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS
VERILATOR_FLAGS := --top-module $(MODEL) \
VERILATOR_FLAGS := --top-module $(VLOG_MODEL) \
+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
+define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
--output-split 20000 \
-Wno-STMTDLY --x-assign unique \
-O3 -CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(MODEL) -DVERILATOR"
-O3 -CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(VLOG_MODEL) -DVERILATOR"

1
src/main/resources/project-template/bootrom Symbolic link
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@@ -0,0 +1 @@
../../../../generators/rocket-chip/bootrom/

170
src/main/scala/example/ConfigMixins.scala Normal file
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@@ -0,0 +1,170 @@
package example
import chisel3._
import freechips.rocketchip.config.{Parameters, Config}
import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32}
import freechips.rocketchip.diplomacy.{LazyModule, ValName}
import freechips.rocketchip.devices.tilelink.BootROMParams
import freechips.rocketchip.tile.XLen
import testchipip._
import sifive.blocks.devices.gpio._
/**
* TODO: Why do we need this?
*/
object ConfigValName {
implicit val valName = ValName("TestHarness")
}
import ConfigValName._
// -----------------------
// Common Parameter Mixins
// -----------------------
/**
* Class to specify where the BootRom file is (from `rebar` top)
*/
class WithBootROM extends Config((site, here, up) => {
case BootROMParams => BootROMParams(
contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img")
})
/**
* Class to add in GPIO
*/
class WithGPIO extends Config((site, here, up) => {
case PeripheryGPIOKey => List(
GPIOParams(address = 0x10012000, width = 4, includeIOF = false))
})
// ----------------------------------------
// Rocket Top Level System Parameter Mixins
// ----------------------------------------
/**
* Class to specify a "plain" top level rocket-chip system
*/
class WithNormalRocketTop extends Config((site, here, up) => {
case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
Module(LazyModule(new RocketTop()(p)).module)
}
})
/**
* Class to specify a top level rocket-chip system with PWM
*/
class WithPWMRocketTop extends Config((site, here, up) => {
case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) =>
Module(LazyModule(new RocketTopWithPWMTL()(p)).module)
})
/**
* Class to specify a top level rocket-chip system with a PWM AXI4
*/
class WithPWMAXI4RocketTop extends Config((site, here, up) => {
case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) =>
Module(LazyModule(new RocketTopWithPWMAXI4()(p)).module)
})
/**
* Class to specify a top level rocket-chip system with a block device
*/
class WithBlockDeviceModelRocketTop extends Config((site, here, up) => {
case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
val top = Module(LazyModule(new RocketTopWithBlockDevice()(p)).module)
top.connectBlockDeviceModel()
top
}
})
/**
* Class to specify a top level rocket-chip system with a simulator block device
*/
class WithSimBlockDeviceRocketTop extends Config((site, here, up) => {
case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
val top = Module(LazyModule(new RocketTopWithBlockDevice()(p)).module)
top.connectSimBlockDevice(clock, reset)
top
}
})
/**
* Class to specify a top level rocket-chip system with GPIO
*/
class WithGPIORocketTop extends Config((site, here, up) => {
case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
val top = Module(LazyModule(new RocketTopWithGPIO()(p)).module)
for (gpio <- top.gpio) {
for (pin <- gpio.pins) {
pin.i.ival := false.B
}
}
top
}
})
// --------------------------------------
// BOOM Top Level System Parameter Mixins
// --------------------------------------
/**
* Class to specify a "plain" top level BOOM system
*/
class WithNormalBoomTop extends Config((site, here, up) => {
case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => {
Module(LazyModule(new BoomTop()(p)).module)
}
})
/**
* Class to specify a top level BOOM system with PWM
*/
class WithPWMBoomTop extends Config((site, here, up) => {
case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) =>
Module(LazyModule(new BoomTopWithPWMTL()(p)).module)
})
/**
* Class to specify a top level BOOM system with a PWM AXI4
*/
class WithPWMAXI4BoomTop extends Config((site, here, up) => {
case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) =>
Module(LazyModule(new BoomTopWithPWMAXI4()(p)).module)
})
/**
* Class to specify a top level BOOM system with a block device
*/
class WithBlockDeviceModelBoomTop extends Config((site, here, up) => {
case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => {
val top = Module(LazyModule(new BoomTopWithBlockDevice()(p)).module)
top.connectBlockDeviceModel()
top
}
})
/**
* Class to specify a top level BOOM system with a simulator block device
*/
class WithSimBlockDeviceBoomTop extends Config((site, here, up) => {
case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => {
val top = Module(LazyModule(new BoomTopWithBlockDevice()(p)).module)
top.connectSimBlockDevice(clock, reset)
top
}
})
/**
* Class to specify a top level BOOM system with GPIO
*/
class WithGPIOBoomTop extends Config((site, here, up) => {
case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => {
val top = Module(LazyModule(new BoomTopWithGPIO()(p)).module)
for (gpio <- top.gpio) {
for (pin <- gpio.pins) {
pin.i.ival := false.B
}
}
top
}
})

145
src/main/scala/example/Configs.scala
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@@ -1,84 +1,101 @@
package example
import chisel3._
import freechips.rocketchip.config.{Parameters, Config}
import freechips.rocketchip.config.{Config}
import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32}
import freechips.rocketchip.diplomacy.{LazyModule, ValName}
import freechips.rocketchip.devices.tilelink.BootROMParams
import freechips.rocketchip.tile.XLen
import testchipip._
class WithBootROM extends Config((site, here, up) => {
case BootROMParams => BootROMParams(
contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img")
})
// --------------
// Rocket Configs
// --------------
object ConfigValName {
implicit val valName = ValName("TestHarness")
}
import ConfigValName._
class WithExampleTop extends Config((site, here, up) => {
case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
Module(LazyModule(new ExampleTop()(p)).module)
}
})
class WithPWM extends Config((site, here, up) => {
case BuildTop => (clock: Clock, reset: Bool, p: Parameters) =>
Module(LazyModule(new ExampleTopWithPWMTL()(p)).module)
})
class WithPWMAXI4 extends Config((site, here, up) => {
case BuildTop => (clock: Clock, reset: Bool, p: Parameters) =>
Module(LazyModule(new ExampleTopWithPWMAXI4()(p)).module)
})
class WithBlockDeviceModel extends Config((site, here, up) => {
case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
val top = Module(LazyModule(new ExampleTopWithBlockDevice()(p)).module)
top.connectBlockDeviceModel()
top
}
})
class WithSimBlockDevice extends Config((site, here, up) => {
case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
val top = Module(LazyModule(new ExampleTopWithBlockDevice()(p)).module)
top.connectSimBlockDevice(clock, reset)
top
}
})
class BaseExampleConfig extends Config(
class BaseRocketConfig extends Config(
new WithBootROM ++
new freechips.rocketchip.system.DefaultConfig)
class DefaultExampleConfig extends Config(
new WithExampleTop ++ new BaseExampleConfig)
class DefaultRocketConfig extends Config(
new WithNormalRocketTop ++
new BaseRocketConfig)
class RoccExampleConfig extends Config(
new WithRoccExample ++ new DefaultExampleConfig)
class RoccRocketConfig extends Config(
new WithRoccExample ++
new DefaultRocketConfig)
class PWMConfig extends Config(new WithPWM ++ new BaseExampleConfig)
class PWMRocketConfig extends Config(
new WithPWMRocketTop ++
new BaseRocketConfig)
class PWMAXI4Config extends Config(new WithPWMAXI4 ++ new BaseExampleConfig)
class PWMAXI4RocketConfig extends Config(
new WithPWMAXI4RocketTop ++
new BaseRocketConfig)
class SimBlockDeviceConfig extends Config(
new WithBlockDevice ++ new WithSimBlockDevice ++ new BaseExampleConfig)
class SimBlockDeviceRocketConfig extends Config(
new WithBlockDevice ++
new WithSimBlockDeviceRocketTop ++
new BaseRocketConfig)
class BlockDeviceModelConfig extends Config(
new WithBlockDevice ++ new WithBlockDeviceModel ++ new BaseExampleConfig)
class BlockDeviceModelRocketConfig extends Config(
new WithBlockDevice ++
new WithBlockDeviceModelRocketTop ++
new BaseRocketConfig)
class WithTwoTrackers extends WithNBlockDeviceTrackers(2)
class WithFourTrackers extends WithNBlockDeviceTrackers(4)
class DualCoreRocketConfig extends Config(
new WithNBigCores(2) ++
new DefaultRocketConfig)
class WithTwoMemChannels extends WithNMemoryChannels(2)
class WithFourMemChannels extends WithNMemoryChannels(4)
class RV32RocketConfig extends Config(
new WithRV32 ++
new DefaultRocketConfig)
class DualCoreConfig extends Config(
class GPIORocketConfig extends Config(
new WithGPIO ++
new WithGPIORocketTop ++
new BaseRocketConfig)
// ------------
// BOOM Configs
// ------------
class BaseBoomConfig extends Config(
new WithBootROM ++
new boom.system.BoomConfig)
class DefaultBoomConfig extends Config(
new WithNormalBoomTop ++
new BaseBoomConfig)
class RoccBoomConfig extends Config(
new WithRoccExample ++
new DefaultBoomConfig)
class PWMBoomConfig extends Config(
new WithPWMBoomTop ++
new BaseBoomConfig)
class PWMAXI4BoomConfig extends Config(
new WithPWMAXI4BoomTop ++
new BaseBoomConfig)
class SimBlockDeviceBoomConfig extends Config(
new WithBlockDevice ++
new WithSimBlockDeviceBoomTop ++
new BaseBoomConfig)
class BlockDeviceModelBoomConfig extends Config(
new WithBlockDevice ++
new WithBlockDeviceModelBoomTop ++
new BaseBoomConfig)
class DualCoreBoomConfig extends Config(
// Core gets tacked onto existing list
new WithNBigCores(2) ++ new DefaultExampleConfig)
new boom.system.WithNBoomCores(2) ++
new DefaultBoomConfig)
class RV32ExampleConfig extends Config(
new WithRV32 ++ new DefaultExampleConfig)
class RV32BoomConfig extends Config(
new WithBootROM ++
new boom.system.SmallRV32UnifiedBoomConfig)
class GPIOBoomConfig extends Config(
new WithGPIO ++
new WithGPIOBoomTop ++
new BaseBoomConfig)

138
src/main/scala/example/Generator.scala Normal file
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@@ -0,0 +1,138 @@
package example
import scala.collection.mutable.LinkedHashSet
import chisel3._
import chisel3.experimental._
import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper}
import freechips.rocketchip.subsystem.{RocketTilesKey}
import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.util.{GeneratorApp}
import freechips.rocketchip.tile.{XLen}
import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite}
import boom.system.{BoomTilesKey, BoomTestSuites}
object Generator extends GeneratorApp {
val rv64RegrTestNames = LinkedHashSet(
"rv64ud-v-fcvt",
"rv64ud-p-fdiv",
"rv64ud-v-fadd",
"rv64uf-v-fadd",
"rv64um-v-mul",
"rv64mi-p-breakpoint",
"rv64uc-v-rvc",
"rv64ud-v-structural",
"rv64si-p-wfi",
"rv64um-v-divw",
"rv64ua-v-lrsc",
"rv64ui-v-fence_i",
"rv64ud-v-fcvt_w",
"rv64uf-v-fmin",
"rv64ui-v-sb",
"rv64ua-v-amomax_d",
"rv64ud-v-move",
"rv64ud-v-fclass",
"rv64ua-v-amoand_d",
"rv64ua-v-amoxor_d",
"rv64si-p-sbreak",
"rv64ud-v-fmadd",
"rv64uf-v-ldst",
"rv64um-v-mulh",
"rv64si-p-dirty")
val rv32RegrTestNames = LinkedHashSet(
"rv32mi-p-ma_addr",
"rv32mi-p-csr",
"rv32ui-p-sh",
"rv32ui-p-lh",
"rv32uc-p-rvc",
"rv32mi-p-sbreak",
"rv32ui-p-sll")
override def addTestSuites {
import freechips.rocketchip.system.DefaultTestSuites._
val xlen = params(XLen)
// TODO: for now only generate tests for the first rocket/boom tile in the subsystem
// TODO: support heterogenous systems?
// rocket specific tests
params(RocketTilesKey).headOption.map { tileParams =>
val coreParams = tileParams.core
val vm = coreParams.useVM
val env = if (vm) List("p","v") else List("p")
coreParams.fpu foreach { case cfg =>
if (xlen == 32) {
TestGeneration.addSuites(env.map(rv32uf))
if (cfg.fLen >= 64)
TestGeneration.addSuites(env.map(rv32ud))
} else {
TestGeneration.addSuite(rv32udBenchmarks)
TestGeneration.addSuites(env.map(rv64uf))
if (cfg.fLen >= 64)
TestGeneration.addSuites(env.map(rv64ud))
}
}
if (coreParams.useAtomics) {
if (tileParams.dcache.flatMap(_.scratch).isEmpty)
TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
else
TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
}
if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
val (rvi, rvu) =
if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
else ((if (vm) rv32i else rv32pi), rv32u)
TestGeneration.addSuites(rvi.map(_("p")))
TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
TestGeneration.addSuite(benchmarks)
TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
}
// boom specific tests
params(BoomTilesKey).headOption.map { tileParams =>
val coreParams = tileParams.core
val vm = coreParams.useVM
val env = if (vm) List("p","v") else List("p")
coreParams.fpu foreach { case cfg =>
if (xlen == 32) {
TestGeneration.addSuites(env.map(rv32uf))
if (cfg.fLen >= 64) {
TestGeneration.addSuites(env.map(rv32ud))
}
} else if (cfg.fLen >= 64) {
TestGeneration.addSuites(env.map(rv64ud))
TestGeneration.addSuites(env.map(rv64uf))
TestGeneration.addSuite(rv32udBenchmarks)
}
}
if (coreParams.useAtomics) {
if (tileParams.dcache.flatMap(_.scratch).isEmpty) {
TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
} else {
TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
}
}
if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
// Include our BOOM-specific overrides.
val (rvi, rvu) =
if (xlen == 64) ((if (vm) BoomTestSuites.rv64i else BoomTestSuites.rv64pi), rv64u)
else ((if (vm) rv32i else rv32pi), rv32u)
TestGeneration.addSuites(rvi.map(_("p")))
TestGeneration.addSuites(rvu.map(_("p")))
TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
TestGeneration.addSuite(benchmarks)
rv64RegrTestNames -= "rv64mi-p-breakpoint" // TODO: breakpoints not implemented yet
TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
}
}
val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
generateFirrtl
generateAnno
generateTestSuiteMakefrags
generateArtefacts
}

1
src/main/scala/example/Simulator.scala
View File

@@ -102,6 +102,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
firrtl.FileUtils.makeDirectory("./bootrom/")
writeResource("/testchipip/bootrom/bootrom.rv64.img", "./bootrom/")
writeResource("/testchipip/bootrom/bootrom.rv32.img", "./bootrom/")
writeResource("/project-template/bootrom/bootrom.img", "./bootrom/")
}
def writeFiles(cfg: GenerateSimConfig): Unit = {

57
src/main/scala/example/TestHarness.scala
View File

@@ -7,14 +7,57 @@ import freechips.rocketchip.diplomacy.LazyModule
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.util.GeneratorApp
case object BuildTop extends Field[(Clock, Bool, Parameters) => ExampleTopModule[ExampleTop]]
// -------------------
// Rocket Test Harness
// -------------------
class TestHarness(implicit val p: Parameters) extends Module {
case object BuildRocketTop extends Field[(Clock, Bool, Parameters) => RocketTopModule[RocketTop]]
class RocketTestHarness(implicit val p: Parameters) extends Module {
val io = IO(new Bundle {
val success = Output(Bool())
})
val dut = p(BuildTop)(clock, reset.toBool, p)
// force Chisel to rename module
override def desiredName = "TestHarness"
val dut = p(BuildRocketTop)(clock, reset.toBool, p)
dut.debug := DontCare
dut.connectSimAXIMem()
dut.connectSimAXIMMIO()
dut.dontTouchPorts()
dut.tieOffInterrupts()
dut.l2_frontend_bus_axi4.foreach(axi => {
axi.tieoff()
experimental.DataMirror.directionOf(axi.ar.ready) match {
case core.ActualDirection.Input =>
axi.r.bits := DontCare
axi.b.bits := DontCare
case core.ActualDirection.Output =>
axi.aw.bits := DontCare
axi.ar.bits := DontCare
axi.w.bits := DontCare
}
})
io.success := dut.connectSimSerial()
}
// -----------------
// BOOM Test Harness
// -----------------
case object BuildBoomTop extends Field[(Clock, Bool, Parameters) => BoomTopModule[BoomTop]]
class BoomTestHarness(implicit val p: Parameters) extends Module {
val io = IO(new Bundle {
val success = Output(Bool())
})
// force Chisel to rename module
override def desiredName = "TestHarness"
val dut = p(BuildBoomTop)(clock, reset.toBool, p)
dut.debug := DontCare
dut.connectSimAXIMem()
dut.connectSimAXIMMIO()
@@ -34,11 +77,3 @@ class TestHarness(implicit val p: Parameters) extends Module {
})
io.success := dut.connectSimSerial()
}
object Generator extends GeneratorApp {
val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
generateFirrtl
generateAnno
generateTestSuiteMakefrags
generateArtefacts
}

112
src/main/scala/example/Top.scala
View File

@@ -7,47 +7,123 @@ import freechips.rocketchip.config.Parameters
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.util.DontTouch
import testchipip._
import sifive.blocks.devices.gpio._
class ExampleTop(implicit p: Parameters) extends ExampleRocketSystem //RocketSubsystem
// ------------------------
// Rocket Top Level Systems
// ------------------------
class RocketTop(implicit p: Parameters) extends ExampleRocketSystem
with CanHaveMasterAXI4MemPort
with HasPeripheryBootROM
// with HasSystemErrorSlave
// with HasSyncExtInterrupts
with HasNoDebug
with HasPeripherySerial {
override lazy val module = new ExampleTopModule(this)
override lazy val module = new RocketTopModule(this)
}
class ExampleTopModule[+L <: ExampleTop](l: L) extends ExampleRocketSystemModuleImp(l) // RocketSubsystemModuleImp(l)
class RocketTopModule[+L <: RocketTop](l: L) extends ExampleRocketSystemModuleImp(l)
with HasRTCModuleImp
with CanHaveMasterAXI4MemPortModuleImp
with HasPeripheryBootROMModuleImp
// with HasExtInterruptsModuleImp
with HasNoDebugModuleImp
with HasPeripherySerialModuleImp
with DontTouch
class ExampleTopWithPWMTL(implicit p: Parameters) extends ExampleTop
//---------------------------------------------------------------------------------------------------------
class RocketTopWithPWMTL(implicit p: Parameters) extends RocketTop
with HasPeripheryPWMTL {
override lazy val module = new ExampleTopWithPWMTLModule(this)
override lazy val module = new RocketTopWithPWMTLModule(this)
}
class ExampleTopWithPWMTLModule(l: ExampleTopWithPWMTL)
extends ExampleTopModule(l) with HasPeripheryPWMTLModuleImp
class RocketTopWithPWMTLModule(l: RocketTopWithPWMTL)
extends RocketTopModule(l) with HasPeripheryPWMTLModuleImp
class ExampleTopWithPWMAXI4(implicit p: Parameters) extends ExampleTop
//---------------------------------------------------------------------------------------------------------
class RocketTopWithPWMAXI4(implicit p: Parameters) extends RocketTop
with HasPeripheryPWMAXI4 {
override lazy val module = new ExampleTopWithPWMAXI4Module(this)
override lazy val module = new RocketTopWithPWMAXI4Module(this)
}
class ExampleTopWithPWMAXI4Module(l: ExampleTopWithPWMAXI4)
extends ExampleTopModule(l) with HasPeripheryPWMAXI4ModuleImp
class RocketTopWithPWMAXI4Module(l: RocketTopWithPWMAXI4)
extends RocketTopModule(l) with HasPeripheryPWMAXI4ModuleImp
class ExampleTopWithBlockDevice(implicit p: Parameters) extends ExampleTop
//---------------------------------------------------------------------------------------------------------
class RocketTopWithBlockDevice(implicit p: Parameters) extends RocketTop
with HasPeripheryBlockDevice {
override lazy val module = new ExampleTopWithBlockDeviceModule(this)
override lazy val module = new RocketTopWithBlockDeviceModule(this)
}
class ExampleTopWithBlockDeviceModule(l: ExampleTopWithBlockDevice)
extends ExampleTopModule(l)
class RocketTopWithBlockDeviceModule(l: RocketTopWithBlockDevice)
extends RocketTopModule(l)
with HasPeripheryBlockDeviceModuleImp
//---------------------------------------------------------------------------------------------------------
class RocketTopWithGPIO(implicit p: Parameters) extends RocketTop
with HasPeripheryGPIO {
override lazy val module = new RocketTopWithGPIOModule(this)
}
class RocketTopWithGPIOModule(l: RocketTopWithGPIO)
extends RocketTopModule(l)
with HasPeripheryGPIOModuleImp
// ----------------------
// BOOM Top Level Systems
// ----------------------
class BoomTop(implicit p: Parameters) extends boom.system.ExampleBoomSystem
with HasNoDebug
with HasPeripherySerial {
override lazy val module = new BoomTopModule(this)
}
class BoomTopModule[+L <: BoomTop](l: L) extends boom.system.ExampleBoomSystemModule(l)
with HasRTCModuleImp
with HasNoDebugModuleImp
with HasPeripherySerialModuleImp
with DontTouch
//---------------------------------------------------------------------------------------------------------
class BoomTopWithPWMTL(implicit p: Parameters) extends BoomTop
with HasPeripheryPWMTL {
override lazy val module = new BoomTopWithPWMTLModule(this)
}
class BoomTopWithPWMTLModule(l: BoomTopWithPWMTL) extends BoomTopModule(l)
with HasPeripheryPWMTLModuleImp
//---------------------------------------------------------------------------------------------------------
class BoomTopWithPWMAXI4(implicit p: Parameters) extends BoomTop
with HasPeripheryPWMAXI4 {
override lazy val module = new BoomTopWithPWMAXI4Module(this)
}
class BoomTopWithPWMAXI4Module(l: BoomTopWithPWMAXI4) extends BoomTopModule(l)
with HasPeripheryPWMAXI4ModuleImp
//---------------------------------------------------------------------------------------------------------
class BoomTopWithBlockDevice(implicit p: Parameters) extends BoomTop
with HasPeripheryBlockDevice {
override lazy val module = new BoomTopWithBlockDeviceModule(this)
}
class BoomTopWithBlockDeviceModule(l: BoomTopWithBlockDevice) extends BoomTopModule(l)
with HasPeripheryBlockDeviceModuleImp
//---------------------------------------------------------------------------------------------------------
class BoomTopWithGPIO(implicit p: Parameters) extends BoomTop
with HasPeripheryGPIO {
override lazy val module = new BoomTopWithGPIOModule(this)
}
class BoomTopWithGPIOModule(l: BoomTopWithGPIO)
extends BoomTopModule(l)
with HasPeripheryGPIOModuleImp

40
variables.mk
View File

@@ -3,10 +3,11 @@
#########################################################################################
#########################################################################################
# default variables to invoke the generator
# default variables to invoke the generator for a example Rocket system
# descriptions:
# PROJECT = the scala package to find the MODEL/Generator in
# MODEL = the top level module of the project (normally the harness)
# MODEL = the top level module of the project in Chisel (normally the harness)
# VLOG_MODEL = the top level module of the project in Firrtl/Verilog (normally the harness)
# CONFIG = the configuration class to give the parameters for the project
# CFG_PROJECT = the scala package to find the CONFIG class
# SBT_PROJECT = the SBT project that you should find the Generator class in
@@ -17,19 +18,39 @@
# SUB_PROJECT = use the specific subproject default variables
#########################################################################################
PROJECT ?= example
MODEL ?= TestHarness
CONFIG ?= DefaultExampleConfig
MODEL ?= RocketTestHarness
VLOG_MODEL ?= TestHarness
CONFIG ?= DefaultRocketConfig
CFG_PROJECT ?= $(PROJECT)
SBT_PROJECT ?= $(PROJECT)
TB ?= TestDriver
TOP ?= ExampleTop
TOP ?= RocketTop
# make it so that you only change 1 param to change most or all of them!
SUB_PROJECT ?= example
ifeq ($(SUB_PROJECT),boom) # make it so that you only change 1 param to change them all!
SBT_PROJECT=boom
ifeq ($(SUB_PROJECT),boomexample)
# for a BOOM based system (provides all necessary params)
MODEL=BoomTestHarness
CONFIG=DefaultBoomConfig
TOP=BoomTop
endif
ifeq ($(SUB_PROJECT),boom)
# for BOOM developers (only need to provide a CONFIG)
PROJECT=boom.system
MODEL=TestHarness
CFG_PROJECT=boom.system
SBT_PROJECT=boom
TOP=ExampleBoomSystem
endif
ifeq ($(SUB_PROJECT),rocketchip)
# for Rocket-chip developers
PROJECT=freechips.rocketchip.system
MODEL=TestHarness
CONFIG=DefaultConfig
CFG_PROJECT=freechips.rocketchip.system
SBT_PROJECT=rebarrocketchip
TOP=ExampleRocketSystem
endif
#########################################################################################
# path to rocket-chip and testchipip
@@ -43,6 +64,11 @@ REBAR_FIRRTL_DIR = $(base_dir)/tools/firrtl
#########################################################################################
long_name = $(PROJECT).$(MODEL).$(CONFIG)
# if building from rocketchip, override the long_name to match what they expect
ifeq ($(SBT_PROJECT),rebarrocketchip)
long_name=$(PROJECT).$(CONFIG)
endif
FIRRTL_FILE ?= $(build_dir)/$(long_name).fir
ANNO_FILE ?= $(build_dir)/$(long_name).anno.json
VERILOG_FILE ?= $(build_dir)/$(long_name).top.v