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alonamid
2019-09-25 18:07:44 -07:00
parent 90bafa6409
commit a33b716504
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docs/Generators/SiFive-Generators.rst
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@@ -11,7 +11,7 @@ Last-Level Cache Generator
To learn more about configuring this L2 cache, please refer to the :ref:`memory-hierarchy` section.
Perihperal Devices
Peripheral Devices
-------------------
``sifive-blocks`` includes multiple peripheral device generators, such as UART, SPI, PWM, JTAG, GPIO and more.