From a33b716504b0b86caf571d4ab6ae64429683052c Mon Sep 17 00:00:00 2001
From: alonamid <alonamid@eecs.berkeley.edu>
Date: Wed, 25 Sep 2019 18:07:44 -0700
Subject: [PATCH] typo

---
 docs/Generators/SiFive-Generators.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/Generators/SiFive-Generators.rst b/docs/Generators/SiFive-Generators.rst
index 17776b6e..8f2202b0 100644
--- a/docs/Generators/SiFive-Generators.rst
+++ b/docs/Generators/SiFive-Generators.rst
@@ -11,7 +11,7 @@ Last-Level Cache Generator
 To learn more about configuring this L2 cache, please refer to the :ref:`memory-hierarchy` section.
 
 
-Perihperal Devices
+Peripheral Devices
 -------------------
 ``sifive-blocks`` includes multiple peripheral device generators, such as UART, SPI, PWM, JTAG, GPIO and more.