Merge branch 'main' of https://github.com/ucb-bar/chipyard into ucb-bar-main

fpga/Makefile

@@ -87,6 +87,8 @@ ifeq ($(SUB_PROJECT),arty100t)
 	FPGA_BRAND        ?= xilinx
 endif
 
+export USE_CHISEL6=1
+
 include $(base_dir)/variables.mk
 
 # default variables to build the arty example

fpga/src/main/scala/arty/Configs.scala

@@ -5,7 +5,6 @@ import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.devices.tilelink._
-import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase}
 import freechips.rocketchip.system._
 import freechips.rocketchip.tile._
 
@@ -25,7 +24,6 @@ class WithArtyTweaks extends Config(
 
   new chipyard.harness.WithHarnessBinderClockFreqMHz(32) ++
   new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
-  new chipyard.config.WithDTSTimebase(32000) ++
   new chipyard.config.WithSystemBusFrequency(32) ++
   new chipyard.config.WithFrontBusFrequency(32) ++
   new chipyard.config.WithControlBusFrequency(32) ++

fpga/src/main/scala/arty/IOBinders.scala

@@ -1,7 +1,6 @@
 package chipyard.fpga.arty
 
 import chisel3._
-import chisel3.experimental.{IO}
 
 import freechips.rocketchip.devices.debug.{HasPeripheryDebug}
 

fpga/src/main/scala/vc707/TestHarness.scala

@@ -1,6 +1,5 @@
 package chipyard.fpga.vc707
 import chisel3._
-import chisel3.experimental.{IO}
 
 import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource}
 import org.chipsalliance.cde.config.{Parameters}

fpga/src/main/scala/vcu118/TestHarness.scala

@@ -1,7 +1,6 @@
 package chipyard.fpga.vcu118
 
 import chisel3._
-import chisel3.experimental.{IO}
 
 import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource}
 import org.chipsalliance.cde.config.{Parameters}