diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh index 8043c12f..570a6ee5 100755 --- a/.github/scripts/check-commit.sh +++ b/.github/scripts/check-commit.sh @@ -45,21 +45,11 @@ search () { done } -submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy") +submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy") dir="generators" branches=("master" "main" "dev") search -submodules=("esp-tools-feedstock") -dir="toolchains/esp-tools" -branches=("main") -search - -submodules=("riscv-isa-sim" "riscv-pk" "riscv-tests") -dir="toolchains/esp-tools" -branches=("master") -search - submodules=("riscv-tools-feedstock") dir="toolchains/riscv-tools" branches=("main") @@ -92,7 +82,7 @@ dir="software" branches=("master" "dev") search -submodules=("DRAMSim2" "axe" "barstools" "dsptools" "rocket-dsp-utils" "torture" "fixedpoint" "cde") +submodules=("DRAMSim2" "axe" "dsptools" "dsptools-chisel3" "rocket-dsp-utils" "torture" "fixedpoint" "fixedpoint-chisel3" "cde" "midas-targetutils") dir="tools" branches=("master" "dev" "main") search diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index 4eb7546f..dff549b9 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -30,7 +30,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache declare -A grouping grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boomv3 chipyard-boomv4 chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle" grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboomv3 chipyard-dmiboomv4 chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric chipyard-llcchiplet" -grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb" +grouping["group-accels"]="chipyard-mempress chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb" grouping["group-constellation"]="chipyard-constellation" grouping["group-gpu"]="chipyard-radiance chipyard-radiance-fuzzer chipyard-coalescer coalescer" grouping["group-tracegen"]="tracegen tracegen-boomv3 tracegen-boomv4" @@ -41,7 +41,6 @@ grouping["group-fpga"]="arty35t arty100t nexysvideo vc707 vcu118" declare -A mapping mapping["chipyard-rocket"]=" CONFIG=QuadChannelRocketConfig" mapping["chipyard-dmirocket"]=" CONFIG=dmiRocketConfig" -mapping["chipyard-sha3"]=" CONFIG=Sha3RocketConfig" mapping["chipyard-mempress"]=" CONFIG=MempressRocketConfig" mapping["chipyard-prefetchers"]=" CONFIG=PrefetchingRocketConfig" mapping["chipyard-digitaltop"]=" TOP=DigitalTop" @@ -53,7 +52,6 @@ mapping["chipyard-dmiboomv3"]=" CONFIG=dmiMediumBoomV3CosimConfig" mapping["chipyard-boomv4"]=" CONFIG=MediumBoomV4CosimConfig" mapping["chipyard-dmiboomv4"]=" CONFIG=dmiMediumBoomV4CosimConfig" mapping["chipyard-spike"]=" CONFIG=SpikeConfig EXTRA_SIM_FLAGS='+spike-ipc=10'" -mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig" mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig" mapping["chipyard-cva6"]=" CONFIG=CVA6Config" mapping["chipyard-ibex"]=" CONFIG=IbexConfig" @@ -81,8 +79,8 @@ mapping["chipyard-coalescer"]=" CONFIG=MemtraceCoreConfig" mapping["constellation"]=" SUB_PROJECT=constellation" mapping["coalescer"]=" SUB_PROJECT=coalescer" -mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests" -mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests" +mapping["firesim"]="TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig" +mapping["fireboom"]="TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimLargeBoomConfig" mapping["icenet"]="SUB_PROJECT=icenet" mapping["testchipip"]="SUB_PROJECT=testchipip" mapping["rocketchip-amba"]="SUB_PROJECT=rocketchip CONFIG=AMBAUnitTestConfig" diff --git a/.github/scripts/remote-do-rtl-build.sh b/.github/scripts/remote-do-rtl-build.sh index 9cbc8531..7a988840 100755 --- a/.github/scripts/remote-do-rtl-build.sh +++ b/.github/scripts/remote-do-rtl-build.sh @@ -53,5 +53,5 @@ do export COURSIER_CACHE=$REMOTE_COURSIER_CACHE export JVM_MEMORY=10G export JAVA_TMP_DIR=$REMOTE_JAVA_TMP_DIR - make -j$REMOTE_MAKE_NPROC -C $REMOTE_MAKE_DIR FIRRTL_LOGLEVEL=info ${mapping[$key]} + make -j$REMOTE_MAKE_NPROC -C $REMOTE_MAKE_DIR ${mapping[$key]} done diff --git a/.github/scripts/remote-run-firesim-scala-tests.sh b/.github/scripts/remote-run-firesim-scala-tests.sh index 5d9a970d..69f28c52 100755 --- a/.github/scripts/remote-run-firesim-scala-tests.sh +++ b/.github/scripts/remote-run-firesim-scala-tests.sh @@ -13,10 +13,8 @@ source $SCRIPT_DIR/defaults.sh cd $REMOTE_CHIPYARD_DIR ./scripts/init-submodules-no-riscv-tools.sh -# Run Firesim Scala Tests +# Test firesim compile and metasim export FIRESIM_ENV_SOURCED=1 -export COURSIER_CACHE=$REMOTE_COURSIER_CACHE -export JVM_MEMORY=10G -export JAVA_TMP_DIR=$REMOTE_JAVA_TMP_DIR -export TEST_DISABLE_VIVADO=1 -make -C $REMOTE_FIRESIM_DIR TARGET_SBT_PROJECT="{file:$REMOTE_CHIPYARD_DIR}firechip" testOnly ${mapping[$1]} +cd $REMOTE_FIRESIM_DIR +make TARGET_PROJECT=firesim EMUL=verilator ${mapping[$1]} run-verilator SIM_BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple + diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh index 2a4ad42f..ce4de3e5 100755 --- a/.github/scripts/run-tests.sh +++ b/.github/scripts/run-tests.sh @@ -77,9 +77,6 @@ case $1 in rocketchip) run_bmark ;; - chipyard-hwacha) - make run-rv64uv-p-asm-tests -j$CI_MAKE_NPROC -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ $MAPPING_FLAGS - ;; chipyard-gemmini) GEMMINI_SOFTWARE_DIR=$LOCAL_SIM_DIR/../../generators/gemmini/software/gemmini-rocc-tests rm -rf $GEMMINI_SOFTWARE_DIR/riscv-tests @@ -88,10 +85,6 @@ case $1 in run_binary BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal run_binary BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal ;; - chipyard-sha3) - (cd $LOCAL_CHIPYARD_DIR/generators/sha3/software && ./build.sh) - run_binary BINARY=$LOCAL_CHIPYARD_DIR/generators/sha3/software/tests/bare/sha3-rocc.riscv - ;; chipyard-mempress) (cd $LOCAL_CHIPYARD_DIR/generators/mempress/software/src && make) run_binary BINARY=$LOCAL_CHIPYARD_DIR/generators/mempress/software/src/mempress-rocc.riscv diff --git a/.github/workflows/chipyard-full-flow.yml b/.github/workflows/chipyard-full-flow.yml index 3e3f89f1..56e753e0 100644 --- a/.github/workflows/chipyard-full-flow.yml +++ b/.github/workflows/chipyard-full-flow.yml @@ -61,8 +61,8 @@ jobs: - '**/.gitignore' - '.github/ISSUE_TEMPLATE/**' - setup-repo: - name: setup-repo + full-flow: + name: full-flow needs: [change-filters, cancel-prior-workflows] if: needs.change-filters.outputs.needs-rtl == 'true' runs-on: as4 @@ -84,12 +84,6 @@ jobs: mkdir ${{ env.JAVA_TMP_DIR }} export MAKEFLAGS="-j32" ./build-setup.sh -v - - run-cfg-finder: - name: run-cfg-finder - needs: [setup-repo] - runs-on: as4 - steps: - name: Run config finder run: | cd ${{ env.REMOTE_WORK_DIR }} @@ -97,12 +91,6 @@ jobs: source env.sh cd sims/verilator make find-config-fragments - - run-tutorial: - name: run-tutorial - needs: [setup-repo] - runs-on: as4 - steps: - name: Run smoke test run: | cd ${{ env.REMOTE_WORK_DIR }} @@ -169,7 +157,7 @@ jobs: cleanup: name: cleanup - needs: [run-tutorial] + needs: [full-flow] runs-on: as4 if: ${{ always() }} steps: diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index dd91f4de..0b644888 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -119,29 +119,6 @@ jobs: conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools .github/scripts/check-commit.sh - tutorial-setup-check: - name: tutorial-setup-check - needs: [setup-complete] - if: needs.change-filters.outputs.needs-rtl == 'true' - runs-on: as4 - steps: - - name: Delete old checkout - run: | - ls -alh . - rm -rf ${{ github.workspace }}/* || true - rm -rf ${{ github.workspace }}/.* || true - ls -alh . - - name: Checkout - uses: actions/checkout@v3 - - name: Git workaround - uses: ./.github/actions/git-workaround - - name: Create conda env - uses: ./.github/actions/create-conda-env - - name: Check that the tutorial-setup patches apply - run: | - conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools - scripts/tutorial-setup.sh - documentation-check: name: documentation-check needs: [setup-complete] @@ -800,29 +777,6 @@ jobs: group-key: "group-peripherals" project-key: "chipyard-llcchiplet" - chipyard-sha3-run-tests: - name: chipyard-sha3-run-tests - needs: prepare-chipyard-accels - runs-on: as4 - steps: - - name: Delete old checkout - run: | - ls -alh . - rm -rf ${{ github.workspace }}/* || true - rm -rf ${{ github.workspace }}/.* || true - ls -alh . - - name: Checkout - uses: actions/checkout@v3 - - name: Git workaround - uses: ./.github/actions/git-workaround - - name: Create conda env - uses: ./.github/actions/create-conda-env - - name: Run tests - uses: ./.github/actions/run-tests - with: - group-key: "group-accels" - project-key: "chipyard-sha3" - chipyard-gemmini-run-tests: name: chipyard-gemmini-run-tests needs: prepare-chipyard-accels @@ -1172,7 +1126,6 @@ jobs: all_tests_passed: name: "all tests passed" needs: [commit-on-master-check, - tutorial-setup-check, documentation-check, chipyard-rocket-run-tests, chipyard-hetero-run-tests, @@ -1190,7 +1143,6 @@ jobs: chipyard-tethered-run-tests, chipyard-symmetric-run-tests, chipyard-llcchiplet-run-tests, - chipyard-sha3-run-tests, chipyard-gemmini-run-tests, chipyard-manymmioaccels-run-tests, # chipyard-nvdla-run-tests, chipyard-prefetchers-run-tests, diff --git a/.gitmodules b/.gitmodules index 56292b05..709b4865 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,137 +1,125 @@ -[submodule "generators/rocket-chip"] - path = generators/rocket-chip - url = https://github.com/hansungk/rocket-chip.git -[submodule "generators/testchipip"] - path = generators/testchipip - url = https://github.com/richardyrh/testchipip.git -[submodule "tools/barstools"] - path = tools/barstools - url = https://github.com/ucb-bar/barstools.git -[submodule "tools/torture"] - path = tools/torture - url = https://github.com/ucb-bar/riscv-torture.git +[submodule "fpga/fpga-shells"] + path = fpga/fpga-shells + url = https://github.com/chipsalliance/rocket-chip-fpga-shells.git +[submodule "generators/bar-fetchers"] + path = generators/bar-fetchers + url = https://github.com/ucb-bar/bar-fetchers.git [submodule "generators/boom"] path = generators/boom url = https://github.com/riscv-boom/riscv-boom.git -[submodule "generators/hwacha"] - path = generators/hwacha - url = https://github.com/ucb-bar/hwacha.git -[submodule "sims/firesim"] - path = sims/firesim - url = https://github.com/firesim/firesim.git -[submodule "generators/icenet"] - path = generators/icenet - url = https://github.com/firesim/icenet.git -[submodule "tools/circt"] - path = tools/circt - url = https://github.com/llvm/circt.git -[submodule "tools/dsptools"] - path = tools/dsptools - url = https://github.com/ucb-bar/dsptools.git -[submodule "generators/sha3"] - path = generators/sha3 - url = https://github.com/ucb-bar/sha3.git -[submodule "vlsi/hammer-mentor-plugins"] - path = vlsi/hammer-mentor-plugins - url = https://github.com/ucb-bar/hammer-mentor-plugins.git -[submodule "tools/axe"] - path = tools/axe - url = https://github.com/CTSRD-CHERI/axe.git -[submodule "software/spec2017"] - path = software/spec2017 - url = https://github.com/ucb-bar/spec2017-workload.git -[submodule "software/coremark"] - path = software/coremark - url = https://github.com/ucb-bar/coremark-workload.git -[submodule "generators/gemmini"] - path = generators/gemmini - url = https://github.com/ucb-bar/gemmini -[submodule "software/firemarshal"] - path = software/firemarshal - url = https://github.com/firesim/FireMarshal.git +[submodule "generators/caliptra-aes-acc"] + path = generators/caliptra-aes-acc + url = https://github.com/ucb-bar/caliptra-aes-acc.git +[submodule "generators/constellation"] + path = generators/constellation + url = https://github.com/ucb-bar/constellation.git [submodule "generators/cva6"] path = generators/cva6 url = https://github.com/ucb-bar/cva6-wrapper.git [submodule "generators/diplomacy"] path = generators/diplomacy url = https://github.com/chipsalliance/diplomacy.git -[submodule "tools/DRAMSim2"] - path = tools/DRAMSim2 - url = https://github.com/firesim/DRAMSim2.git -[submodule "generators/nvdla"] - path = generators/nvdla - url = https://github.com/ucb-bar/nvdla-wrapper.git -[submodule "software/nvdla-workload"] - path = software/nvdla-workload - url = https://github.com/ucb-bar/nvdla-workload.git -[submodule "software/baremetal-ide"] - path = software/baremetal-ide - url = https://github.com/ucb-bar/Baremetal-IDE.git -[submodule "generators/riscv-sodor"] - path = generators/riscv-sodor - url = https://github.com/ucb-bar/riscv-sodor.git -[submodule "fpga/fpga-shells"] - path = fpga/fpga-shells - url = https://github.com/chipsalliance/rocket-chip-fpga-shells.git -[submodule "tools/rocket-dsp-utils"] - path = tools/rocket-dsp-utils - url = https://github.com/ucb-bar/rocket-dsp-utils -[submodule "generators/ibex"] - path = generators/ibex - url = https://github.com/ucb-bar/ibex-wrapper [submodule "generators/fft-generator"] path = generators/fft-generator url = https://github.com/ucb-bar/FFTGenerator.git -[submodule "toolchains/riscv-tools/riscv-tests"] - path = toolchains/riscv-tools/riscv-tests - url = https://github.com/riscv-software-src/riscv-tests.git -[submodule "toolchains/riscv-tools/riscv-pk"] - path = toolchains/riscv-tools/riscv-pk - url = https://github.com/riscv-software-src/riscv-pk.git -[submodule "toolchains/riscv-tools/riscv-openocd"] - path = toolchains/riscv-tools/riscv-openocd - url = https://github.com/riscv/riscv-openocd.git -[submodule "toolchains/riscv-tools/riscv-isa-sim"] - path = toolchains/riscv-tools/riscv-isa-sim - url = https://github.com/richardyrh/riscv-isa-sim -[submodule "toolchains/riscv-tools/riscv-tools-feedstock"] - path = toolchains/riscv-tools/riscv-tools-feedstock - url = https://github.com/ucb-bar/riscv-tools-feedstock.git -[submodule "toolchains/esp-tools/esp-tools-feedstock"] - path = toolchains/esp-tools/esp-tools-feedstock - url = https://github.com/ucb-bar/esp-tools-feedstock.git -[submodule "toolchains/esp-tools/riscv-isa-sim"] - path = toolchains/esp-tools/riscv-isa-sim - url = https://github.com/ucb-bar/esp-isa-sim.git -[submodule "toolchains/esp-tools/riscv-pk"] - path = toolchains/esp-tools/riscv-pk - url = https://github.com/riscv-software-src/riscv-pk.git -[submodule "toolchains/esp-tools/riscv-tests"] - path = toolchains/esp-tools/riscv-tests - url = https://github.com/ucb-bar/esp-tests.git -[submodule "toolchains/libgloss"] - path = toolchains/libgloss - url = https://github.com/ucb-bar/libgloss-htif.git -[submodule "generators/constellation"] - path = generators/constellation - url = https://github.com/ucb-bar/constellation.git +[submodule "generators/gemmini"] + path = generators/gemmini + url = https://github.com/ucb-bar/gemmini.git +[submodule "generators/hardfloat"] + path = generators/hardfloat + url = https://github.com/ucb-bar/berkeley-hardfloat.git +[submodule "generators/ibex"] + path = generators/ibex + url = https://github.com/ucb-bar/ibex-wrapper.git +[submodule "generators/icenet"] + path = generators/icenet + url = https://github.com/firesim/icenet.git [submodule "generators/mempress"] path = generators/mempress url = https://github.com/ucb-bar/mempress.git -[submodule "tools/cde"] - path = tools/cde - url = https://github.com/chipsalliance/cde.git +[submodule "generators/nvdla"] + path = generators/nvdla + url = https://github.com/ucb-bar/nvdla-wrapper.git +[submodule "generators/riscv-sodor"] + path = generators/riscv-sodor + url = https://github.com/ucb-bar/riscv-sodor.git +[submodule "generators/rocc-acc-utils"] + path = generators/rocc-acc-utils + url = https://github.com/ucb-bar/rocc-acc-utils.git +[submodule "generators/rocket-chip"] + path = generators/rocket-chip + url = https://github.com/hansungk/rocket-chip.git +[submodule "generators/rocket-chip-blocks"] + path = generators/rocket-chip-blocks + url = https://github.com/chipsalliance/rocket-chip-blocks.git +[submodule "generators/rocket-chip-inclusive-cache"] + path = generators/rocket-chip-inclusive-cache + url = https://github.com/chipsalliance/rocket-chip-inclusive-cache.git +[submodule "generators/shuttle"] + path = generators/shuttle + url = https://github.com/ucb-bar/shuttle.git +[submodule "generators/testchipip"] + path = generators/testchipip + url = https://github.com/richardyrh/testchipip.git +[submodule "sims/firesim"] + path = sims/firesim + url = https://github.com/firesim/firesim.git +[submodule "software/baremetal-ide"] + path = software/baremetal-ide + url = https://github.com/ucb-bar/Baremetal-IDE.git +[submodule "software/coremark"] + path = software/coremark + url = https://github.com/ucb-bar/coremark-workload.git [submodule "software/embench/embench-iot"] path = software/embench/embench-iot url = https://github.com/embench/embench-iot.git -[submodule "shuttle"] - path = generators/shuttle - url = https://github.com/ucb-bar/shuttle.git -[submodule "generators/bar-fetchers"] - path = generators/bar-fetchers - url = https://github.com/ucb-bar/bar-fetchers.git -[submodule "tools/fixedpoint"] - path = tools/fixedpoint +[submodule "software/firemarshal"] + path = software/firemarshal + url = https://github.com/firesim/FireMarshal.git +[submodule "software/nvdla-workload"] + path = software/nvdla-workload + url = https://github.com/ucb-bar/nvdla-workload.git +[submodule "software/spec2017"] + path = software/spec2017 + url = https://github.com/ucb-bar/spec2017-workload.git +[submodule "toolchains/libgloss"] + path = toolchains/libgloss + url = https://github.com/ucb-bar/libgloss-htif.git +[submodule "toolchains/riscv-tools/riscv-isa-sim"] + path = toolchains/riscv-tools/riscv-isa-sim + url = https://github.com/richardyrh/riscv-isa-sim +[submodule "toolchains/riscv-tools/riscv-openocd"] + path = toolchains/riscv-tools/riscv-openocd + url = https://github.com/riscv/riscv-openocd.git +[submodule "toolchains/riscv-tools/riscv-pk"] + path = toolchains/riscv-tools/riscv-pk + url = https://github.com/riscv-software-src/riscv-pk.git +[submodule "toolchains/riscv-tools/riscv-spike-devices"] + path = toolchains/riscv-tools/riscv-spike-devices + url = https://github.com/ucb-bar/spike-devices.git +[submodule "toolchains/riscv-tools/riscv-tests"] + path = toolchains/riscv-tools/riscv-tests + url = https://github.com/riscv-software-src/riscv-tests.git +[submodule "toolchains/riscv-tools/riscv-tools-feedstock"] + path = toolchains/riscv-tools/riscv-tools-feedstock + url = https://github.com/ucb-bar/riscv-tools-feedstock.git +[submodule "tools/DRAMSim2"] + path = tools/DRAMSim2 + url = https://github.com/firesim/DRAMSim2.git +[submodule "tools/axe"] + path = tools/axe + url = https://github.com/CTSRD-CHERI/axe.git +[submodule "tools/cde"] + path = tools/cde + url = https://github.com/chipsalliance/cde.git +[submodule "tools/circt"] + path = tools/circt + url = https://github.com/llvm/circt.git +[submodule "tools/dsptools-fixedpoint"] + path = tools/dsptools-chisel3 + url = https://github.com/ucb-bar/dsptools.git +[submodule "tools/fixedpoint-chisel3"] + path = tools/fixedpoint-chisel3 url = https://github.com/ucb-bar/fixedpoint.git [submodule "generators/hardfloat"] path = generators/hardfloat @@ -144,16 +132,26 @@ url = https://github.com/ucb-bar/rocc-acc-utils [submodule "tools/install-circt"] path = tools/install-circt - url = https://github.com/circt/install-circt/ -[submodule "toolchains/riscv-tools/riscv-spike-devices"] - path = toolchains/riscv-tools/riscv-spike-devices - url = https://github.com/ucb-bar/spike-devices.git -[submodule "generators/rocket-chip-blocks"] - path = generators/rocket-chip-blocks - url = https://github.com/chipsalliance/rocket-chip-blocks.git -[submodule "generators/rocket-chip-inclusive-cache"] - path = generators/rocket-chip-inclusive-cache - url = https://github.com/chipsalliance/rocket-chip-inclusive-cache.git + url = https://github.com/circt/install-circt.git +[submodule "tools/rocket-dsp-utils"] + path = tools/rocket-dsp-utils + url = https://github.com/ucb-bar/rocket-dsp-utils.git +[submodule "tools/torture"] + path = tools/torture + url = https://github.com/ucb-bar/riscv-torture.git +[submodule "vlsi/hammer-mentor-plugins"] + path = vlsi/hammer-mentor-plugins + url = https://github.com/ucb-bar/hammer-mentor-plugins.git +[submodule "tools/dsptools"] + path = tools/dsptools + url = https://github.com/ucb-bar/dsptools.git +[submodule "tools/fixedpoint"] + path = tools/fixedpoint + url = https://github.com/ucb-bar/fixedpoint.git +[submodule "tools/midas-targetutils"] + path = tools/midas-targetutils + url = https://github.com/firesim/midas-targetutils.git + [submodule "generators/radiance"] path = generators/radiance url = https://github.com/ucb-bar/radiance.git diff --git a/README.md b/README.md index 8bb2e3e3..2a275e7c 100644 --- a/README.md +++ b/README.md @@ -16,7 +16,7 @@ To get started using Chipyard, see the stable documentation on the Chipyard docu Chipyard is an open source framework for agile development of Chisel-based systems-on-chip. It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators. -Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [CVA6 (Ariane)][cva6]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC. +Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [CVA6 (Ariane)][cva6]), accelerators ([Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC. Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation ([FireSim][firesim]), automated VLSI flows ([Hammer][hammer]), and software workload generation for bare-metal and Linux-based systems ([FireMarshal][firemarshal]). Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley]. @@ -65,7 +65,6 @@ These additional publications cover many of the internal components used in Chip * **BOOM**: C. Celio, et al., *Hot Chips 30*. [PDF](https://old.hotchips.org/hc30/1conf/1.03_Berkeley_BROOM_HC30.Berkeley.Celio.v02.pdf). * **SonicBOOM (BOOMv3)**: J. Zhao, et al., *CARRV'20*. [PDF](https://carrv.github.io/2020/papers/CARRV2020_paper_15_Zhao.pdf). * **COBRA (BOOM Branch Prediction)**: J. Zhao, et al., *ISPASS'21*. [PDF](https://ieeexplore.ieee.org/document/9408173). - * **Hwacha**: Y. Lee, et al., *ESSCIRC'14*. [PDF](http://hwacha.org/papers/riscv-esscirc2014.pdf). * **Gemmini**: H. Genc, et al., *DAC'21*. [PDF](https://arxiv.org/pdf/1911.09925). * **Sims** * **FireSim**: S. Karandikar, et al., *ISCA'18*. [PDF](https://sagark.org/assets/pubs/firesim-isca2018.pdf). @@ -87,7 +86,6 @@ These additional publications cover many of the internal components used in Chip This work is supported by the NSF CCRI ENS Chipyard Award #2016662. -[hwacha]:https://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-262.pdf [hammer]:https://github.com/ucb-bar/hammer [firesim]:https://fires.im [ucb-bar]: http://bar.eecs.berkeley.edu diff --git a/build.sbt b/build.sbt index ea1637cd..31ea7b0f 100644 --- a/build.sbt +++ b/build.sbt @@ -1,5 +1,9 @@ import Tests._ +val chisel6 = sys.env.get("USE_CHISEL6").isDefined +val chiselTestVersion = if (chisel6) "6.0.0" else "0.6.0" +val scalaVersionFromChisel = if (chisel6) "2.13.12" else "2.13.10" + // This gives us a nicer handle to the root project instead of using the // implicit one lazy val chipyardRoot = Project("chipyardRoot", file(".")) @@ -11,7 +15,7 @@ val chiselFirrtlMergeStrategy = CustomMergeStrategy.rename { dep => case p: Project => p.name case l: Library => l.moduleCoord.name } - if (Seq("firrtl", "chisel3").contains(nm.split("_")(0))) { // split by _ to avoid checking on major/minor version + if (Seq("firrtl", "chisel3", "chisel").contains(nm.split("_")(0))) { // split by _ to avoid checking on major/minor version dep.target } else { "renamed/" + dep.target @@ -21,11 +25,13 @@ val chiselFirrtlMergeStrategy = CustomMergeStrategy.rename { dep => lazy val commonSettings = Seq( organization := "edu.berkeley.cs", version := "1.6", - scalaVersion := "2.13.10", + scalaVersion := scalaVersionFromChisel, assembly / test := {}, assembly / assemblyMergeStrategy := { case PathList("chisel3", "stage", xs @ _*) => chiselFirrtlMergeStrategy + case PathList("chisel", "stage", xs @ _*) => chiselFirrtlMergeStrategy case PathList("firrtl", "stage", xs @ _*) => chiselFirrtlMergeStrategy + case PathList("META-INF", _*) => MergeStrategy.discard // should be safe in JDK11: https://stackoverflow.com/questions/54834125/sbt-assembly-deduplicate-module-info-class case x if x.endsWith("module-info.class") => MergeStrategy.discard case x => @@ -35,6 +41,7 @@ lazy val commonSettings = Seq( scalacOptions ++= Seq( "-deprecation", "-unchecked", + "-Ytasty-reader", "-Ymacro-annotations"), // fix hierarchy API unmanagedBase := (chipyardRoot / unmanagedBase).value, allDependencies := { @@ -44,6 +51,9 @@ lazy val commonSettings = Seq( dropDeps.contains((dep.organization, dep.name)) } }, + libraryDependencies += "com.lihaoyi" %% "sourcecode" % "0.3.1", + libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value, + exportJars := true, resolvers ++= Seq( Resolver.sonatypeRepo("snapshots"), @@ -82,13 +92,22 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => new Group(test.name, Seq(test), SubProcess(options)) } toSeq -val chiselVersion = "3.6.0" -lazy val chiselSettings = Seq( - libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % chiselVersion, - "org.apache.commons" % "commons-lang3" % "3.12.0", - "org.apache.commons" % "commons-text" % "1.9"), - addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full)) +lazy val chisel6Settings = Seq( + libraryDependencies ++= Seq("org.chipsalliance" %% "chisel" % "6.0.0"), + addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % "6.0.0" cross CrossVersion.full) +) +lazy val chisel3Settings = Seq( + libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % "3.6.0"), + addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.6.0" cross CrossVersion.full) +) + +lazy val chiselSettings = (if (chisel6) chisel6Settings else chisel3Settings) ++ Seq( + libraryDependencies ++= Seq( + "org.apache.commons" % "commons-lang3" % "3.12.0", + "org.apache.commons" % "commons-text" % "1.9" + ) +) // Subproject definitions begin @@ -97,8 +116,8 @@ lazy val chiselSettings = Seq( lazy val hardfloat = freshProject("hardfloat", file("generators/hardfloat/hardfloat")) .settings(chiselSettings) - .dependsOn(midasTargetUtils) .settings(commonSettings) + .dependsOn(if (chisel6) midasStandaloneTargetUtils else midasTargetUtils) .settings( libraryDependencies ++= Seq( "org.scalatest" %% "scalatest" % "3.2.0" % "test" @@ -109,7 +128,6 @@ lazy val rocketMacros = (project in rocketChipDir / "macros") .settings(commonSettings) .settings( libraryDependencies ++= Seq( - "org.scala-lang" % "scala-reflect" % scalaVersion.value, ) ) @@ -118,11 +136,6 @@ lazy val diplomacy = freshProject("diplomacy", file("generators/diplomacy/diplom .settings(commonSettings) .settings(chiselSettings) .settings(Compile / scalaSource := baseDirectory.value / "diplomacy") - .settings( - libraryDependencies ++= Seq( - "com.lihaoyi" %% "sourcecode" % "0.3.1" - ) - ) lazy val rocketchip = freshProject("rocketchip", rocketChipDir) .dependsOn(hardfloat, rocketMacros, diplomacy, cde) @@ -131,18 +144,11 @@ lazy val rocketchip = freshProject("rocketchip", rocketChipDir) .settings( libraryDependencies ++= Seq( "com.lihaoyi" %% "mainargs" % "0.5.0", - "org.scala-lang" % "scala-reflect" % scalaVersion.value, "org.json4s" %% "json4s-jackson" % "4.0.5", "org.scalatest" %% "scalatest" % "3.2.0" % "test", - "org.scala-graph" %% "graph-core" % "1.13.5", - "com.lihaoyi" %% "sourcecode" % "0.3.1" + "org.scala-graph" %% "graph-core" % "1.13.5" ) ) - .settings( // Settings for scalafix - semanticdbEnabled := true, - semanticdbVersion := scalafixSemanticdb.revision, - scalacOptions += "-Ywarn-unused" - ) lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies) @@ -150,19 +156,23 @@ lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies) // Contains annotations & firrtl passes you may wish to use in rocket-chip without // introducing a circular dependency between RC and MIDAS -lazy val midasTargetUtils = ProjectRef(firesimDir, "targetutils") +lazy val midasTargetUtils = (project in file ("sims/firesim/sim/midas/targetutils")) + .settings(commonSettings) + .settings(chiselSettings) +lazy val midasStandaloneTargetUtils = (project in file("tools/midas-targetutils")) + .settings(commonSettings) + .settings(chiselSettings) lazy val testchipip = (project in file("generators/testchipip")) .dependsOn(rocketchip, rocketchip_blocks) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) +val stageDir = if (chisel6) "tools/stage/src/main/scala" else "tools/stage-chisel3/src/main/scala" lazy val chipyard = (project in file("generators/chipyard")) - .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, iocell, - radiance, - sha3, // On separate line to allow for cleaner tutorial-setup patches + .dependsOn(testchipip, rocketchip, boom, rocketchip_blocks, rocketchip_inclusive_cache, dsptools, rocket_dsp_utils, - gemmini, icenet, tracegen, cva6, nvdla, radiance, sodor, ibex, fft_generator, + radiance, gemmini, icenet, tracegen, cva6, nvdla, radiance, sodor, ibex, fft_generator, constellation, mempress, barf, shuttle, caliptra_aes) .settings(libraryDependencies ++= rocketLibDeps.value) .settings( @@ -170,10 +180,11 @@ lazy val chipyard = (project in file("generators/chipyard")) "org.reflections" % "reflections" % "0.10.2" ) ) - .settings(commonSettings) + .settings(commonSettings) + .settings(Compile / unmanagedSourceDirectories += file(stageDir)) lazy val mempress = (project in file("generators/mempress")) - .dependsOn(rocketchip, midasTargetUtils) + .dependsOn(rocketchip) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) @@ -202,11 +213,6 @@ lazy val icenet = (project in file("generators/icenet")) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) -lazy val hwacha = (project in file("generators/hwacha")) - .dependsOn(rocketchip) - .settings(libraryDependencies ++= rocketLibDeps.value) - .settings(commonSettings) - lazy val boom = freshProject("boom", file("generators/boom")) .dependsOn(rocketchip) .settings(libraryDependencies ++= rocketLibDeps.value) @@ -232,17 +238,12 @@ lazy val sodor = (project in file("generators/riscv-sodor")) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) -lazy val sha3 = (project in file("generators/sha3")) - .dependsOn(rocketchip, midasTargetUtils) - .settings(libraryDependencies ++= rocketLibDeps.value) - .settings(commonSettings) - lazy val radiance = (project in file("generators/radiance")) .dependsOn(rocketchip, gemmini) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) -lazy val gemmini = (project in file("generators/gemmini")) +lazy val gemmini = freshProject("gemmini", file("generators/gemmini")) .dependsOn(rocketchip) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) @@ -253,7 +254,7 @@ lazy val nvdla = (project in file("generators/nvdla")) .settings(commonSettings) lazy val caliptra_aes = (project in file("generators/caliptra-aes-acc")) - .dependsOn(rocketchip, rocc_acc_utils, testchipip, midasTargetUtils) + .dependsOn(rocketchip, rocc_acc_utils, testchipip) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) @@ -262,25 +263,25 @@ lazy val rocc_acc_utils = (project in file("generators/rocc-acc-utils")) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) -lazy val iocell = Project(id = "iocell", base = file("./tools/barstools/") / "iocell") +lazy val tapeout = (project in file("./tools/tapeout/")) + .settings(chisel3Settings) // stuck on chisel3 and SFC + .settings(commonSettings) + .settings(scalaVersion := "2.13.10") // stuck on chisel3 2.13.10 + .settings(libraryDependencies ++= Seq("com.typesafe.play" %% "play-json" % "2.9.2")) + +val fixedpointDir = if (chisel6) "./tools/fixedpoint" else "./tools/fixedpoint-chisel3" +lazy val fixedpoint = freshProject("fixedpoint", file(fixedpointDir)) .settings(chiselSettings) .settings(commonSettings) -lazy val tapeout = (project in file("./tools/barstools/")) - .settings(chiselSettings) - .settings(commonSettings) - -lazy val fixedpoint = (project in file("./tools/fixedpoint/")) - .settings(chiselSettings) - .settings(commonSettings) - -lazy val dsptools = freshProject("dsptools", file("./tools/dsptools")) +val dsptoolsDir = if (chisel6) "./tools/dsptools" else "./tools/dsptools-chisel3" +lazy val dsptools = freshProject("dsptools", file(dsptoolsDir)) .dependsOn(fixedpoint) .settings( chiselSettings, commonSettings, libraryDependencies ++= Seq( - "edu.berkeley.cs" %% "chiseltest" % "0.6.0", + "edu.berkeley.cs" %% "chiseltest" % chiselTestVersion, "org.scalatest" %% "scalatest" % "3.2.+" % "test", "org.typelevel" %% "spire" % "0.18.0", "org.scalanlp" %% "breeze" % "2.1.0", @@ -310,8 +311,17 @@ lazy val rocketchip_inclusive_cache = (project in file("generators/rocket-chip-i .settings(libraryDependencies ++= rocketLibDeps.value) // Library components of FireSim -lazy val midas = ProjectRef(firesimDir, "midas") -lazy val firesimLib = ProjectRef(firesimDir, "firesimLib") +lazy val midas = (project in file ("sims/firesim/sim/midas")) + .dependsOn(rocketchip, midasTargetUtils) + .settings(libraryDependencies ++= Seq( + "org.scalatestplus" %% "scalacheck-1-14" % "3.1.3.0" % "test")) + .settings(commonSettings) + .settings(chiselSettings) + +lazy val firesimLib = (project in file("sims/firesim/sim/firesim-lib")) + .dependsOn(midas, icenet, testchipip, rocketchip_blocks) + .settings(commonSettings) + .settings(chiselSettings) lazy val firechip = (project in file("generators/firechip")) .dependsOn(chipyard, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") diff --git a/common.mk b/common.mk index 8770683e..bc5ace81 100644 --- a/common.mk +++ b/common.mk @@ -17,10 +17,8 @@ HELP_COMPILATION_VARIABLES += \ " EXTRA_SIM_SOURCES = additional simulation sources needed for simulator" \ " EXTRA_SIM_REQS = additional make requirements to build the simulator" \ " EXTRA_SIM_OUT_NAME = additional suffix appended to the simulation .out log filename" \ -" ENABLE_CUSTOM_FIRRTL_PASS = if set, enable custom firrtl passes (SFC lowers to LowFIRRTL & MFC converts to Verilog)" \ " ENABLE_YOSYS_FLOW = if set, add compilation flags to enable the vlsi flow for yosys(tutorial flow)" \ " EXTRA_CHISEL_OPTIONS = additional options to pass to the Chisel compiler" \ -" EXTRA_BASE_FIRRTL_OPTIONS = additional options to pass to the Scala FIRRTL compiler" \ " MFC_BASE_LOWERING_OPTIONS = override lowering options to pass to the MLIR FIRRTL compiler" \ " ASPECTS = comma separated list of Chisel aspect flows to run (e.x. chipyard.upf.ChipTopUPFAspect)" @@ -91,12 +89,12 @@ CHECK_SUBMODULES_COMMAND = echo "Checking all submodules in generators/ are init SCALA_EXT = scala VLOG_EXT = sv v -CHIPYARD_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim fpga/fpga-shells fpga/src) +CHIPYARD_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim/src sims/firesim/sim/firesim-lib sims/firesim/sim/midas fpga/fpga-shells fpga/src tools/stage tools/stage-chisel3) CHIPYARD_SCALA_SOURCES = $(call lookup_srcs_by_multiple_type,$(CHIPYARD_SOURCE_DIRS),$(SCALA_EXT)) CHIPYARD_VLOG_SOURCES = $(call lookup_srcs_by_multiple_type,$(CHIPYARD_SOURCE_DIRS),$(VLOG_EXT)) -BARSTOOLS_SOURCE_DIRS = $(addprefix $(base_dir)/,tools/barstools) -BARSTOOLS_SCALA_SOURCES = $(call lookup_srcs_by_multiple_type,$(BARSTOOLS_SOURCE_DIRS),$(SCALA_EXT)) -BARSTOOLS_VLOG_SOURCES = $(call lookup_srcs_by_multiple_type,$(BARSTOOLS_SOURCE_DIRS),$(VLOG_EXT)) +TAPEOUT_SOURCE_DIRS = $(addprefix $(base_dir)/,tools/tapeout) +TAPEOUT_SCALA_SOURCES = $(call lookup_srcs_by_multiple_type,$(TAPEOUT_SOURCE_DIRS),$(SCALA_EXT)) +TAPEOUT_VLOG_SOURCES = $(call lookup_srcs_by_multiple_type,$(TAPEOUT_SOURCE_DIRS),$(VLOG_EXT)) # This assumes no SBT meta-build sources SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools) SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt $(base_dir)/project/build.properties @@ -130,7 +128,7 @@ $(CHIPYARD_CLASSPATH_TARGETS) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEP $(call run_sbt_assembly,$(SBT_PROJECT),$(CHIPYARD_CLASSPATH)) # order only dependency between sbt runs needed to avoid concurrent sbt runs -$(TAPEOUT_CLASSPATH_TARGETS) &: $(BARSTOOLS_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(BARSTOOLS_VLOG_SOURCES) | $(CHIPYARD_CLASSPATH_TARGETS) +$(TAPEOUT_CLASSPATH_TARGETS) &: $(TAPEOUT_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(TAPEOUT_VLOG_SOURCES) | $(CHIPYARD_CLASSPATH_TARGETS) mkdir -p $(dir $@) $(call run_sbt_assembly,tapeout,$(TAPEOUT_CLASSPATH)) @@ -164,20 +162,11 @@ define mfc_extra_anno_contents } ] endef -define sfc_extra_low_transforms_anno_contents -[ - { - "class": "firrtl.stage.RunFirrtlTransformAnnotation", - "transform": "barstools.tapeout.transforms.ExtraLowTransforms" - } -] -endef export mfc_extra_anno_contents export sfc_extra_low_transforms_anno_contents -$(EXTRA_ANNO_FILE) $(MFC_EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) &: $(ANNO_FILE) +$(FINAL_ANNO_FILE) $(MFC_EXTRA_ANNO_FILE) &: $(ANNO_FILE) echo "$$mfc_extra_anno_contents" > $(MFC_EXTRA_ANNO_FILE) - echo "$$sfc_extra_low_transforms_anno_contents" > $(SFC_EXTRA_ANNO_FILE) - jq -s '[.[][]]' $(ANNO_FILE) $(MFC_EXTRA_ANNO_FILE) > $(EXTRA_ANNO_FILE) + jq -s '[.[][]]' $(ANNO_FILE) $(MFC_EXTRA_ANNO_FILE) > $(FINAL_ANNO_FILE) .PHONY: firrtl firrtl: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) @@ -195,30 +184,9 @@ SFC_MFC_TARGETS = \ $(MFC_BB_MODS_FILELIST) \ $(GEN_COLLATERAL_DIR) -SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF) MFC_BASE_LOWERING_OPTIONS ?= emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,disallowPortDeclSharing,locationInfoStyle=wrapInAtSquareBracket # DOC include start: FirrtlCompiler -# There are two possible cases for this step. In the first case, SFC -# compiles Chisel to CHIRRTL, and MFC compiles CHIRRTL to Verilog. Otherwise, -# when custom FIRRTL transforms are included or if a Fixed type is used within -# the dut, SFC compiles Chisel to LowFIRRTL and MFC compiles it to Verilog. -# Users can indicate to the Makefile of custom FIRRTL transforms by setting the -# "ENABLE_CUSTOM_FIRRTL_PASS" variable. -# -# hack: lower to low firrtl if Fixed types are found -# hack: when using dontTouch, io.cpu annotations are not removed by SFC, -# hence we remove them manually by using jq before passing them to firtool - -$(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) &: $(FIRRTL_FILE) -ifeq (,$(ENABLE_CUSTOM_FIRRTL_PASS)) - echo $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), low, none) > $(SFC_LEVEL) - echo "$(EXTRA_BASE_FIRRTL_OPTIONS)" $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), "$(SFC_REPL_SEQ_MEM)",) > $(EXTRA_FIRRTL_OPTIONS) -else - echo low > $(SFC_LEVEL) - echo "$(EXTRA_BASE_FIRRTL_OPTIONS)" "$(SFC_REPL_SEQ_MEM)" > $(EXTRA_FIRRTL_OPTIONS) -endif - $(MFC_LOWERING_OPTIONS): mkdir -p $(dir $@) ifeq (,$(ENABLE_YOSYS_FLOW)) @@ -227,29 +195,8 @@ else echo "$(MFC_BASE_LOWERING_OPTIONS),disallowPackedArrays" > $@ endif -$(FINAL_ANNO_FILE): $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) $(SFC_LEVEL) - if [ $(shell cat $(SFC_LEVEL)) = low ]; then jq -s '[.[][]]' $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) > $@; fi - if [ $(shell cat $(SFC_LEVEL)) = none ]; then cat $(EXTRA_ANNO_FILE) > $@; fi - touch $@ - -$(SFC_MFC_TARGETS) &: private TMP_DIR := $(shell mktemp -d -t cy-XXXXXXXX) -$(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) $(MFC_LOWERING_OPTIONS) +$(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(MFC_LOWERING_OPTIONS) rm -rf $(GEN_COLLATERAL_DIR) - $(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),barstools.tapeout.transforms.GenerateModelStageMain,\ - --no-dedup \ - --output-file $(SFC_FIRRTL_BASENAME) \ - --output-annotation-file $(SFC_ANNO_FILE) \ - --target-dir $(GEN_COLLATERAL_DIR) \ - --input-file $(FIRRTL_FILE) \ - --annotation-file $(FINAL_ANNO_FILE) \ - --log-level $(FIRRTL_LOGLEVEL) \ - --allow-unrecognized-annotations \ - -X $(shell cat $(SFC_LEVEL)) \ - $(shell cat $(EXTRA_FIRRTL_OPTIONS))) - -mv $(SFC_FIRRTL_BASENAME).lo.fir $(SFC_FIRRTL_FILE) 2> /dev/null # Optionally change file type when SFC generates LowFIRRTL - @if [ $(shell cat $(SFC_LEVEL)) = low ]; then cat $(SFC_ANNO_FILE) | jq 'del(.[] | select(.target | test("io.cpu"))?)' > $(TMP_DIR)/unnec-anno-deleted.sfc.anno.json; fi - @if [ $(shell cat $(SFC_LEVEL)) = low ]; then cat $(TMP_DIR)/unnec-anno-deleted.sfc.anno.json | jq 'del(.[] | select(.class | test("SRAMAnnotation"))?)' > $(TMP_DIR)/unnec-anno-deleted2.sfc.anno.json; fi - @if [ $(shell cat $(SFC_LEVEL)) = low ]; then cat $(TMP_DIR)/unnec-anno-deleted2.sfc.anno.json > $(SFC_ANNO_FILE) && rm $(TMP_DIR)/unnec-anno-deleted.sfc.anno.json && rm $(TMP_DIR)/unnec-anno-deleted2.sfc.anno.json; fi firtool \ --format=fir \ --export-module-hierarchy \ @@ -261,11 +208,10 @@ $(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_F --lowering-options=$(shell cat $(MFC_LOWERING_OPTIONS)) \ --repl-seq-mem \ --repl-seq-mem-file=$(MFC_SMEMS_CONF) \ - --annotation-file=$(SFC_ANNO_FILE) \ + --annotation-file=$(FINAL_ANNO_FILE) \ --split-verilog \ -o $(GEN_COLLATERAL_DIR) \ - $(SFC_FIRRTL_FILE) - -mv $(SFC_SMEMS_CONF) $(MFC_SMEMS_CONF) 2> /dev/null + $(FIRRTL_FILE) $(SED) -i 's/.*/& /' $(MFC_SMEMS_CONF) # need trailing space for SFC macrocompiler touch $(MFC_BB_MODS_FILELIST) # if there are no BB's then the file might not be generated, instead always generate it # DOC include end: FirrtlCompiler @@ -301,12 +247,12 @@ $(TOP_SMEMS_CONF) $(MODEL_SMEMS_CONF) &: $(MFC_SMEMS_CONF) $(MFC_MODEL_HRCHY_JS # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs TOP_MACROCOMPILER_MODE ?= --mode synflops $(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(TOP_SMEMS_CONF) - $(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),barstools.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(TOP_MACROCOMPILER_MODE)) + $(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),tapeout.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(TOP_MACROCOMPILER_MODE)) touch $(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) MODEL_MACROCOMPILER_MODE = --mode synflops $(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(MODEL_SMEMS_CONF) - $(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),barstools.macros.MacroCompiler, -n $(MODEL_SMEMS_CONF) -v $(MODEL_SMEMS_FILE) -f $(MODEL_SMEMS_FIR) $(MODEL_MACROCOMPILER_MODE)) + $(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),tapeout.macros.MacroCompiler, -n $(MODEL_SMEMS_CONF) -v $(MODEL_SMEMS_FILE) -f $(MODEL_SMEMS_FIR) $(MODEL_MACROCOMPILER_MODE)) touch $(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) ######################################################################################## diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64-lean.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64-lean.conda-lock.yml deleted file mode 100644 index 9a4aabe8..00000000 --- a/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64-lean.conda-lock.yml +++ /dev/null @@ -1,2636 +0,0 @@ -# This lock file was generated by conda-lock (https://github.com/conda-incubator/conda-lock). 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https://github.com/ucb-bar/esp-tools-feedstock diff --git a/docs/Advanced-Concepts/Resources.rst b/docs/Advanced-Concepts/Resources.rst index fbfaad60..99125194 100644 --- a/docs/Advanced-Concepts/Resources.rst +++ b/docs/Advanced-Concepts/Resources.rst @@ -33,7 +33,3 @@ For example: lazy val myAwesomeAccel = (project in file("generators/myAwesomeAccelFolder")) .dependsOn(rocketchip) .settings(commonSettings) - - lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/")) - .dependsOn(myAwesomeAccel) - .settings(commonSettings) diff --git a/docs/Advanced-Concepts/Top-Testharness.rst b/docs/Advanced-Concepts/Top-Testharness.rst index e412eeff..483814e3 100644 --- a/docs/Advanced-Concepts/Top-Testharness.rst +++ b/docs/Advanced-Concepts/Top-Testharness.rst @@ -25,6 +25,8 @@ The default standard ``ChipTop`` provides a mimimal, barebones template for ``IO For tapeouts, integrating Analog IP, or other non-standard use cases, Chipyard supports specifying a custom ``ChipTop`` using the ``BuildTop`` key. An example of a custom ChipTop which uses non-standard IOCells is provided in `generators/chipyard/src/main/scala/example/CustomChipTop.scala `__ +You can also specify a fully custom ChipTop that does not use any RocketChip or Chipyard SoC components. An example of this is provided in `generators/chipyard/src/main/scala/example/EmptyChipTop.scala `__. The ``EmptyChipTop`` example can be built with ``make CONFIG=EmptyChipTopConfig TOP=EmptyChipTop``. + System/DigitalTop ------------------------- diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index 669bfdfc..a412c2a3 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -31,19 +31,9 @@ Processor Cores Accelerators ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -**Hwacha** - A decoupled vector architecture co-processor. - Hwacha currently implements a non-standard RISC-V extension, using a vector architecture programming model. - Hwacha integrates with a Rocket or BOOM core using the RoCC (Rocket Custom Co-processor) interface. - See :ref:`Generators/Hwacha:Hwacha` for more information. - **Gemmini** A matrix-multiply accelerator targeting neural-networks -**SHA3** - A fixed-function accelerator for the SHA3 hash function. This simple accelerator is used as a demonstration for some of the - Chipyard integration flows using the RoCC interface. - System Components: ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -79,9 +69,9 @@ Tools FIRRTL enables digital circuits manipulation between Chisel elaboration and Verilog generation. See :ref:`Tools/FIRRTL:FIRRTL` for more information. -**Barstools** +**Tapeout-Tools (Formerly Barstools)** A collection of common FIRRTL transformations used to manipulate a digital circuit without changing the generator source RTL. - See :ref:`Tools/Barstools:Barstools` for more information. + See :ref:`Tools/Tapeout-Tools:Tapeout-Tools` for more information. **Dsptools** A Chisel library for writing custom signal processing hardware, as well as integrating custom signal processing hardware into an SoC (especially a Rocket-based SoC). @@ -95,10 +85,6 @@ Toolchains The riscv-tools repository was previously required to run any RISC-V software, however, many of the riscv-tools components have since been upstreamed to their respective open-source projects (Linux, GNU, etc.). Nevertheless, for consistent versioning, as well as software design flexibility for custom hardware, we include the riscv-tools repository and installation in the Chipyard framework. -**esp-tools** - A fork of riscv-tools, designed to work with the Hwacha non-standard RISC-V extension. - This fork can also be used as an example demonstrating how to add additional RoCC accelerators to the ISA-level simulation (Spike) and the higher-level software toolchain (GNU binutils, riscv-opcodes, etc.) - Software ------------------------------------------- diff --git a/docs/Chipyard-Basics/Initial-Repo-Setup.rst b/docs/Chipyard-Basics/Initial-Repo-Setup.rst index 5ee4702b..1ed00628 100644 --- a/docs/Chipyard-Basics/Initial-Repo-Setup.rst +++ b/docs/Chipyard-Basics/Initial-Repo-Setup.rst @@ -63,11 +63,7 @@ Start by checking out the proper Chipyard version. Run: # note: this may not be the latest release if the documentation version != "stable" git checkout |version| -Next run the following script to fully setup Chipyard with a specific toolchain. -There are two toolchains, one for normal RISC-V programs called ``riscv-tools`` which is the one needed for most Chipyard use-cases, and another for Hwacha called ``esp-tools``. -Run the following script based off which compiler you would like to use. - -.. Note:: Prior versions of Chipyard recommended ``esp-tools`` for Gemmini development. Gemmini should now be used with the standard ``riscv-tools``. +Next run the following script to fully setup Chipyard with the ``riscv-tools`` toolchain. .. Warning:: The following script will complete a "full" installation of Chipyard which may take a long time depending on the system. Ensure that this script completes fully (no interruptions) before continuing on. User can use the ``--skip`` or ``-s`` flag to skip steps: @@ -96,7 +92,7 @@ Run the following script based off which compiler you would like to use. .. code-block:: shell - ./build-setup.sh riscv-tools # or esp-tools + ./build-setup.sh riscv-tools This script wraps around the conda environment initialization process, initializes all submodules (with the ``init-submodules-no-riscv-tools.sh`` script), installs a toolchain, and runs other setups. See ``./build-setup.sh --help`` for more details on what this does and how to disable parts of the setup. @@ -107,7 +103,7 @@ See ``./build-setup.sh --help`` for more details on what this does and how to di .. Note:: If you already have a working conda environment setup, separate Chipyard clones can use that pre-used environment in combination with running the aforementioned scripts yourself (``init-submodules...``, ``build-toolchain...``, etc). -.. Note:: If you are a power user and would like to build your own compiler/toolchain, you can refer to the https://github.com/ucb-bar/riscv-tools-feedstock and https://github.com/ucb-bar/esp-tools-feedstock repositories (submoduled in the ``toolchains/*`` directories) on how to build the compiler yourself. +.. Note:: If you are a power user and would like to build your own compiler/toolchain, you can refer to the https://github.com/ucb-bar/riscv-tools-feedstock repository (submoduled in the ``toolchains/*`` directories) on how to build the compiler yourself. By running the following command you should see a environment listed with the path ``$CHIPYARD_DIRECTORY/.conda-env``. diff --git a/docs/Customization/Custom-Chisel.rst b/docs/Customization/Custom-Chisel.rst index a3b4ef72..126f6837 100644 --- a/docs/Customization/Custom-Chisel.rst +++ b/docs/Customization/Custom-Chisel.rst @@ -59,8 +59,8 @@ should look something like this: .. code-block:: scala lazy val chipyard = (project in file("generators/chipyard")) - .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, iocell, - sha3, dsptools, `rocket-dsp-utils`, + .dependsOn(testchipip, rocketchip, boom, rocketchip_blocks, rocketchip_inclusive_cache, + dsptools, `rocket-dsp-utils`, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator, yourproject, // <- added to the middle of the list for simplicity constellation, mempress) diff --git a/docs/Customization/Firrtl-Transforms.rst b/docs/Customization/Firrtl-Transforms.rst deleted file mode 100644 index 1113bde6..00000000 --- a/docs/Customization/Firrtl-Transforms.rst +++ /dev/null @@ -1,106 +0,0 @@ -.. _firrtl-transforms: - -Adding a Firrtl Transform -========================= - -Similar to how LLVM IR passes can perform transformations and optimizations on software, FIRRTL transforms can -modify Chisel-elaborated RTL. -As mentioned in Section :ref:`Tools/FIRRTL:firrtl`, transforms are modifications that happen on the FIRRTL IR that can modify a circuit. -Transforms are a powerful tool to take in the FIRRTL IR that is emitted from Chisel and run analysis or convert the circuit into a new form. - -The Scala FIRRTL Compiler and the MLIR FIRRTL Compiler ------------------------------------------------------- -In Chipyard, two FIRRTL compilers work together to compile Chisel into Verilog. The Scala FIRRTL compiler (SFC) and the MLIR FIRRTL compiler (MFC). -They are basically doing the same thing, except that MFC is written in C++ which makes compilation much faster (the generated Verilog will be different). In the default setting, the SFC will compile Chisel into CHIRRTL and MFC will -compile CHIRRTL into Verilog (as of now, we are using SFC as a backup for cases when MFC doesn't work, e.g., when the design is using Fixed types). By setting the ``ENABLE_CUSTOM_FIRRTL_PASS`` env variable to a non-zero value, -we can make the SFC compile Chisel into LowFIRRTL so that our custom FIRRTL passes are applied. - -For more information on MLIR FIRRTL Compiler, please visit https://mlir.llvm.org/ and https://circt.llvm.org/. - -Where to add transforms ------------------------ - -In Chipyard, the FIRRTL compiler is called multiple times to create a "Top" file that contains the DUT and a "Model" file containing the test harness, which instantiates the DUT. -The "Model" file does not contain the DUT's module definition or any of its submodules. -This is done by the ``tapeout`` SBT project (located in ``tools/barstools/tapeout``) which calls ``GenerateModelStageMain`` (a function that wraps the multiple FIRRTL compiler calls and extra transforms). - -.. literalinclude:: ../../common.mk - :language: make - :start-after: DOC include start: FirrtlCompiler - :end-before: DOC include end: FirrtlCompiler - -If you look inside of the `tools/barstools/tapeout/src/main/scala/transforms/GenerateModelStageMain.scala `__ file, -you can see that FIRRTL is invoked for "Model". Currently, the FIRRTL compiler is agnostic to the ``TOP`` and ``MODEL`` differentiation, -and the user is responsible for providing annotations that will inform the compiler where(``TOP`` vs ``MODEL``) to perform the custom FIRRTL transformations. - -For more information on Barstools, please visit the :ref:`Tools/Barstools:Barstools` section. - -Examples of transforms ----------------------- - -There are multiple examples of transforms that you can apply and are spread across the FIRRTL ecosystem. -Within FIRRTL there is a default set of supported transforms located in https://github.com/freechipsproject/firrtl/tree/master/src/main/scala/firrtl/transforms. -This includes transforms that can flatten modules (``Flatten``), group modules together (``GroupAndDedup``), and more. - -Transforms can be standalone or can take annotations as input. Annotations are used to pass information between FIRRTL transforms. This includes information on -what modules to flatten, group, and more. Annotations can be added to the code by -adding them to your Chisel source or by creating a serialized annotation ``json`` file and adding it to the FIRRTL compiler -(note: annotating the Chisel source will automatically serialize the annotation as a ``json`` snippet into the build system for you). -**The recommended way to annotate something is to do it in the Chisel source, but not all annotation types have Chisel APIs**. - -The example below shows two ways to annotate the signal using the ``DontTouchAnnotation`` -(makes sure that a particular signal is not removed by the "Dead Code Elimination" pass in FIRRTL): - -* use the Chisel API/wrapper function called ``dontTouch`` that does this automatically for you (more `dontTouch `__ information): -* directly annotate the signal with the ``annotate`` function and the ``DontTouchAnnotation`` class if there is no Chisel API for it (note: most FIRRTL annotations have Chisel APIs for them) - -.. code-block:: scala - - class TopModule extends Module { - ... - val submod = Module(new Submodule) - ... - } - - class Submodule extends Module { - ... - val some_signal := ... - - // MAIN WAY TO USE `dontTouch` - // how to annotate if there is a Chisel API/wrapper - chisel3.dontTouch(some_signal) - - // how to annotate WITHOUT a Chisel API/wrapper - annotate(new ChiselAnnotation { - def toFirrtl = DontTouchAnnotation(some_signal.toNamed) - }) - - ... - } - -Here is an example of the ``DontTouchAnnotation`` when it is serialized: - -.. code-block:: json - - [ - { - "class": "firrtl.transforms.DontTouchAnnotation", - "target": "~TopModule|Submodule>some_signal" - } - ] - -In this case, the specific syntax depends on the type of annotation and its fields. -One of the easier ways to figure out the serialized syntax is to first try and find a Chisel -annotation to add to the code. Then you can look at the collateral that is generated from the -build system, find the ``*.anno.json``, and find the proper syntax for the annotation. - -Once ``yourAnnoFile.json`` is created then you can add ``-faf yourAnnoFile.json`` to the FIRRTL -compiler invocation in ``common.mk``. - -.. literalinclude:: ../../common.mk - :language: make - :start-after: DOC include start: FirrtlCompiler - :end-before: DOC include end: FirrtlCompiler - -If you are interested in writing FIRRTL transforms please refer to the FIRRTL documentation located here: -https://github.com/freechipsproject/firrtl/wiki. diff --git a/docs/Customization/Heterogeneous-SoCs.rst b/docs/Customization/Heterogeneous-SoCs.rst index 1f534393..0fd7086c 100644 --- a/docs/Customization/Heterogeneous-SoCs.rst +++ b/docs/Customization/Heterogeneous-SoCs.rst @@ -4,7 +4,7 @@ Heterogeneous SoCs =============================== The Chipyard framework involves multiple cores and accelerators that can be composed in arbitrary ways. -This discussion will focus on how you combine Rocket, BOOM and Hwacha in particular ways to create a unique SoC. +This discussion will focus on how you combine Rocket and BOOM in particular ways to create a unique SoC. Creating a Rocket and BOOM System ------------------------------------------- @@ -21,40 +21,6 @@ The following example shows a dual core BOOM with a single core Rocket. :end-before: DOC include end: DualBoomAndSingleRocket -Adding Hwachas -------------------------------------------- - -Adding a Hwacha accelerator is as easy as adding the ``DefaultHwachaConfig`` so that it can setup the Hwacha parameters and add itself to the ``BuildRoCC`` parameter. -An example of adding a Hwacha to all tiles in the system is below. - -.. literalinclude:: ../../generators/chipyard/src/main/scala/config/HeteroConfigs.scala - :language: scala - :start-after: DOC include start: BoomAndRocketWithHwacha - :end-before: DOC include end: BoomAndRocketWithHwacha - -In this example, Hwachas are added to both BOOM tiles and to the Rocket tile. -All with the same Hwacha parameters. - -Assigning Accelerators to Specific Tiles with MultiRoCC -------------------------------------------------------- - -Located in ``generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala`` is a config fragment that provides support for adding RoCC accelerators to specific tiles in your SoC. -Named ``MultiRoCCKey``, this key allows you to attach RoCC accelerators based on the ``hartId`` of the tile. -For example, using this allows you to create a 8 tile system with a RoCC accelerator on only a subset of the tiles. -An example is shown below with two BOOM cores, and one Rocket tile with a RoCC accelerator (Hwacha) attached. - -.. literalinclude:: ../../generators/chipyard/src/main/scala/config/HeteroConfigs.scala - :language: scala - :start-after: DOC include start: DualBoomAndRocketOneHwacha - :end-before: DOC include end: DualBoomAndRocketOneHwacha - -The ``WithMultiRoCCHwacha`` config fragment assigns a Hwacha accelerator to a particular ``hartId`` (in this case, the ``hartId`` of ``0`` corresponds to the Rocket core). -Finally, the ``WithMultiRoCC`` config fragment is called. -This config fragment sets the ``BuildRoCC`` key to use the ``MultiRoCCKey`` instead of the default. -This must be used after all the RoCC parameters are set because it needs to override the ``BuildRoCC`` parameter. -If this is used earlier in the configuration sequence, then MultiRoCC does not work. - -This config fragment can be changed to put more accelerators on more cores by changing the arguments to cover more ``hartId``'s (i.e. ``WithMultiRoCCHwacha(0,1,3,6,...)``). Since config fragments are applied from right-to-left (or bottom-to-top as they are formatted here), the right-most config fragment specifying a core (which is ``freechips.rocketchip.subsystem.WithNBigCores`` in the example above) gets the first hart ID. Consider this config: diff --git a/docs/Customization/Incorporating-Verilog-Blocks.rst b/docs/Customization/Incorporating-Verilog-Blocks.rst index fde44411..9d7ceb81 100644 --- a/docs/Customization/Incorporating-Verilog-Blocks.rst +++ b/docs/Customization/Incorporating-Verilog-Blocks.rst @@ -33,19 +33,6 @@ different directory from Chisel (Scala) sources. vsrc/ YourFile.v -In addition to the steps outlined in the previous section on adding a -project to the ``build.sbt`` at the top level, it is also necessary to -add any projects that contain Verilog IP as dependencies to the -``tapeout`` project. This ensures that the Verilog sources are visible -to the downstream FIRRTL passes that provide utilities for integrating -Verilog files into the build process, which are part of the -``tapeout`` package in ``barstools/tapeout``. - -.. code-block:: scala - - lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/")) - .dependsOn(chisel_testers, example, yourproject) - .settings(commonSettings) For this concrete GCD example, we will be using a ``GCDMMIOBlackBox`` Verilog module that is defined in the ``chipyard`` project. The Scala diff --git a/docs/Customization/index.rst b/docs/Customization/index.rst index 8e268059..9656efe6 100644 --- a/docs/Customization/index.rst +++ b/docs/Customization/index.rst @@ -29,8 +29,6 @@ We also provide information on: - The boot process for Chipyard SoCs -- Examples of FIRRTL transforms used in Chipyard, and where they are specified - We recommend reading all these pages in order. Hit next to get started! .. toctree:: @@ -50,5 +48,4 @@ We recommend reading all these pages in order. Hit next to get started! Incorporating-Verilog-Blocks Memory-Hierarchy Boot-Process - Firrtl-Transforms IOBinders diff --git a/docs/Generators/Hwacha.rst b/docs/Generators/Hwacha.rst deleted file mode 100644 index 62f4dc06..00000000 --- a/docs/Generators/Hwacha.rst +++ /dev/null @@ -1,15 +0,0 @@ -Hwacha -==================================== - -The Hwacha project is developing a new vector architecture for future computer systems that are constrained in their power and energy consumption. -The Hwacha project is inspired by traditional vector machines from the 70s and 80s, and lessons learned from our previous vector-thread architectures such as Scale and Maven -The Hwacha project includes the Hwacha microarchitecture generator, as well as the ``XHwacha`` non-standard RISC-V extension. Hwacha does not implement the RISC-V standard vector extension proposal. - -For more information on the Hwacha project, please visit the `Hwacha website `__ or search for "Krste Asanovic Hwacha" on Google Scholar for publications. - -To add the Hwacha vector unit to an SoC, you should add the ``hwacha.DefaultHwachaConfig`` config fragment to the SoC configurations. The Hwacha vector unit uses the RoCC port of a Rocket or BOOM `tile`, and by default connects to the memory system through the `System Bus` (i.e., directly to the L2 cache). - -To change the configuration of the Hwacha vector unit, you can write a custom configuration to replace the ``DefaultHwachaConfig``. You can view the ``DefaultHwachaConfig`` under `generators/hwacha/src/main/scala/configs.scala `__ to see the possible configuration parameters. - -Since Hwacha implements a non-standard RISC-V extension, it requires a unique software toolchain to be able to compile and assemble its vector instructions. -To install the Hwacha toolchain, run the ``./scripts/build-toolchains.sh esp-tools`` command within the root Chipyard directory. This may take a while, and it will install the ``esp-tools-install`` directory within your Chipyard root directory. ``esp-tools`` is a fork of ``riscv-tools`` (formerly a collection of relevant software RISC-V tools) that was enhanced with additional non-standard vector instructions. However, due to the upstreaming of the equivalent RISC-V toolchains, ``esp-tools`` may not be up-to-date with the latest mainline version of the tools included in it. diff --git a/docs/Generators/SHA3.rst b/docs/Generators/SHA3.rst deleted file mode 100644 index 428e2ebe..00000000 --- a/docs/Generators/SHA3.rst +++ /dev/null @@ -1,81 +0,0 @@ -SHA3 RoCC Accelerator -=================================== -The SHA3 accelerator is a basic RoCC accelerator for the SHA3 hashing algorithm. -We like using SHA3 in Chipyard tutorial content because it is a self-contained, simple -example of integrating a custom accelerator into Chipyard. - - -Introduction ------------------------------------ -Secure hashing algorithms represent a class of hashing functions that provide four attributes: ease -of hash computation, inability to generate the message from the hash (one-way property), inability -to change the message and not the hash (weakly collision free property), and inability to find -two messages with the same hash (strongly collision free property). The National Institute of -Standards and Technology (NIST) recently held a competition for a new algorithm to be added to -its set of Secure Hashing Algorithms (SHA). In 2012 the winner was determined to be the Keccak -hashing function and a rough specification for SHA3 was established. The algorithm operates on -variable length messages with a sponge function, and thus alternates between absorbing chunks of -the message into a set of state bits and permuting the state. The absorbing is a simple bitwise -XOR while the permutation is a more complex function composed of several operations, χ, θ, ρ, -π, ι, that all perform various bitwise operations, including rotations, parity calculations, XORs, -etc. The Keccak hashing function is parameterized for different sizes of state and message chunks -but for this accelerator we will only support the Keccak-256 variant with 1600 bits of state and -1088 bit message chunks. A diagram of the SHA3 accelerator is shown below. - -.. image:: ../_static/images/sha3.png - -Technical Details ------------------------------------- -The accelerator is designed around three sub-systems, an -interface with the processor, an interface with memory, and -the actual hashing computation system. The interface -with the processor is designed using the ROCC interface for -coprocessors integrating with the RISC-V Rocket/BOOM -processor. It includes the ability to transfer two 64 bit -words to the co-processor, the request for a return value, -and a small field for the function requested. The accelerator -receives these requests using a ready/valid interface. The -ROCC instruction is parsed and the needed information is -stored into a execution context. The execution context contains -the memory address of the message being hashed, the memory address -to store the resulting hash in, the length of the message, and -several other control fields. - -Once the execution context is valid the memory subsystem -then begins to fetch chunks of the message. The memory -subsystem is fully decoupled from the other subsystems -and maintains a single full round memory buffers. -The accelerators memory interface can provide a -maximum of one 64 bit word per cycle which corresponds -to 17 requests needed to fill a buffer (the size is dictated by -the SHA3 algorithm). Memory requests to fill these buffers -are sent out as rapidly as the memory interface can handle, -with a tag field set to allow the different memory buffers -requests to be distinguished, as they may be returned out of -order. Once the memory subsystem has filled a buffer the -control unit absorbs the buffer into the execution -context, at which point the execution context is free to -begin permutation, and the memory buffer is free to send -more memory requests. - -After the buffer is absorbed, the hashing computation -subsystem begins the permutation operations. Once -the message is fully hashed, the hash is written to memory -with a simple state machine. - - -Using a SHA3 Accelerator ------------------------- -Since the SHA3 accelerator is designed as a RoCC accelerator, -it can be mixed into a Rocket or BOOM core by overriding the -``BuildRoCC`` key. The config fragment is defined in the SHA3 -generator. An example configuration highlighting the use of -this config fragment is shown here: - -.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketSha3Configs.scala - :language: scala - :start-after: DOC include start: Sha3Rocket - :end-before: DOC include end: Sha3Rocket - -The SHA3 example baremetal and Linux tests are located in the SHA3 repository. -Please refer to its `README.md `_ for more information on how to run/build the tests. diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index 651a6bae..88d9ee2a 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -22,12 +22,10 @@ so changes to the generators themselves will automatically be used when building Rocket BOOM Constellation - Hwacha Gemmini IceNet TestChipIP Rocket-Chip-Generators - SHA3 CVA6 Ibex fft diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index c84673b9..459418a2 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -50,16 +50,16 @@ This will elaborate the ``RocketConfig`` in the example project. .. Note:: The elaboration of ``RocketConfig`` requires about 6.5 GB of main memory. Otherwise the process will fail with ``make: *** [firrtl_temp] Error 137`` which is most likely related to limited resources. Other configurations might require even more main memory. -An executable called ``simulator-chipyard-RocketConfig`` will be produced. +An executable called ``simulator-chipyard.harness-RocketConfig`` will be produced. This executable is a simulator that has been compiled based on the design that was built. You can then use this executable to run any compatible RV64 code. For instance, to run one of the riscv-tools assembly tests. .. code-block:: shell - ./simulator-chipyard-RocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple + ./simulator-chipyard.harness-RocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple -.. Note:: In a VCS simulator, the simulator name will be ``simv-chipyard-RocketConfig`` instead of ``simulator-chipyard-RocketConfig``. +.. Note:: In a VCS simulator, the simulator name will be ``simv-chipyard.harness-RocketConfig`` instead of ``simulator-chipyard.harness-RocketConfig``. The makefiles have a ``run-binary`` rule that simplifies running the simulation executable. It adds many of the common command line options for you and redirects the output to a file. @@ -155,13 +155,6 @@ Therefore, in order to simulate a simple Rocket-based example system we can use: ./simulator-- ... -All ``make`` targets that can be applied to the default example, can also be applied to custom project using the custom environment variables. For example, the following code example will run the RISC-V assembly benchmark suite on the Hwacha subproject: - -.. code-block:: shell - - make SUB_PROJECT=hwacha run-asm-tests - - Finally, in the ``generated-src/<...>--/`` directory resides all of the collateral while the generated Verilog source files resides in ``generated-src/<...>--/gen-collateral`` for the build/simulation. Specifically, for ``CONFIG=RocketConfig`` the SoC top-level (``TOP``) Verilog file is ``ChipTop.sv`` while the (``Model``) file is ``TestHarness.sv``. diff --git a/docs/Tools/FIRRTL.rst b/docs/Tools/FIRRTL.rst index 2e88218f..f12b448e 100644 --- a/docs/Tools/FIRRTL.rst +++ b/docs/Tools/FIRRTL.rst @@ -7,6 +7,4 @@ Without going into too much detail, FIRRTL is consumed by FIRRTL compilers which An example of a FIRRTL pass (transformation) is one that optimizes out unused signals. Once the transformations are done, a Verilog file is emitted and the build process is done. -To see how FIRRTL is transformed to Verilog in Chipyard, please visit the :ref:`firrtl-transforms` section. - For more information on FIRRTL, please visit their `website `__. diff --git a/docs/Tools/Barstools.rst b/docs/Tools/Tapeout-Tools.rst similarity index 95% rename from docs/Tools/Barstools.rst rename to docs/Tools/Tapeout-Tools.rst index fa4176c4..b522c46d 100644 --- a/docs/Tools/Barstools.rst +++ b/docs/Tools/Tapeout-Tools.rst @@ -1,7 +1,7 @@ -Barstools +Tapeout-Tools =============================== -Barstools is a collection of useful FIRRTL transformations and compilers to help the build process. +Tapeout-Tools is a collection of useful FIRRTL transformations and compilers to help the build process. Included in the tools are a MacroCompiler (used to map Chisel memory constructs to vendor SRAMs), FIRRTL transforms (to separate harness and top-level SoC files), and more. Mapping technology SRAMs (MacroCompiler) @@ -23,16 +23,16 @@ An external module reference is a FIRRTL construct that enables a design to refe A list of unique SRAM configurations is output to a ``.conf`` file by FIRRTL, which is used to map technology SRAMs. Without this transform, FIRRTL will map all ``SeqMem`` s to flip-flop arrays with equivalent behavior, which may lead to a design that is difficult to route. -The ``.conf`` file is consumed by a tool called MacroCompiler, which is part of the :ref:`Tools/Barstools:Barstools` scala package. +The ``.conf`` file is consumed by a tool called MacroCompiler, which is part of the :ref:`Tools/Tapeout-Tools:Tapeout-Tools` scala package. MacroCompiler is also passed an ``.mdf`` file that describes the available list of technology SRAMs or the capabilities of the SRAM compiler, if one is provided by the foundry. -Typically a foundry SRAM compiler will be able to generate a set of different SRAMs collateral based on some requirements on size, aspect ratio, etc. (see :ref:`Tools/Barstools:SRAM MDF Fields`). +Typically a foundry SRAM compiler will be able to generate a set of different SRAMs collateral based on some requirements on size, aspect ratio, etc. (see :ref:`Tools/Tapeout-Tools:SRAM MDF Fields`). Using a user-customizable cost function, MacroCompiler will select the SRAMs that are the best fit for each dimensionality in the ``.conf`` file. This may include over provisioning (e.g. using a 64x1024 SRAM for a requested 60x1024, if the latter is not available) or arraying. Arraying can be done in both width and depth, as well as to solve masking constraints. For example, a 128x2048 array could be composed of four 64x1024 arrays, with two macros in parallel to create two 128x1024 virtual SRAMs which are combinationally muxed to add depth. If this macro requires byte-granularity write masking, but no technology SRAMs support masking, then the tool may choose to use thirty-two 8x1024 arrays in a similar configuration. You may wish to create a cache of your available SRAM macros either manually, or via a script. A reference script for creating a JSON of your SRAM macros is in the `asap7 technology library folder `__. -For information on writing ``.mdf`` files, look at `MDF on github `__ and a brief description in :ref:`Tools/Barstools:SRAM MDF Fields` section. +For information on writing ``.mdf`` files, look at `MDF on github `__ and a brief description in :ref:`Tools/Tapeout-Tools:SRAM MDF Fields` section. The output of MacroCompiler is a Verilog file containing modules that wrap the technology SRAMs into the specified interface names from the ``.conf``. If the technology supports an SRAM compiler, then MacroCompiler will also emit HammerIR that can be passed to Hammer to run the compiler itself and generate design collateral. @@ -105,7 +105,7 @@ This is necessary to facilitate post-synthesis and post-place-and-route simulati Simulations, after your design goes through a VLSI flow, will use the verilog netlist generated from the flow and will need an untouched test harness to drive it. Separating these components into separate files makes this straightforward. Without the separation the file that included the test harness would also redefine the DUT which is often disallowed in simulation tools. -To do this, there is a FIRRTL ``App`` in :ref:`Tools/Barstools:Barstools` called ``GenerateTopAndHarness``, which runs the appropriate transforms to elaborate the modules separately. +To do this, there is a FIRRTL ``App`` in :ref:`Tools/Tapeout-Tools:Tapeout-Tools` called ``GenerateTopAndHarness``, which runs the appropriate transforms to elaborate the modules separately. This also renames modules in the test harness so that any modules that are instantiated in both the test harness and the chip are uniquified. .. Note:: For VLSI projects, this ``App`` is run instead of the normal FIRRTL ``App`` to elaborate Verilog. @@ -133,5 +133,5 @@ This, unfortunately, breaks the process-agnostic RTL abstraction, so it is recom The simplest way to do this is to have a config fragment that when included updates instantiates the IO cells and connects them in the test harness. When simulating chip-specific designs, it is important to include the IO cells. The IO cell behavioral models will often assert if they are connected incorrectly, which is a useful runtime check. -They also keep the IO interface at the chip and test harness boundary (see :ref:`Tools/Barstools:Separating the Top module from the TestHarness module`) consistent after synthesis and place-and-route, +They also keep the IO interface at the chip and test harness boundary (see :ref:`Tools/Tapeout-Tools:Separating the Top module from the TestHarness module`) consistent after synthesis and place-and-route, which allows the RTL simulation test harness to be reused. diff --git a/docs/Tools/index.rst b/docs/Tools/index.rst index f8d0be95..491bd60c 100644 --- a/docs/Tools/index.rst +++ b/docs/Tools/index.rst @@ -12,4 +12,4 @@ The following pages will introduce them, and how we can use them in order to gen FIRRTL Treadle Dsptools - Barstools + Tapeout-Tools diff --git a/docs/VLSI/Basic-Flow.rst b/docs/VLSI/Basic-Flow.rst index 10a7af2f..a8f329a3 100644 --- a/docs/VLSI/Basic-Flow.rst +++ b/docs/VLSI/Basic-Flow.rst @@ -56,7 +56,7 @@ We will do so by calling ``make buildfile`` with appropriate Chipyard configurat As in the rest of the Chipyard flows, we specify our SoC configuration using the ``CONFIG`` make variable. However, unlike the rest of the Chipyard flows, in the case of physical design we might be interested in working in a hierarchical fashion and therefore we would like to work on a single module. Therefore, we can also specify a ``VLSI_TOP`` make variable with the same of a specific Verilog module (which should also match the name of the equivalent Chisel module) which we would like to work on. -The makefile will automatically call tools such as Barstools and the MacroCompiler (:ref:`Tools/Barstools:barstools`) in order to make the generated Verilog more VLSI friendly. +The makefile will automatically call tools such as Tapeout-Tools and the MacroCompiler (:ref:`Tools/Tapeout-Tools:Tapeout-Tools`) in order to make the generated Verilog more VLSI friendly. By default, the MacroCompiler will attempt to map memories into the SRAM options within the Hammer technology plugin. However, if you are working with a new process technology and prefer to work with flip-flop arrays, you can configure the MacroCompiler using the ``TOP_MACROCOMPILER_MODE`` make variable. For example, if your technology plugin does not have an SRAM compiler ready, you can use the ``TOP_MACROCOMPILER_MODE='--mode synflops'`` option (Note that synthesizing a design with only flipflops is very slow and will often may not meet constraints). We call the ``make buildfile`` command while also specifying the name of the process technology we are working with (same ``tech_name`` for the configuration files and plugin name) and the configuration files we created. Note, in the ASAP7 tutorial ((:ref:`tutorial`)) these configuration files are merged into a single file called ``example-asap7.yml``. @@ -227,7 +227,7 @@ While hierarchical physical design can be performed in multiple ways (top-down, The bottom-up approach traverses a tree representing the hierarchy starting from the leaves and towards the direction of the root (the "top level"), and runs the physical design flow on each node of the hierarchy tree using the previously layed-out children nodes. As nodes get closer to the root (or "top level") of the hierarchy, largers sections of the design get layed-out. -The Hammer hierarchical flow relies on a manually-specified descrition of the desired heirarchy tree. The specification of the heirarchy tree is defined based on the instance names in the generated Verilog, which sometime make this specification challenging due to inconsisent instance names. Additionally, the specification of the heirarchy tree is intertwined with the manual specification of a floorplan for the design. +The Hammer hierarchical flow relies on a manually-specified description of the desired hierarchy tree. The specification of the hierarchy tree is defined based on the instance names in the generated Verilog, which sometime make this specification challenging due to inconsisent instance names. Additionally, the specification of the hierarchy tree is intertwined with the manual specification of a floorplan for the design. For example, if we choose to specifiy the previously mentioned ``GemminiRocketConfig`` configuration in a hierarchical fashion in which the Gemmini accelerator and the last-level cache are run separetly from the top-level SoC, we would replace the floorplan example in ``example-design.yml`` from the :ref:`VLSI/Basic-Flow:Place-and-Route` section with the following specification: diff --git a/docs/VLSI/Building-A-Chip.rst b/docs/VLSI/Building-A-Chip.rst index adc79802..c635bc5f 100644 --- a/docs/VLSI/Building-A-Chip.rst +++ b/docs/VLSI/Building-A-Chip.rst @@ -10,7 +10,7 @@ Transforming the RTL -------------------- Building a chip requires specializing the generic verilog emitted by FIRRTL to adhere to the constraints imposed by the technology used for fabrication. -This includes mapping Chisel memories to available technology macros such as SRAMs, mapping the input and output of your chip to connect to technology IO cells, see :ref:`Tools/Barstools:Barstools`. +This includes mapping Chisel memories to available technology macros such as SRAMs, mapping the input and output of your chip to connect to technology IO cells, see :ref:`Tools/Tapeout-Tools:Tapeout-tools`. In addition to these required transformations, it may also be beneficial to transform the RTL to make it more amenable to hierarchical physical design easier. This often includes modifying the logical hierarchy to match the physical hierarchy through grouping components together or flattening components into a single larger module. diff --git a/fpga/Makefile b/fpga/Makefile index ebf55a97..1abb7f02 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -87,6 +87,8 @@ ifeq ($(SUB_PROJECT),arty100t) FPGA_BRAND ?= xilinx endif +export USE_CHISEL6=1 + include $(base_dir)/variables.mk # default variables to build the arty example diff --git a/fpga/fpga-shells b/fpga/fpga-shells index 6019bb35..474ad191 160000 --- a/fpga/fpga-shells +++ b/fpga/fpga-shells @@ -1 +1 @@ -Subproject commit 6019bb3508d12887b01765f3cad512c3282aeb70 +Subproject commit 474ad19113b89ed5679695b269acdb011b9b871a diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index 7f10b174..ccb26c7d 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -5,7 +5,6 @@ import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.debug._ import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase} import freechips.rocketchip.system._ import freechips.rocketchip.tile._ @@ -25,7 +24,6 @@ class WithArtyTweaks extends Config( new chipyard.harness.WithHarnessBinderClockFreqMHz(32) ++ new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++ - new chipyard.config.WithDTSTimebase(32000) ++ new chipyard.config.WithSystemBusFrequency(32) ++ new chipyard.config.WithFrontBusFrequency(32) ++ new chipyard.config.WithControlBusFrequency(32) ++ diff --git a/fpga/src/main/scala/arty/IOBinders.scala b/fpga/src/main/scala/arty/IOBinders.scala index eb3185f9..9be218db 100644 --- a/fpga/src/main/scala/arty/IOBinders.scala +++ b/fpga/src/main/scala/arty/IOBinders.scala @@ -1,7 +1,6 @@ package chipyard.fpga.arty import chisel3._ -import chisel3.experimental.{IO} import freechips.rocketchip.devices.debug.{HasPeripheryDebug} diff --git a/fpga/src/main/scala/vc707/TestHarness.scala b/fpga/src/main/scala/vc707/TestHarness.scala index 317dedf6..4b49ec6e 100644 --- a/fpga/src/main/scala/vc707/TestHarness.scala +++ b/fpga/src/main/scala/vc707/TestHarness.scala @@ -1,6 +1,5 @@ package chipyard.fpga.vc707 import chisel3._ -import chisel3.experimental.{IO} import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource} import org.chipsalliance.cde.config.{Parameters} diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index b707d144..ea9472b4 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -1,7 +1,6 @@ package chipyard.fpga.vcu118 import chisel3._ -import chisel3.experimental.{IO} import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource} import org.chipsalliance.cde.config.{Parameters} diff --git a/generators/bar-fetchers b/generators/bar-fetchers index 45380026..bd02692f 160000 --- a/generators/bar-fetchers +++ b/generators/bar-fetchers @@ -1 +1 @@ -Subproject commit 45380026ff2918613849c18008d0d9315e060426 +Subproject commit bd02692fe6cb5197df90dc39051d31369ef61fcd diff --git a/generators/chipyard/src/main/resources/vsrc/Analog.v b/generators/chipyard/src/main/resources/vsrc/Analog.v new file mode 100644 index 00000000..0a9abf03 --- /dev/null +++ b/generators/chipyard/src/main/resources/vsrc/Analog.v @@ -0,0 +1,11 @@ +// See LICENSE for license details + +`timescale 1ns/1ps + +module AnalogConst #(CONST, WIDTH) ( + output [WIDTH-1:0] io +); + + assign io = CONST; + +endmodule diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala index d80d71af..518afa7d 100644 --- a/generators/chipyard/src/main/scala/ChipTop.scala +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -10,7 +10,7 @@ import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleI import freechips.rocketchip.util.{DontTouch} import chipyard.iobinders._ -import barstools.iocell.chisel._ +import chipyard.iocell._ case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) => new DigitalTop()(p)) diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala index d67f99bd..6be276e2 100644 --- a/generators/chipyard/src/main/scala/System.scala +++ b/generators/chipyard/src/main/scala/System.scala @@ -80,9 +80,10 @@ trait CanHaveMasterTLMemPort { this: BaseSubsystem => } }).toList.flatten) + // disable inwards monitors from node since the class with this trait (i.e. DigitalTop) + // doesn't provide an implicit clock to those monitors mbus.coupleTo(s"memory_controller_port_named_$portName") { - (memTLNode - :*= TLBuffer() + (DisableMonitors { implicit p => memTLNode :*= TLBuffer() } :*= TLSourceShrinker(1 << idBits) :*= TLWidthWidget(mbus.beatBytes) :*= _) diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala index fdb2ec9e..d075fcbb 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala @@ -7,7 +7,7 @@ import freechips.rocketchip.prci._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ -import barstools.iocell.chisel._ +import chipyard.iocell._ // This uses the FakePLL, which uses a ClockAtFreq Verilog blackbox to generate // the requested clocks. This also adds TileLink ClockDivider and ClockSelector diff --git a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala index f2e12ec0..9de616ea 100644 --- a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala +++ b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala @@ -12,36 +12,6 @@ class LargeBoomAndRocketConfig extends Config( new chipyard.config.WithSystemBusWidth(128) ++ new chipyard.config.AbstractConfig) -// DOC include start: BoomAndRocketWithHwacha -class HwachaLargeBoomAndHwachaRocketConfig extends Config( - new chipyard.config.WithHwachaTest ++ - new hwacha.DefaultHwachaConfig ++ // add hwacha to all harts - new boom.v3.common.WithNLargeBooms(1) ++ // add 1 boom core - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket core - new chipyard.config.WithSystemBusWidth(128) ++ - new chipyard.config.AbstractConfig) -// DOC include end: BoomAndRocketWithHwacha - -class LargeBoomAndHwachaRocketConfig extends Config( - new chipyard.config.WithMultiRoCC ++ // support heterogeneous rocc - new chipyard.config.WithMultiRoCCHwacha(0) ++ // put hwacha on hart-0 (rocket) - new hwacha.DefaultHwachaConfig ++ // set default hwacha config keys - new boom.v3.common.WithNLargeBooms(1) ++ // add 1 boom core - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket core - new chipyard.config.WithSystemBusWidth(128) ++ - new chipyard.config.AbstractConfig) - -// DOC include start: DualBoomAndRocketOneHwacha -class DualLargeBoomAndHwachaRocketConfig extends Config( - new chipyard.config.WithMultiRoCC ++ // support heterogeneous rocc - new chipyard.config.WithMultiRoCCHwacha(0) ++ // put hwacha on hart-0 (rocket) - new hwacha.DefaultHwachaConfig ++ // set default hwacha config keys - new boom.v3.common.WithNLargeBooms(2) ++ // add 2 boom cores - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket core - new chipyard.config.WithSystemBusWidth(128) ++ - new chipyard.config.AbstractConfig) -// DOC include end: DualBoomAndRocketOneHwacha - class DualLargeBoomAndDualRocketConfig extends Config( new boom.v3.common.WithNLargeBooms(2) ++ // add 2 boom cores new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // add 2 rocket cores diff --git a/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala b/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala index 6647e516..23da9700 100644 --- a/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala +++ b/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala @@ -17,3 +17,9 @@ class NoCoresConfig extends Config( new chipyard.config.WithNoDebug ++ new chipyard.config.WithNoPLIC ++ new chipyard.config.AbstractConfig) + +// A config that uses a empty chiptop module with no rocket-chip soc components +class EmptyChipTopConfig extends Config( + new chipyard.example.WithEmptyChipTop ++ + new chipyard.config.AbstractConfig // since we aren't using rocket-chip, this doesn't do anything +) diff --git a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala index 32c5fe19..184afaa7 100644 --- a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala @@ -33,13 +33,6 @@ class LeanGemminiPrintfRocketConfig extends Config( new chipyard.config.WithSystemBusWidth(128) ++ new chipyard.config.AbstractConfig) -class HwachaRocketConfig extends Config( - new chipyard.config.WithHwachaTest ++ - new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new chipyard.config.WithSystemBusWidth(128) ++ - new chipyard.config.AbstractConfig) - class MempressRocketConfig extends Config( new mempress.WithMemPress ++ // use Mempress (memory traffic generation) accelerator new chipyard.config.WithExtMemIdBits(7) ++ // use 7 bits for tl like request id @@ -50,13 +43,6 @@ class MempressRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) -class HwachaLargeBoomV3Config extends Config( - new chipyard.config.WithHwachaTest ++ - new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator - new boom.v3.common.WithNLargeBooms(1) ++ - new chipyard.config.WithSystemBusWidth(128) ++ - new chipyard.config.AbstractConfig) - class AES256ECBRocketConfig extends Config( new aes.WithAES256ECBAccel ++ // use Caliptra AES 256 ECB accelerator new freechips.rocketchip.subsystem.WithNBigCores(1) ++ diff --git a/generators/chipyard/src/main/scala/config/RocketSha3Configs.scala b/generators/chipyard/src/main/scala/config/RocketSha3Configs.scala deleted file mode 100644 index 43ad1de3..00000000 --- a/generators/chipyard/src/main/scala/config/RocketSha3Configs.scala +++ /dev/null @@ -1,22 +0,0 @@ -package chipyard - -import org.chipsalliance.cde.config.{Config} -import freechips.rocketchip.diplomacy.{AsynchronousCrossing} - -// -------------- -// Rocket+SHA3 Configs -// These live in a separate file to simplify patching out for the tutorials. -// -------------- - -// DOC include start: Sha3Rocket -class Sha3RocketConfig extends Config( - new sha3.WithSha3Accel ++ // add SHA3 rocc accelerator - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new chipyard.config.AbstractConfig) -// DOC include end: Sha3Rocket - -class Sha3RocketPrintfConfig extends Config( - new sha3.WithSha3Printf ++ - new sha3.WithSha3Accel ++ // add SHA3 rocc accelerator - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala index 7225c800..dca2af03 100644 --- a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala @@ -12,10 +12,6 @@ import scala.collection.immutable.ListMap // For each of 4 phases, participants will customize and build a // small demonstration config. -// This file is designed to be used after running chipyard/scripts/tutorial-setup.sh, -// which removes the SHA3 accelerator RTL, and provides participants -// the experience of integrating external RTL. - // This file was originally developed for the cancelled ASPLOS-2020 // Chipyard tutorial. While the configs here work, the corresponding // slideware has not yet been created. @@ -54,26 +50,6 @@ class TutorialMMIOConfig extends Config( new chipyard.config.AbstractConfig ) -// Tutorial Phase 3: Integrate a SHA3 RoCC accelerator -class TutorialSha3Config extends Config( - // Uncomment this line once you added SHA3 to the build.sbt, and cloned the SHA3 repo - // new sha3.WithSha3Accel ++ - - // For this demonstration we assume the base system is a single-core Rocket, for fast elaboration - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new chipyard.config.AbstractConfig -) - -// Tutorial Phase 4: Integrate a Black-box verilog version of the SHA3 RoCC accelerator -class TutorialSha3BlackBoxConfig extends Config( - // Uncomment these lines once SHA3 is integrated - // new sha3.WithSha3BlackBox ++ // Specify we want the Black-box verilog version of Sha3 Ctrl - // new sha3.WithSha3Accel ++ - - // For this demonstration we assume the base system is a single-core Rocket, for fast elaboration - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new chipyard.config.AbstractConfig -) // Tutorial Phase 5: Map a multicore heterogeneous SoC with multiple cores and memory-mapped accelerators class TutorialNoCConfig extends Config( diff --git a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala index 8cf6ae67..83a42146 100644 --- a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala @@ -89,9 +89,12 @@ class WithFbusToSbusCrossingType(xType: ClockCrossingType) extends Config((site, * Mixins to set the dtsFrequency field of BusParams -- these will percolate its way * up the diplomatic graph to the clock sources. */ -class WithPeripheryBusFrequency(freqMHz: Double) extends Config((site, here, up) => { - case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) -}) +class WithPeripheryBusFrequency(freqMHz: Double) extends Config( + new freechips.rocketchip.subsystem.WithTimebase((freqMHz * 1e3).toLong) ++ // Match DTS timebase to PBUS (i.e. RTC) frequency. Makes RTC 'tick' at the PBUS rate. + new Config((site, here, up) => { + case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) + }) +) class WithMemoryBusFrequency(freqMHz: Double) extends Config((site, here, up) => { case MemoryBusKey => up(MemoryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) }) diff --git a/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala b/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala index c9f7fcdb..5ef76b75 100644 --- a/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala @@ -6,7 +6,6 @@ import org.chipsalliance.cde.config.{Field, Parameters, Config} import freechips.rocketchip.tile._ import freechips.rocketchip.diplomacy._ -import hwacha.{Hwacha} import gemmini._ import chipyard.{TestSuitesKey, TestSuiteHelper} @@ -34,47 +33,6 @@ class WithMultiRoCCFromBuildRoCC(harts: Int*) extends Config((site, here, up) => } }) -/** - * Config fragment to add Hwachas to cores based on hart - * - * For ex: - * Core 0, 1, 2, 3 have been defined earlier - * with tileIds of 0, 1, 2, 3 respectively - * And you call WithMultiRoCCHwacha(0,1) - * Then Core 0 and 1 will get a Hwacha - * - * @param harts harts to specify which will get a Hwacha - */ -class WithMultiRoCCHwacha(harts: Int*) extends Config( - new chipyard.config.WithHwachaTest ++ - new Config((site, here, up) => { - case MultiRoCCKey => { - up(MultiRoCCKey, site) ++ harts.distinct.map{ i => - (i -> Seq((p: Parameters) => { - val hwacha = LazyModule(new Hwacha()(p)) - hwacha - })) - } - } - }) -) - -class WithHwachaTest extends Config((site, here, up) => { - case TestSuitesKey => (tileParams: Seq[TileParams], suiteHelper: TestSuiteHelper, p: Parameters) => { - up(TestSuitesKey).apply(tileParams, suiteHelper, p) - import hwacha.HwachaTestSuites._ - suiteHelper.addSuites(rv64uv.map(_("p"))) - suiteHelper.addSuites(rv64uv.map(_("vp"))) - suiteHelper.addSuite(rv64sv("p")) - suiteHelper.addSuite(hwachaBmarks) - "SRC_EXTENSION = $(base_dir)/hwacha/$(src_path)/*.scala" + "\nDISASM_EXTENSION = --extension=hwacha" - } -}) - -/** - * The MultiRoCCGemmini fragment functions similarly to the - * WithMultiRoCCHwacha fragment defined above - */ class WithMultiRoCCGemmini[T <: Data : Arithmetic, U <: Data, V <: Data]( harts: Int*)(gemminiConfig: GemminiArrayConfig[T,U,V] = GemminiConfigs.defaultConfig) extends Config((site, here, up) => { case MultiRoCCKey => up(MultiRoCCKey, site) ++ harts.distinct.map { i => diff --git a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala index b4971cba..8e16b26c 100644 --- a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala @@ -18,10 +18,6 @@ class WithSystemBusWidth(bitWidth: Int) extends Config((site, here, up) => { case SystemBusKey => up(SystemBusKey, site).copy(beatBytes=bitWidth/8) }) -class WithDTSTimebase(freqMHz: BigInt) extends Config((site, here, up) => { - case DTSTimebase => freqMHz -}) - // Adds buffers on the interior of the inclusive LLC, to improve PD class WithInclusiveCacheInteriorBuffer(buffer: InclusiveCachePortParameters = InclusiveCachePortParameters.full) extends Config((site, here, up) => { case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerInterior=buffer, bufOuterInterior=buffer) diff --git a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala index c9493e78..b61b99f3 100644 --- a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala @@ -131,3 +131,8 @@ class WithRocketBoundaryBuffers(buffers: Option[RocketTileBoundaryBufferParams] class WithSV48IfPossible extends Config((site, here, up) => { case PgLevels => if (site(XLen) == 64) 4 /* Sv48 */ else up(PgLevels) }) + +// Uses SV39 if possible, otherwise default to the Rocket Chip core default +class WithSV39 extends Config((site, here, up) => { + case PgLevels => { require(site(XLen) == 64); 3; } +}) diff --git a/generators/chipyard/src/main/scala/example/CustomChipTop.scala b/generators/chipyard/src/main/scala/example/CustomChipTop.scala index eb0565ce..5958d1b2 100644 --- a/generators/chipyard/src/main/scala/example/CustomChipTop.scala +++ b/generators/chipyard/src/main/scala/example/CustomChipTop.scala @@ -6,7 +6,7 @@ import chipyard.iobinders._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy.{InModuleBody} import freechips.rocketchip.subsystem.{PBUS, HasTileLinkLocations} -import barstools.iocell.chisel._ +import chipyard.iocell._ import chipyard._ import chipyard.harness.{BuildTop} import sifive.blocks.devices.uart._ diff --git a/generators/chipyard/src/main/scala/example/EmptyChipTop.scala b/generators/chipyard/src/main/scala/example/EmptyChipTop.scala new file mode 100644 index 00000000..e2bb3f8c --- /dev/null +++ b/generators/chipyard/src/main/scala/example/EmptyChipTop.scala @@ -0,0 +1,21 @@ +package chipyard.example + +import chisel3._ + +import org.chipsalliance.cde.config._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.util.{DontTouch} + +import chipyard._ +import chipyard.harness.{BuildTop} + +class EmptyChipTop(implicit p: Parameters) extends LazyModule { + override lazy val module = new Impl + class Impl extends LazyRawModuleImp(this) with DontTouch { + // Your custom non-rocketchip-soc stuff here + } +} + +class WithEmptyChipTop extends Config((site, here, up) => { + case BuildTop => (p: Parameters) => new EmptyChipTop()(p) +}) diff --git a/generators/chipyard/src/main/scala/example/FlatChipTop.scala b/generators/chipyard/src/main/scala/example/FlatChipTop.scala index 6b249286..d8f659f4 100644 --- a/generators/chipyard/src/main/scala/example/FlatChipTop.scala +++ b/generators/chipyard/src/main/scala/example/FlatChipTop.scala @@ -13,7 +13,7 @@ import chipyard.{BuildSystem, DigitalTop} import chipyard.harness.{BuildTop} import chipyard.clocking._ import chipyard.iobinders._ -import barstools.iocell.chisel._ +import chipyard.iocell._ import testchipip.serdes.{SerialTLKey} class WithFlatChipTop extends Config((site, here, up) => { diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala index 4cc1b2af..866496e7 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala @@ -12,7 +12,7 @@ import freechips.rocketchip.subsystem._ import freechips.rocketchip.util._ import freechips.rocketchip.jtag.{JTAGIO} import freechips.rocketchip.devices.debug.{SimJTAG} -import barstools.iocell.chisel._ +import chipyard.iocell._ import testchipip.dram.{SimDRAM} import testchipip.tsi.{SimTSI, SerialRAM, TSI, TSIIO} import testchipip.soc.{TestchipSimDTM} diff --git a/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala b/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala index b8674623..1cb1e87d 100644 --- a/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala +++ b/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala @@ -99,6 +99,7 @@ trait HasHarnessInstantiators { if (p(DontTouchChipTopPorts)) { duts.map(_ match { case d: DontTouch => d.dontTouchPorts() + case _ => }) } diff --git a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala index 55ff4191..4657f9fa 100644 --- a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala @@ -30,30 +30,29 @@ object ApplyMultiHarnessBinders { } } -class MultiHarnessBinder[T <: Port[_], S <: HasHarnessInstantiators]( +class MultiHarnessBinder[T <: Port[_], U <: Port[_], S <: HasHarnessInstantiators]( chip0: Int, chip1: Int, - chip0portFn: T => Boolean, chip1portFn: T => Boolean, - connectFn: (S, T, T) => Unit -)(implicit tag0: ClassTag[T], tag1: ClassTag[S]) extends Config((site, here, up) => { + chip0portFn: T => Boolean, chip1portFn: U => Boolean, + connectFn: (S, T, U) => Unit +)(implicit tag0: ClassTag[T], tag1: ClassTag[U], tag2: ClassTag[S]) extends Config((site, here, up) => { // Override any HarnessBinders for chip0/chip1 case MultiChipParameters(`chip0`) => new Config( new HarnessBinder({case (th: S, port: T, chipId: Int) if chip0portFn(port) => }) ++ up(MultiChipParameters(chip0)) ) case MultiChipParameters(`chip1`) => new Config( - new HarnessBinder({case (th: S, port: T, chipId: Int) if chip1portFn(port) => }) ++ up(MultiChipParameters(chip1)) + new HarnessBinder({case (th: S, port: U, chipId: Int) if chip1portFn(port) => }) ++ up(MultiChipParameters(chip1)) ) // Set the multiharnessbinder key case MultiHarnessBinders(`chip0`, `chip1`) => up(MultiHarnessBinders(chip0, chip1)) :+ { ((th: S, chip0Ports: Seq[Port[_]], chip1Ports: Seq[Port[_]]) => { val chip0Port: Seq[T] = chip0Ports.collect { case (p: T) if chip0portFn(p) => p } - val chip1Port: Seq[T] = chip1Ports.collect { case (p: T) if chip1portFn(p) => p } + val chip1Port: Seq[U] = chip1Ports.collect { case (p: U) if chip1portFn(p) => p } require(chip0Port.size == 1 && chip1Port.size == 1) connectFn(th, chip0Port(0), chip1Port(0)) }) } }) - class WithMultiChipSerialTL(chip0: Int, chip1: Int, chip0portId: Int = 0, chip1portId: Int = 0) extends MultiHarnessBinder( chip0, chip1, (p0: SerialTLPort) => p0.portId == chip0portId, diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala index 4b1eb640..a987d1ab 100644 --- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala +++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala @@ -27,7 +27,7 @@ import sifive.blocks.devices.spi._ import sifive.blocks.devices.i2c._ import tracegen.{TraceGenSystemModuleImp} -import barstools.iocell.chisel._ +import chipyard.iocell._ import testchipip.serdes.{CanHavePeripheryTLSerial, SerialTLKey} import testchipip.spi.{SPIChipIO} diff --git a/generators/chipyard/src/main/scala/iocell/Analog.scala b/generators/chipyard/src/main/scala/iocell/Analog.scala new file mode 100644 index 00000000..78e1cfe7 --- /dev/null +++ b/generators/chipyard/src/main/scala/iocell/Analog.scala @@ -0,0 +1,18 @@ +// See LICENSE for license details + +package chipyard.iocell + +import chisel3._ +import chisel3.util.{HasBlackBoxResource} +import chisel3.experimental.{Analog, IntParam} + +class AnalogConst(value: Int, width: Int = 1) + extends BlackBox(Map("CONST" -> IntParam(value), "WIDTH" -> IntParam(width))) + with HasBlackBoxResource { + val io = IO(new Bundle { val io = Analog(width.W) }) + addResource("/vsrc/Analog.v") +} + +object AnalogConst { + def apply(value: Int, width: Int = 1) = Module(new AnalogConst(value, width)).io.io +} diff --git a/generators/chipyard/src/main/scala/iocell/IOCell.scala b/generators/chipyard/src/main/scala/iocell/IOCell.scala new file mode 100644 index 00000000..5f0129b8 --- /dev/null +++ b/generators/chipyard/src/main/scala/iocell/IOCell.scala @@ -0,0 +1,338 @@ +// See LICENSE for license details + +package chipyard.iocell + +import chisel3._ +import chisel3.util.{Cat, HasBlackBoxInline} +import chisel3.reflect.DataMirror +import chisel3.experimental.{Analog, BaseModule} + +// The following four IO cell bundle types are bare-minimum functional connections +// for modeling 4 different IO cell scenarios. The intention is that the user +// would create wrapper modules that extend these interfaces with additional +// control signals. These are loosely similar to the sifive-blocks PinCtrl bundles +// (https://github.com/sifive/sifive-blocks/blob/master/src/main/scala/devices/pinctrl/PinCtrl.scala), +// but we want to avoid a dependency on an external libraries. + +/** The base IO bundle for an analog signal (typically something with no digital buffers inside) + * pad: off-chip (external) connection + * core: internal connection + */ +class AnalogIOCellBundle extends Bundle { + val pad = Analog(1.W) // Pad/bump signal (off-chip) + val core = Analog(1.W) // core signal (on-chip) +} + +/** The base IO bundle for a signal with runtime-controllable direction + * pad: off-chip (external) connection + * i: input to chip logic (output from IO cell) + * ie: enable signal for i + * o: output from chip logic (input to IO cell) + * oe: enable signal for o + */ +class DigitalGPIOCellBundle extends Bundle { + val pad = Analog(1.W) + val i = Output(Bool()) + val ie = Input(Bool()) + val o = Input(Bool()) + val oe = Input(Bool()) +} + +/** The base IO bundle for a digital output signal + * pad: off-chip (external) connection + * o: output from chip logic (input to IO cell) + * oe: enable signal for o + */ +class DigitalOutIOCellBundle extends Bundle { + val pad = Output(Bool()) + val o = Input(Bool()) + val oe = Input(Bool()) +} + +/** The base IO bundle for a digital input signal + * pad: off-chip (external) connection + * i: input to chip logic (output from IO cell) + * ie: enable signal for i + */ +class DigitalInIOCellBundle extends Bundle { + val pad = Input(Bool()) + val i = Output(Bool()) + val ie = Input(Bool()) +} + +trait IOCell extends BaseModule { + var iocell_name: Option[String] = None + + /** Set IOCell name + * @param s Proposed name for the IOCell + * + * @return An inherited IOCell with given the proposed name + */ + def suggestName(s: String): this.type = { + iocell_name = Some(s) + super.suggestName(s) + } +} + +trait AnalogIOCell extends IOCell { + val io: AnalogIOCellBundle +} + +trait DigitalGPIOCell extends IOCell { + val io: DigitalGPIOCellBundle +} + +trait DigitalInIOCell extends IOCell { + val io: DigitalInIOCellBundle +} + +trait DigitalOutIOCell extends IOCell { + val io: DigitalOutIOCellBundle +} + +// The following Generic IO cell black boxes have verilog models that mimic a very simple +// implementation of an IO cell. For building a real chip, it is important to implement +// and use similar classes which wrap the foundry-specific IO cells. + +abstract class GenericIOCell extends BlackBox with HasBlackBoxInline { + val impl: String + val moduleName = this.getClass.getSimpleName + setInline(s"$moduleName.v", impl); +} + +class GenericAnalogIOCell extends GenericIOCell with AnalogIOCell { + val io = IO(new AnalogIOCellBundle) + lazy val impl = s""" +`timescale 1ns/1ps +module GenericAnalogIOCell( + inout pad, + inout core +); + + assign core = 1'bz; + assign pad = core; + +endmodule""" +} + +class GenericDigitalGPIOCell extends GenericIOCell with DigitalGPIOCell { + val io = IO(new DigitalGPIOCellBundle) + lazy val impl = s""" +`timescale 1ns/1ps +module GenericDigitalGPIOCell( + inout pad, + output i, + input ie, + input o, + input oe +); + + assign pad = oe ? o : 1'bz; + assign i = ie ? pad : 1'b0; + +endmodule""" +} + +class GenericDigitalInIOCell extends GenericIOCell with DigitalInIOCell { + val io = IO(new DigitalInIOCellBundle) + lazy val impl = s""" +`timescale 1ns/1ps +module GenericDigitalInIOCell( + input pad, + output i, + input ie +); + + assign i = ie ? pad : 1'b0; + +endmodule""" +} + +class GenericDigitalOutIOCell extends GenericIOCell with DigitalOutIOCell { + val io = IO(new DigitalOutIOCellBundle) + lazy val impl = s""" +`timescale 1ns/1ps +module GenericDigitalOutIOCell( + output pad, + input o, + input oe +); + + assign pad = oe ? o : 1'bz; + +endmodule""" +} + +trait IOCellTypeParams { + def analog(): AnalogIOCell + def gpio(): DigitalGPIOCell + def input(): DigitalInIOCell + def output(): DigitalOutIOCell +} + +case class GenericIOCellParams() extends IOCellTypeParams { + def analog() = Module(new GenericAnalogIOCell) + def gpio() = Module(new GenericDigitalGPIOCell) + def input() = Module(new GenericDigitalInIOCell) + def output() = Module(new GenericDigitalOutIOCell) +} + +object IOCell { + + /** From within a RawModule or MultiIOModule context, generate new module IOs from a given + * signal and return the new IO and a Seq containing all generated IO cells. + * @param coreSignal The signal onto which to add IO cells + * @param name An optional name or name prefix to use for naming IO cells + * @param abstractResetAsAsync When set, will coerce abstract resets to + * AsyncReset, and otherwise to Bool (sync reset) + * @return A tuple of (the generated IO data node, a Seq of all generated IO cell instances) + */ + def generateIOFromSignal[T <: Data]( + coreSignal: T, + name: String, + typeParams: IOCellTypeParams = GenericIOCellParams(), + abstractResetAsAsync: Boolean = false + ): (T, Seq[IOCell]) = { + val padSignal = IO(DataMirror.internal.chiselTypeClone[T](coreSignal)).suggestName(name) + val resetFn = if (abstractResetAsAsync) toAsyncReset else toSyncReset + val iocells = IOCell.generateFromSignal(coreSignal, padSignal, Some(s"iocell_$name"), typeParams, resetFn) + (padSignal, iocells) + } + + /** Connect two identical signals together by adding IO cells between them and return a Seq + * containing all generated IO cells. + * @param coreSignal The core-side (internal) signal onto which to connect/add IO cells + * @param padSignal The pad-side (external) signal onto which to connect IO cells + * @param name An optional name or name prefix to use for naming IO cells + * @return A Seq of all generated IO cell instances + */ + val toSyncReset: (Reset) => Bool = _.asBool + val toAsyncReset: (Reset) => AsyncReset = _.asAsyncReset + def generateFromSignal[T <: Data, R <: Reset]( + coreSignal: T, + padSignal: T, + name: Option[String] = None, + typeParams: IOCellTypeParams = GenericIOCellParams(), + concretizeResetFn: (Reset) => R = toSyncReset + ): Seq[IOCell] = { + def genCell[T <: Data]( + castToBool: (T) => Bool, + castFromBool: (Bool) => T + )(coreSignal: T, + padSignal: T + ): Seq[IOCell] = { + DataMirror.directionOf(coreSignal) match { + case ActualDirection.Input => { + val iocell = typeParams.input() + name.foreach(n => { + iocell.suggestName(n) + }) + coreSignal := castFromBool(iocell.io.i) + iocell.io.ie := true.B + iocell.io.pad := castToBool(padSignal) + Seq(iocell) + } + case ActualDirection.Output => { + val iocell = typeParams.output() + name.foreach(n => { + iocell.suggestName(n) + }) + iocell.io.o := castToBool(coreSignal) + iocell.io.oe := true.B + padSignal := castFromBool(iocell.io.pad) + Seq(iocell) + } + case _ => throw new Exception(s"Signal does not have a direction and cannot be matched to an IOCell") + } + } + def genCellForClock = genCell[Clock](_.asUInt.asBool, _.asClock) _ + def genCellForAsyncReset = genCell[AsyncReset](_.asBool, _.asAsyncReset) _ + def genCellForAbstractReset = genCell[Reset](_.asBool, concretizeResetFn) _ + + (coreSignal, padSignal) match { + case (coreSignal: Analog, padSignal: Analog) => { + if (coreSignal.getWidth == 0) { + Seq() + } else { + require( + coreSignal.getWidth == 1, + "Analogs wider than 1 bit are not supported because we can't bit-select Analogs (https://github.com/freechipsproject/chisel3/issues/536)" + ) + val iocell = typeParams.analog() + name.foreach(n => iocell.suggestName(n)) + iocell.io.core <> coreSignal + padSignal <> iocell.io.pad + Seq(iocell) + } + } + case (coreSignal: Clock, padSignal: Clock) => genCellForClock(coreSignal, padSignal) + case (coreSignal: AsyncReset, padSignal: AsyncReset) => genCellForAsyncReset(coreSignal, padSignal) + case (coreSignal: Bits, padSignal: Bits) => { + require(padSignal.getWidth == coreSignal.getWidth, "padSignal and coreSignal must be the same width") + if (padSignal.getWidth == 0) { + // This dummy assignment will prevent invalid firrtl from being emitted + DataMirror.directionOf(coreSignal) match { + case ActualDirection.Input => coreSignal := 0.U + case _ => {} + } + Seq() + } else { + DataMirror.directionOf(coreSignal) match { + case ActualDirection.Input => { + val iocells = padSignal.asBools.zipWithIndex.map { case (sig, i) => + val iocell = typeParams.input() + // Note that we are relying on chisel deterministically naming this in the index order (which it does) + // This has the side-effect of naming index 0 with no _0 suffix, which is how chisel names other signals + // An alternative solution would be to suggestName(n + "_" + i) + name.foreach(n => { + iocell.suggestName(n) + }) + iocell.io.pad := sig + iocell.io.ie := true.B + iocell + } + // Note that the reverse here is because Cat(Seq(a,b,c,d)) yields abcd, but a is index 0 of the Seq + coreSignal := Cat(iocells.map(_.io.i).reverse) + iocells + } + case ActualDirection.Output => { + val iocells = coreSignal.asBools.zipWithIndex.map { case (sig, i) => + val iocell = typeParams.output() + // Note that we are relying on chisel deterministically naming this in the index order (which it does) + // This has the side-effect of naming index 0 with no _0 suffix, which is how chisel names other signals + // An alternative solution would be to suggestName(n + "_" + i) + name.foreach(n => { + iocell.suggestName(n) + }) + iocell.io.o := sig + iocell.io.oe := true.B + iocell + } + // Note that the reverse here is because Cat(Seq(a,b,c,d)) yields abcd, but a is index 0 of the Seq + padSignal := Cat(iocells.map(_.io.pad).reverse) + iocells + } + case _ => throw new Exception("Bits signal does not have a direction and cannot be matched to IOCell(s)") + } + } + } + case (coreSignal: Reset, padSignal: Reset) => genCellForAbstractReset(coreSignal, padSignal) + case (coreSignal: Vec[_], padSignal: Vec[_]) => { + require(padSignal.size == coreSignal.size, "size of Vec for padSignal and coreSignal must be the same") + coreSignal.zip(padSignal).zipWithIndex.foldLeft(Seq.empty[IOCell]) { case (total, ((core, pad), i)) => + val ios = IOCell.generateFromSignal(core, pad, name.map(_ + "_" + i), typeParams) + total ++ ios + } + } + case (coreSignal: Record, padSignal: Record) => { + coreSignal.elements.foldLeft(Seq.empty[IOCell]) { case (total, (eltName, core)) => + val pad = padSignal.elements(eltName) + val ios = IOCell.generateFromSignal(core, pad, name.map(_ + "_" + eltName), typeParams) + total ++ ios + } + } + case _ => { throw new Exception("Oops, I don't know how to handle this signal.") } + } + } + +} diff --git a/generators/diplomacy b/generators/diplomacy index edf37530..055be698 160000 --- a/generators/diplomacy +++ b/generators/diplomacy @@ -1 +1 @@ -Subproject commit edf375300d99a4c260a214d7c1553de0040771d7 +Subproject commit 055be698f4ad55bf4a90b3d5e31d4344be5f788b diff --git a/generators/fft-generator b/generators/fft-generator index 490b975d..6a6413b5 160000 --- a/generators/fft-generator +++ b/generators/fft-generator @@ -1 +1 @@ -Subproject commit 490b975d36f49632f05c29dd22bcd6e5f0e703ab +Subproject commit 6a6413b526dfdd9150656f235ae75525238b4719 diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 55089358..48ea9bb3 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -26,7 +26,7 @@ import firesim.configs.MemModelKey import tracegen.{TraceGenSystemModuleImp} import cva6.CVA6Tile -import barstools.iocell.chisel._ +import chipyard.iocell._ import chipyard.iobinders._ import chipyard._ import chipyard.harness._ diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index f36fea47..5934f8c2 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -367,3 +367,11 @@ class FireSimRadianceClusterSynConfig extends Config( new WithDefaultMemModel ++ new WithFireSimConfigTweaks ++ new chipyard.RadianceClusterSynConfig) + +class FireSimLargeBoomSV39CospikeConfig extends Config( + new firesim.firesim.WithCospikeBridge ++ + new WithDefaultFireSimBridges ++ + new WithDefaultMemModel ++ + new WithFireSimConfigTweaks++ + new chipyard.config.WithSV39 ++ + new chipyard.LargeBoomV3Config) diff --git a/generators/gemmini b/generators/gemmini index 5bcbead0..8a9c4239 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 5bcbead0ad5a5a4c0f162f083fb010fbf0b7486a +Subproject commit 8a9c423900766ea59efefd4ce51e40cd242555b4 diff --git a/generators/hwacha b/generators/hwacha deleted file mode 160000 index bf799dc4..00000000 --- a/generators/hwacha +++ /dev/null @@ -1 +0,0 @@ -Subproject commit bf799dc48293cb5017ed2ec22c5023de8d461184 diff --git a/generators/ibex b/generators/ibex index c2174aba..89c19c2d 160000 --- a/generators/ibex +++ b/generators/ibex @@ -1 +1 @@ -Subproject commit c2174aba4fb304c7565c248f2a673f7151be896b +Subproject commit 89c19c2d7bc2523a0d9fb85e154bcaf2c1cc7665 diff --git a/generators/icenet b/generators/icenet index ab30e23e..969bc8f9 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit ab30e23e8e1fdd0777a7e4eb82bb40e2657cfcd3 +Subproject commit 969bc8f9a00e4b11d243656f255761e04e10ccb9 diff --git a/generators/mempress b/generators/mempress index 415f55b5..0b362f90 160000 --- a/generators/mempress +++ b/generators/mempress @@ -1 +1 @@ -Subproject commit 415f55b583f3527500c5cf4e0a7b663982479098 +Subproject commit 0b362f9031a50b5af24d9d9606b8bbddd5bbc00c diff --git a/generators/riscv-sodor b/generators/riscv-sodor index bbfc3c35..ca043149 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit bbfc3c35100329386314c49b62b49a7f42f65e87 +Subproject commit ca0431493ec35983388cb08bb203d5e12e9a32b2 diff --git a/generators/rocket-chip b/generators/rocket-chip index 8c8b3f5d..cf654499 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 8c8b3f5dcf8cdc0166a030c75aa50c12578d5745 +Subproject commit cf654499abf9a616cad5a235a5973d826f5ea18e diff --git a/generators/rocket-chip-inclusive-cache b/generators/rocket-chip-inclusive-cache index 1332d226..45d184f2 160000 --- a/generators/rocket-chip-inclusive-cache +++ b/generators/rocket-chip-inclusive-cache @@ -1 +1 @@ -Subproject commit 1332d2268ae01b2b311966d53a3ee0d930e83f07 +Subproject commit 45d184f2fd1e2189d6302468e208a054b681caab diff --git a/generators/sha3 b/generators/sha3 deleted file mode 160000 index 2d38585d..00000000 --- a/generators/sha3 +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 2d38585d6410ca51ab19040fc23b1f6b3465270c diff --git a/scripts/build-setup.sh b/scripts/build-setup.sh index 56f56506..1879c9ae 100755 --- a/scripts/build-setup.sh +++ b/scripts/build-setup.sh @@ -12,11 +12,10 @@ source $CYDIR/scripts/utils.sh common_setup usage() { - echo "Usage: ${0} [OPTIONS] [riscv-tools | esp-tools]" + echo "Usage: ${0} [OPTIONS] [riscv-tools]" echo "" echo "Installation Types" echo " riscv-tools: if set, builds the riscv toolchain (this is also the default)" - echo " esp-tools: if set, builds esp-tools toolchain used for the hwacha vector accelerator" echo "" echo "Helper script to fully initialize repository that wraps other scripts." echo "By default it initializes/installs things in the following order:" @@ -69,7 +68,7 @@ do case $1 in -h | --help ) usage 3 ;; - riscv-tools | esp-tools) + riscv-tools ) TOOLCHAIN_TYPE=$1 ;; --verbose | -v) VERBOSE_FLAG=$1 @@ -119,29 +118,6 @@ run_step() { { -# esp-tools should ONLY be used for hwacha. -# Check for this, since many users will be attempting to use this with gemmini -if [ $TOOLCHAIN_TYPE == "esp-tools" ]; then - while true; do - printf '\033[2J' - read -p "WARNING: You are trying to install the esp-tools toolchain."$'\n'"This should ONLY be used for Hwacha development."$'\n'"Gemmini should be used with riscv-tools."$'\n'"Type \"y\" to continue if this is intended, or \"n\" if not: " validate - case "$validate" in - y | Y) - echo "Installing esp-tools." - break - ;; - n | N) - error "Rerun with riscv-tools" - exit 3 - ;; - *) - error "Invalid response. Please type \"y\" or \"n\"" - ;; - esac - done -fi - - ####################################### ###### BEGIN STEP-BY-STEP SETUP ####### ####################################### @@ -271,7 +247,8 @@ if run_step "6"; then echo $CYDIR source sourceme-manager.sh --skip-ssh-setup pushd sim - make sbt SBT_COMMAND="project {file:$CYDIR}firechip; compile" TARGET_PROJECT=firesim + make target-classpath + make firesim-main-classpath popd ) exit_if_last_command_failed diff --git a/scripts/build-toolchain-extra.sh b/scripts/build-toolchain-extra.sh index 4e7b29c6..24b024bc 100755 --- a/scripts/build-toolchain-extra.sh +++ b/scripts/build-toolchain-extra.sh @@ -16,11 +16,10 @@ common_setup readonly MAKE usage() { - echo "usage: ${0} [OPTIONS] [riscv-tools | esp-tools]" + echo "usage: ${0} [OPTIONS] [riscv-tools]" echo "" echo "Installation Types" echo " riscv-tools: if set, builds the riscv toolchain (this is also the default)" - echo " esp-tools: if set, builds esp-tools toolchain used for the hwacha vector accelerator" echo "" echo "Options" echo " --prefix -p PREFIX : Install destination." @@ -45,7 +44,7 @@ do RISCV=$(realpath $1) ;; --clean-after-install ) CLEANAFTERINSTALL="true" ;; - riscv-tools | esp-tools) + riscv-tools ) TOOLCHAIN=$1 ;; * ) error "invalid option $1" diff --git a/scripts/generate-conda-lockfiles.sh b/scripts/generate-conda-lockfiles.sh index b0a8983f..2d4a2e8d 100755 --- a/scripts/generate-conda-lockfiles.sh +++ b/scripts/generate-conda-lockfiles.sh @@ -10,7 +10,7 @@ if [ ! -d "$REQS_DIR" ]; then exit 1 fi -for TOOLCHAIN_TYPE in riscv-tools esp-tools; do +for TOOLCHAIN_TYPE in riscv-tools; do # note: lock file must end in .conda-lock.yml - see https://github.com/conda-incubator/conda-lock/issues/154 LOCKFILE=$REQS_DIR/conda-lock-reqs/conda-requirements-$TOOLCHAIN_TYPE-linux-64.conda-lock.yml rm -rf $LOCKFILE diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index e46af0ca..c81c95f1 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -72,7 +72,6 @@ cd "$RDIR" generators/cva6 \ generators/nvdla \ toolchains/libgloss \ - generators/sha3 \ generators/gemmini \ generators/rocket-chip \ sims/firesim \ @@ -101,9 +100,6 @@ cd "$RDIR" ) ( - # Non-recursive clone to exclude riscv-linux - git submodule update --init generators/sha3 - # Non-recursive clone to exclude cva6 submods git submodule update --init generators/cva6 git -C generators/cva6 submodule update --init src/main/resources/cva6/vsrc/cva6 diff --git a/scripts/repo-clean.sh b/scripts/repo-clean.sh index c966f265..fef00bc5 100755 --- a/scripts/repo-clean.sh +++ b/scripts/repo-clean.sh @@ -9,9 +9,6 @@ rm -rf $RDIR/toolchains/libgloss/build.log rm -rf $RDIR/toolchains/riscv-tools/riscv-isa-sim/build.log rm -rf $RDIR/toolchains/riscv-tools/riscv-pk/build.log rm -rf $RDIR/toolchains/riscv-tools/riscv-tests/build.log -rm -rf $RDIR/toolchains/esp-tools/riscv-isa-sim/build.log -rm -rf $RDIR/toolchains/esp-tools/riscv-pk/build.log -rm -rf $RDIR/toolchains/esp-tools/riscv-tests/build.log ( pushd $RDIR/generators/constellation if [ -d espresso ] diff --git a/scripts/split-mems-conf.py b/scripts/split-mems-conf.py index 351bb7b2..086aa450 100755 --- a/scripts/split-mems-conf.py +++ b/scripts/split-mems-conf.py @@ -70,7 +70,10 @@ if __name__ == "__main__": imhj_data = json.load(imhj) dut_root = bfs_find_root(imhj_data, args.dut_module_name) - dut_submodules = bfs_collect_submodules(dut_root) + if dut_root: + dut_submodules = bfs_collect_submodules(dut_root) + else: + dut_submodules = set() model_root = bfs_find_root(imhj_data, args.model_module_name) model_submodules = bfs_collect_submodules(model_root) diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch deleted file mode 100644 index b64d7a43..00000000 --- a/scripts/tutorial-patches/build.sbt.patch +++ /dev/null @@ -1,28 +0,0 @@ -diff --git a/build.sbt b/build.sbt -index c3be6161..2a6d7160 100644 ---- a/build.sbt -+++ b/build.sbt -@@ -147,7 +147,7 @@ lazy val testchipip = (project in file("generators/testchipip")) - - lazy val chipyard = (project in file("generators/chipyard")) - .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, iocell, -- sha3, // On separate line to allow for cleaner tutorial-setup patches -+ //sha3, // On separate line to allow for cleaner tutorial-setup patches - dsptools, rocket_dsp_utils, - gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator, - constellation, mempress, barf, shuttle, caliptra_aes) -@@ -219,10 +219,10 @@ lazy val sodor = (project in file("generators/riscv-sodor")) - .settings(libraryDependencies ++= rocketLibDeps.value) - .settings(commonSettings) - --lazy val sha3 = (project in file("generators/sha3")) -- .dependsOn(rocketchip, midasTargetUtils) -- .settings(libraryDependencies ++= rocketLibDeps.value) -- .settings(commonSettings) -+// lazy val sha3 = (project in file("generators/sha3")) -+// .dependsOn(rocketchip, midasTargetUtils) -+// .settings(libraryDependencies ++= rocketLibDeps.value) -+// .settings(commonSettings) - - lazy val gemmini = (project in file("generators/gemmini")) - .dependsOn(rocketchip) diff --git a/scripts/tutorial-setup.sh b/scripts/tutorial-setup.sh deleted file mode 100755 index 080043f5..00000000 --- a/scripts/tutorial-setup.sh +++ /dev/null @@ -1,16 +0,0 @@ -#!/bin/bash - -set -ex - -RDIR=$(git rev-parse --show-toplevel) - -cd $RDIR - -git rm generators/chipyard/src/main/scala/config/RocketSha3Configs.scala -git rm -rf generators/sha3 - -for p in scripts/tutorial-patches/*.patch -do - echo "Applying tutorial patch $p" - git apply $p -done diff --git a/sims/common-sim-flags.mk b/sims/common-sim-flags.mk index 2b56e989..dd5130c4 100644 --- a/sims/common-sim-flags.mk +++ b/sims/common-sim-flags.mk @@ -2,17 +2,9 @@ # common gcc configuration/optimization #---------------------------------------------------------------------------------------- SIM_OPT_CXXFLAGS := -O3 - -# Workaround: esp-isa-sim doesn't install libriscv, -# so don't link with libriscv if it doesn't exist -# potentially breaks some configs - -ifeq (,$(wildcard $(RISCV)/lib/libriscv.so)) -$(warning libriscv not found) -LRISCV= -else LRISCV=-lriscv -endif + +export USE_CHISEL6=1 SIM_CXXFLAGS = \ $(CXXFLAGS) \ diff --git a/sims/firesim b/sims/firesim index ac8bcd8b..1f62b3ef 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit ac8bcd8b349d89637750fb20e77545818df4ff2d +Subproject commit 1f62b3ef1591a3cfb84439fa767b146eb7e3e024 diff --git a/software/firemarshal b/software/firemarshal index a98f1faf..b014183a 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit a98f1faff6d11a0b4418d3a814cabd51c734c822 +Subproject commit b014183ac6afed7fe1aca89fa010be8d13ad4079 diff --git a/toolchains/esp-tools/esp-tools-feedstock b/toolchains/esp-tools/esp-tools-feedstock deleted file mode 160000 index 76a16c8d..00000000 --- a/toolchains/esp-tools/esp-tools-feedstock +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 76a16c8ddbf3a8af420e1551192d58c4d41e7f66 diff --git a/toolchains/esp-tools/riscv-isa-sim b/toolchains/esp-tools/riscv-isa-sim deleted file mode 160000 index 34741e07..00000000 --- a/toolchains/esp-tools/riscv-isa-sim +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 34741e07bc6b56f1762ce579537948d58e28cd5a diff --git a/toolchains/esp-tools/riscv-pk b/toolchains/esp-tools/riscv-pk deleted file mode 160000 index e8e6b3aa..00000000 --- a/toolchains/esp-tools/riscv-pk +++ /dev/null @@ -1 +0,0 @@ -Subproject commit e8e6b3aaee44d43b48164fbd377864c3a682dbd3 diff --git a/toolchains/esp-tools/riscv-tests b/toolchains/esp-tools/riscv-tests deleted file mode 160000 index 7c3dfd32..00000000 --- a/toolchains/esp-tools/riscv-tests +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 7c3dfd3205fa90104db06346e797a8eeea149207 diff --git a/toolchains/libgloss b/toolchains/libgloss index 39234a16..0ecdf7fa 160000 --- a/toolchains/libgloss +++ b/toolchains/libgloss @@ -1 +1 @@ -Subproject commit 39234a16247ab1fa234821b251f1f1870c3de343 +Subproject commit 0ecdf7fa08c9e40f9d60903b8189511beb8555ab diff --git a/toolchains/riscv-tools/riscv-isa-sim b/toolchains/riscv-tools/riscv-isa-sim index 4d8651be..e46fc096 160000 --- a/toolchains/riscv-tools/riscv-isa-sim +++ b/toolchains/riscv-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit 4d8651be943ea706eb8dcb3443add2e7ccc117a6 +Subproject commit e46fc096e2402c2149caee93111569f5a1dd165a diff --git a/toolchains/riscv-tools/riscv-pk b/toolchains/riscv-tools/riscv-pk index e8e6b3aa..e681d808 160000 --- a/toolchains/riscv-tools/riscv-pk +++ b/toolchains/riscv-tools/riscv-pk @@ -1 +1 @@ -Subproject commit e8e6b3aaee44d43b48164fbd377864c3a682dbd3 +Subproject commit e681d8088bf67af83d7735244c22614d990dfdaf diff --git a/toolchains/riscv-tools/riscv-spike-devices b/toolchains/riscv-tools/riscv-spike-devices index 39a0993b..cc184f2c 160000 --- a/toolchains/riscv-tools/riscv-spike-devices +++ b/toolchains/riscv-tools/riscv-spike-devices @@ -1 +1 @@ -Subproject commit 39a0993b20346215c8c672e083519f02d23af67c +Subproject commit cc184f2cc179765bb7dcf4a82075403604a60813 diff --git a/toolchains/riscv-tools/riscv-tools-feedstock b/toolchains/riscv-tools/riscv-tools-feedstock index 56c29e01..917b56ef 160000 --- a/toolchains/riscv-tools/riscv-tools-feedstock +++ b/toolchains/riscv-tools/riscv-tools-feedstock @@ -1 +1 @@ -Subproject commit 56c29e01ba3e705c563edd1271a387119bddb5a5 +Subproject commit 917b56ef1a78871be22283ecdb01658ac11cbe61 diff --git a/tools/barstools b/tools/barstools deleted file mode 160000 index 60a1be9b..00000000 --- a/tools/barstools +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 60a1be9bfe344fccbddd4874524accb3c9d2ade9 diff --git a/tools/cde b/tools/cde index 384c06b8..2bcaeae2 160000 --- a/tools/cde +++ b/tools/cde @@ -1 +1 @@ -Subproject commit 384c06b8d45c8184ca2f3fba2f8e78f79d2c1b51 +Subproject commit 2bcaeae2b9914bd25497ce3c6fa62dc5ca80e09f diff --git a/tools/dsptools b/tools/dsptools index 8f433663..a310a157 160000 --- a/tools/dsptools +++ b/tools/dsptools @@ -1 +1 @@ -Subproject commit 8f4336639578d2e2dbaf61e542ee1f0fa8d79e63 +Subproject commit a310a157cab6e569d30741eae4ca5592069cab7c diff --git a/tools/dsptools-chisel3 b/tools/dsptools-chisel3 new file mode 160000 index 00000000..8f433663 --- /dev/null +++ b/tools/dsptools-chisel3 @@ -0,0 +1 @@ +Subproject commit 8f4336639578d2e2dbaf61e542ee1f0fa8d79e63 diff --git a/tools/fixedpoint b/tools/fixedpoint index 36ce43c9..ef164009 160000 --- a/tools/fixedpoint +++ b/tools/fixedpoint @@ -1 +1 @@ -Subproject commit 36ce43c90ce9cfc63e7698fa1e27fd122c878e9e +Subproject commit ef164009e40ce5a5abe61ebcc11c12ff82e34014 diff --git a/tools/fixedpoint-chisel3 b/tools/fixedpoint-chisel3 new file mode 160000 index 00000000..36ce43c9 --- /dev/null +++ b/tools/fixedpoint-chisel3 @@ -0,0 +1 @@ +Subproject commit 36ce43c90ce9cfc63e7698fa1e27fd122c878e9e diff --git a/tools/midas-targetutils b/tools/midas-targetutils new file mode 160000 index 00000000..d0fc62d2 --- /dev/null +++ b/tools/midas-targetutils @@ -0,0 +1 @@ +Subproject commit d0fc62d2b463a438f8d721a2dcfcddf315f3d760 diff --git a/tools/rocket-dsp-utils b/tools/rocket-dsp-utils index 24bf9a27..c4c638da 160000 --- a/tools/rocket-dsp-utils +++ b/tools/rocket-dsp-utils @@ -1 +1 @@ -Subproject commit 24bf9a27a8fe565392f1a6aa3e53fdbe92a64dbc +Subproject commit c4c638da02351c701ff31e73aadd987baa7a2acc diff --git a/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala b/tools/stage-chisel3/src/main/scala/ChipyardAnnotations.scala similarity index 100% rename from generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala rename to tools/stage-chisel3/src/main/scala/ChipyardAnnotations.scala diff --git a/generators/chipyard/src/main/scala/stage/ChipyardCli.scala b/tools/stage-chisel3/src/main/scala/ChipyardCli.scala similarity index 100% rename from generators/chipyard/src/main/scala/stage/ChipyardCli.scala rename to tools/stage-chisel3/src/main/scala/ChipyardCli.scala diff --git a/generators/chipyard/src/main/scala/stage/ChipyardOptions.scala b/tools/stage-chisel3/src/main/scala/ChipyardOptions.scala similarity index 100% rename from generators/chipyard/src/main/scala/stage/ChipyardOptions.scala rename to tools/stage-chisel3/src/main/scala/ChipyardOptions.scala diff --git a/generators/chipyard/src/main/scala/stage/ChipyardStage.scala b/tools/stage-chisel3/src/main/scala/ChipyardStage.scala similarity index 100% rename from generators/chipyard/src/main/scala/stage/ChipyardStage.scala rename to tools/stage-chisel3/src/main/scala/ChipyardStage.scala diff --git a/generators/chipyard/src/main/scala/stage/StageUtils.scala b/tools/stage-chisel3/src/main/scala/StageUtils.scala similarity index 100% rename from generators/chipyard/src/main/scala/stage/StageUtils.scala rename to tools/stage-chisel3/src/main/scala/StageUtils.scala diff --git a/generators/chipyard/src/main/scala/stage/package.scala b/tools/stage-chisel3/src/main/scala/package.scala similarity index 100% rename from generators/chipyard/src/main/scala/stage/package.scala rename to tools/stage-chisel3/src/main/scala/package.scala diff --git a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala b/tools/stage-chisel3/src/main/scala/phases/AddDefaultTests.scala similarity index 100% rename from generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala rename to tools/stage-chisel3/src/main/scala/phases/AddDefaultTests.scala diff --git a/generators/chipyard/src/main/scala/stage/phases/Checks.scala b/tools/stage-chisel3/src/main/scala/phases/Checks.scala similarity index 100% rename from generators/chipyard/src/main/scala/stage/phases/Checks.scala rename to tools/stage-chisel3/src/main/scala/phases/Checks.scala diff --git a/generators/chipyard/src/main/scala/stage/phases/GenerateArtefacts.scala b/tools/stage-chisel3/src/main/scala/phases/GenerateArtefacts.scala similarity index 100% rename from generators/chipyard/src/main/scala/stage/phases/GenerateArtefacts.scala rename to tools/stage-chisel3/src/main/scala/phases/GenerateArtefacts.scala diff --git a/generators/chipyard/src/main/scala/stage/phases/GenerateFirrtlAnnos.scala b/tools/stage-chisel3/src/main/scala/phases/GenerateFirrtlAnnos.scala similarity index 100% rename from generators/chipyard/src/main/scala/stage/phases/GenerateFirrtlAnnos.scala rename to tools/stage-chisel3/src/main/scala/phases/GenerateFirrtlAnnos.scala diff --git a/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala b/tools/stage-chisel3/src/main/scala/phases/GenerateTestSuiteMakefrags.scala similarity index 100% rename from generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala rename to tools/stage-chisel3/src/main/scala/phases/GenerateTestSuiteMakefrags.scala diff --git a/generators/chipyard/src/main/scala/stage/phases/PreElaboration.scala b/tools/stage-chisel3/src/main/scala/phases/PreElaboration.scala similarity index 100% rename from generators/chipyard/src/main/scala/stage/phases/PreElaboration.scala rename to tools/stage-chisel3/src/main/scala/phases/PreElaboration.scala diff --git a/generators/chipyard/src/main/scala/stage/phases/TransformAnnotations.scala b/tools/stage-chisel3/src/main/scala/phases/TransformAnnotations.scala similarity index 100% rename from generators/chipyard/src/main/scala/stage/phases/TransformAnnotations.scala rename to tools/stage-chisel3/src/main/scala/phases/TransformAnnotations.scala diff --git a/tools/stage/src/main/scala/ChipyardAnnotations.scala b/tools/stage/src/main/scala/ChipyardAnnotations.scala new file mode 100644 index 00000000..b9c04eb8 --- /dev/null +++ b/tools/stage/src/main/scala/ChipyardAnnotations.scala @@ -0,0 +1,66 @@ +// See LICENSE for license details. +// Based on Rocket Chip's stage implementation + +package chipyard.stage + +import chisel3.experimental.BaseModule +import firrtl.annotations.{Annotation, NoTargetAnnotation} +import firrtl.options.{HasShellOptions, ShellOption, Unserializable} + +trait ChipyardOption extends Unserializable { this: Annotation => } + +/** This hijacks the existing ConfigAnnotation to accept the legacy _-delimited format */ +private[stage] object UnderscoreDelimitedConfigsAnnotation extends HasShellOptions { + override val options = Seq( + new ShellOption[String]( + longOption = "legacy-configs", + toAnnotationSeq = a => { + val split = a.split(':') + assert(split.length == 2, s"'${a}' split by ':' doesn't yield two things") + val packageName = split.head + val configs = split.last.split("_") + Seq(new ConfigsAnnotation(configs map { config => if (config contains ".") s"${config}" else s"${packageName}.${config}" } )) + }, + helpText = "A string of underscore-delimited configs (configs have decreasing precendence from left to right).", + shortOption = Some("LC") + ) + ) +} + +/** Paths to config classes */ +case class ConfigsAnnotation(configNames: Seq[String]) extends NoTargetAnnotation with ChipyardOption +private[stage] object ConfigsAnnotation extends HasShellOptions { + override val options = Seq( + new ShellOption[Seq[String]]( + longOption = "configs", + toAnnotationSeq = a => Seq(ConfigsAnnotation(a)), + helpText = "", + shortOption = Some("C") + ) + ) +} + +case class TopModuleAnnotation(clazz: Class[_ <: Any]) extends NoTargetAnnotation with ChipyardOption +private[stage] object TopModuleAnnotation extends HasShellOptions { + override val options = Seq( + new ShellOption[String]( + longOption = "top-module", + toAnnotationSeq = a => Seq(TopModuleAnnotation(Class.forName(a).asInstanceOf[Class[_ <: BaseModule]])), + helpText = "", + shortOption = Some("T") + ) + ) +} + +/** Optional base name for generated files' filenames */ +case class OutputBaseNameAnnotation(outputBaseName: String) extends NoTargetAnnotation with ChipyardOption +private[stage] object OutputBaseNameAnnotation extends HasShellOptions { + override val options = Seq( + new ShellOption[String]( + longOption = "name", + toAnnotationSeq = a => Seq(OutputBaseNameAnnotation(a)), + helpText = "", + shortOption = Some("n") + ) + ) +} diff --git a/tools/stage/src/main/scala/ChipyardCli.scala b/tools/stage/src/main/scala/ChipyardCli.scala new file mode 100644 index 00000000..d6071ff3 --- /dev/null +++ b/tools/stage/src/main/scala/ChipyardCli.scala @@ -0,0 +1,17 @@ +// See LICENSE for license details. +// Based on Rocket Chip's stage implementation + +package chipyard.stage + +import firrtl.options.Shell + +trait ChipyardCli { this: Shell => + + parser.note("Chipyard Generator Options") + Seq( + TopModuleAnnotation, + ConfigsAnnotation, + OutputBaseNameAnnotation, + UnderscoreDelimitedConfigsAnnotation + ).foreach(_.addOptions(parser)) +} diff --git a/tools/stage/src/main/scala/ChipyardOptions.scala b/tools/stage/src/main/scala/ChipyardOptions.scala new file mode 100644 index 00000000..8d8eb6e3 --- /dev/null +++ b/tools/stage/src/main/scala/ChipyardOptions.scala @@ -0,0 +1,40 @@ +// See LICENSE + +package chipyard.stage + +class ChipyardOptions private[stage] ( + val topModule: Option[Class[_ <: Any]] = None, + val configNames: Option[Seq[String]] = None, + val outputBaseName: Option[String] = None) { + + private[stage] def copy( + topModule: Option[Class[_ <: Any]] = topModule, + configNames: Option[Seq[String]] = configNames, + outputBaseName: Option[String] = outputBaseName, + ): ChipyardOptions = { + + new ChipyardOptions( + topModule=topModule, + configNames=configNames, + outputBaseName=outputBaseName, + ) + } + + lazy val topPackage: Option[String] = topModule match { + case Some(a) => Some(a.getPackage.getName) + case _ => None + } + + lazy val configClass: Option[String] = configNames match { + case Some(names) => + val classNames = names.map{ n => n.split('.').last } + Some(classNames.mkString("_")) + case _ => None + } + + lazy val longName: Option[String] = outputBaseName match { + case Some(name) => Some(name) + case _ => + if (!topPackage.isEmpty && !configClass.isEmpty) Some(s"${topPackage.get}.${configClass.get}") else None + } +} diff --git a/tools/stage/src/main/scala/ChipyardStage.scala b/tools/stage/src/main/scala/ChipyardStage.scala new file mode 100644 index 00000000..2cf4e5bf --- /dev/null +++ b/tools/stage/src/main/scala/ChipyardStage.scala @@ -0,0 +1,71 @@ +// See LICENSE for license details. +// Based on Rocket Chip's stage implementation + +package chipyard.stage + +import circt.stage.{ChiselStage, CIRCTTargetAnnotation, CIRCTTarget} +import firrtl.options.PhaseManager.PhaseDependency +import firrtl.options.{Shell} +import firrtl.{AnnotationSeq} +import firrtl.options.{Phase, PhaseManager, Shell, Stage, StageError, StageMain, Dependency} + +final class ChipyardChiselStage extends ChiselStage { + override def run(annotations: AnnotationSeq): AnnotationSeq = { + + val pm = new PhaseManager( + targets = Seq( + Dependency[chisel3.stage.phases.Checks], + Dependency[chisel3.stage.phases.AddImplicitOutputFile], + Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile], + Dependency[chisel3.stage.phases.MaybeAspectPhase], + Dependency[chisel3.stage.phases.AddSerializationAnnotations], + Dependency[chisel3.stage.phases.Convert], + Dependency[chisel3.stage.phases.AddDedupGroupAnnotations], + Dependency[chisel3.stage.phases.MaybeInjectingPhase], + Dependency[circt.stage.phases.AddImplicitOutputFile], + Dependency[circt.stage.phases.Checks], + Dependency[circt.stage.phases.CIRCT] + ), + currentState = Seq( + Dependency[firrtl.stage.phases.AddDefaults], + Dependency[firrtl.stage.phases.Checks] + ) + ) + pm.transform(annotations :+ CIRCTTargetAnnotation(CIRCTTarget.CHIRRTL)) + } +} + +class ChipyardStage extends ChiselStage { + override val shell = new Shell("chipyard") with ChipyardCli with circt.stage.CLI + override def run(annotations: AnnotationSeq): AnnotationSeq = { + + val pm = new PhaseManager( + targets = Seq( + Dependency[chipyard.stage.phases.Checks], + Dependency[chipyard.stage.phases.TransformAnnotations], + Dependency[chipyard.stage.phases.PreElaboration], + Dependency[ChipyardChiselStage], + Dependency[chipyard.stage.phases.GenerateFirrtlAnnos], + Dependency[chipyard.stage.phases.AddDefaultTests], + Dependency[chipyard.stage.phases.GenerateTestSuiteMakefrags], + Dependency[chipyard.stage.phases.GenerateArtefacts], + ), + currentState = Seq( + Dependency[firrtl.stage.phases.AddDefaults], + Dependency[firrtl.stage.phases.Checks] + ) + ) + pm.transform(annotations) + } + // override val targets: Seq[PhaseDependency] = Seq( + // Dependency[chipyard.stage.phases.Checks], + // Dependency[chipyard.stage.phases.TransformAnnotations], + // Dependency[chipyard.stage.phases.PreElaboration], + // Dependency[ChipyardChiselStage], + // Dependency[chipyard.stage.phases.GenerateFirrtlAnnos], + // Dependency[chipyard.stage.phases.AddDefaultTests], + // Dependency[chipyard.stage.phases.GenerateTestSuiteMakefrags], + // Dependency[chipyard.stage.phases.GenerateArtefacts], + // ) + override final def invalidates(a: Phase): Boolean = false +} diff --git a/tools/stage/src/main/scala/StageUtils.scala b/tools/stage/src/main/scala/StageUtils.scala new file mode 100644 index 00000000..5654c20a --- /dev/null +++ b/tools/stage/src/main/scala/StageUtils.scala @@ -0,0 +1,32 @@ +// See LICENSE + +package chipyard.stage + +import java.io.{File, FileWriter} + +import org.chipsalliance.cde.config.{Config, Parameters} +import freechips.rocketchip.util.{BlackBoxedROM, ROMGenerator} + +trait HasChipyardStageUtils { + + def getConfig(fullConfigClassNames: Seq[String]): Config = { + new Config(fullConfigClassNames.foldRight(Parameters.empty) { case (currentName, config) => + val currentConfig = try { + Class.forName(currentName).newInstance.asInstanceOf[Config] + } catch { + case e: java.lang.ClassNotFoundException => + throw new Exception(s"""Unable to find part "$currentName" from "$fullConfigClassNames", did you misspell it or specify the wrong package path?""", e) + } + currentConfig ++ config + }) + } + + def writeOutputFile(targetDir: String, fname: String, contents: String): File = { + val f = new File(targetDir, fname) + val fw = new FileWriter(f) + fw.write(contents) + fw.close + f + } + +} diff --git a/tools/stage/src/main/scala/package.scala b/tools/stage/src/main/scala/package.scala new file mode 100644 index 00000000..5dc89f9c --- /dev/null +++ b/tools/stage/src/main/scala/package.scala @@ -0,0 +1,24 @@ +// See LICENSE + +package chipyard + +import firrtl.AnnotationSeq +import firrtl.options.OptionsView + +package object stage { + + implicit object ChipyardOptionsView extends OptionsView[ChipyardOptions] { + + def view(annotations: AnnotationSeq): ChipyardOptions = annotations + .collect { case a: ChipyardOption => a } + .foldLeft(new ChipyardOptions()){ (c, x) => + x match { + case TopModuleAnnotation(a) => c.copy(topModule = Some(a)) + case ConfigsAnnotation(a) => c.copy(configNames = Some(a)) + case OutputBaseNameAnnotation(a) => c.copy(outputBaseName = Some(a)) + } + } + + } + +} diff --git a/tools/stage/src/main/scala/phases/AddDefaultTests.scala b/tools/stage/src/main/scala/phases/AddDefaultTests.scala new file mode 100644 index 00000000..e0addc40 --- /dev/null +++ b/tools/stage/src/main/scala/phases/AddDefaultTests.scala @@ -0,0 +1,53 @@ +// See LICENSE for license details. +// Based on Rocket Chip's stage implementation + +package chipyard.stage.phases + +import scala.util.Try +import scala.collection.mutable + +import org.chipsalliance.cde.config.Parameters +import chisel3.stage.phases.Elaborate +import firrtl.AnnotationSeq +import firrtl.annotations.{Annotation, NoTargetAnnotation} +import firrtl.options._ +import firrtl.options.Viewer._ +import freechips.rocketchip.system.{RocketTestSuite, TestGeneration} +import freechips.rocketchip.subsystem.{TilesLocated, InSubsystem} +import freechips.rocketchip.tile.XLen + +import chipyard.TestSuiteHelper +import chipyard.TestSuitesKey +import chipyard.stage._ + +/** Annotation that contains a list of [[RocketTestSuite]]s to run */ +case class ChipyardTestSuiteAnnotation(tests: Seq[RocketTestSuite]) extends NoTargetAnnotation with Unserializable + + +class AddDefaultTests extends Phase with PreservesAll with HasChipyardStageUtils { + override val prerequisites = Seq(Dependency[ChipyardChiselStage]) + override val optionalPrerequisiteOf = Seq(Dependency[GenerateTestSuiteMakefrags]) + + private def addTestSuiteAnnotations(implicit p: Parameters): Seq[Annotation] = { + val annotations = mutable.ArrayBuffer[Annotation]() + val suiteHelper = new TestSuiteHelper + // Use Xlen as a proxy for detecting if we are a processor-like target + // The underlying test suites expect this field to be defined + val tileParams = p(TilesLocated(InSubsystem)) map (tp => tp.tileParams) + if (p.lift(XLen).nonEmpty) + // If a custom test suite is set up, use the custom test suite + annotations += CustomMakefragSnippet(p(TestSuitesKey).apply(tileParams, suiteHelper, p)) + + ChipyardTestSuiteAnnotation(suiteHelper.suites.values.toSeq) +: annotations.toSeq + } + + + override def transform(annotations: AnnotationSeq): AnnotationSeq = { + val (testSuiteAnnos, oAnnos) = annotations.partition { + case ChipyardTestSuiteAnnotation(_) => true + case o => false + } + implicit val p = getConfig(view[ChipyardOptions](annotations).configNames.get).toInstance + addTestSuiteAnnotations(p) ++ oAnnos + } +} diff --git a/tools/stage/src/main/scala/phases/Checks.scala b/tools/stage/src/main/scala/phases/Checks.scala new file mode 100644 index 00000000..b7eaae6e --- /dev/null +++ b/tools/stage/src/main/scala/phases/Checks.scala @@ -0,0 +1,47 @@ +// See LICENSE + +package chipyard.stage.phases + +import firrtl.AnnotationSeq +import firrtl.annotations.Annotation +import firrtl.options.{OptionsException, Phase, TargetDirAnnotation} +import chipyard.stage._ + +import scala.collection.mutable + +/** Checks for the correct type and number of command line arguments */ +class Checks extends Phase with PreservesAll { + + override def transform(annotations: AnnotationSeq): AnnotationSeq = { + val targetDir, topModule, configNames, outputBaseName = mutable.ListBuffer[Annotation]() + + annotations.foreach { + case a: TargetDirAnnotation => a +=: targetDir + case a: TopModuleAnnotation => a +=: topModule + case a: ConfigsAnnotation => a +=: configNames + case a: OutputBaseNameAnnotation => a +=: outputBaseName + case _ => + } + + def required(annoList: mutable.ListBuffer[Annotation], option: String): Unit = { + if (annoList.size != 1) { + throw new OptionsException(s"Exactly one $option required") + } + } + + def optional(annoList: mutable.ListBuffer[Annotation], option: String): Unit = { + if (annoList.size > 1) { + throw new OptionsException(s"Too many $option options have been specified") + } + } + + required(targetDir, "target directory") + required(topModule, "top module") + required(configNames, "configs string (','-delimited)") + + optional(outputBaseName, "output base name") + + annotations + } + +} diff --git a/tools/stage/src/main/scala/phases/GenerateArtefacts.scala b/tools/stage/src/main/scala/phases/GenerateArtefacts.scala new file mode 100644 index 00000000..0982ae36 --- /dev/null +++ b/tools/stage/src/main/scala/phases/GenerateArtefacts.scala @@ -0,0 +1,26 @@ +// See LICENSE + +package chipyard.stage.phases + +import firrtl.AnnotationSeq +import firrtl.options.{Dependency, Phase, StageOptions} +import firrtl.options.Viewer.view +import chipyard.stage._ +import freechips.rocketchip.util.{ElaborationArtefacts} + +/** Writes [[ElaborationArtefacts]] into files */ +class GenerateArtefacts extends Phase with PreservesAll with HasChipyardStageUtils { + + override val prerequisites = Seq(Dependency[chipyard.stage.ChipyardChiselStage]) + + override def transform(annotations: AnnotationSeq): AnnotationSeq = { + val targetDir = view[StageOptions](annotations).targetDir + + ElaborationArtefacts.files.foreach { case (extension, contents) => + writeOutputFile(targetDir, s"${view[ChipyardOptions](annotations).longName.get}.${extension}", contents ()) + } + + annotations + } + +} diff --git a/tools/stage/src/main/scala/phases/GenerateFirrtlAnnos.scala b/tools/stage/src/main/scala/phases/GenerateFirrtlAnnos.scala new file mode 100644 index 00000000..ec69aef2 --- /dev/null +++ b/tools/stage/src/main/scala/phases/GenerateFirrtlAnnos.scala @@ -0,0 +1,34 @@ +// See LICENSE + +package chipyard.stage.phases + +import firrtl.AnnotationSeq +import firrtl.annotations.{JsonProtocol} +import firrtl.options.Viewer.view +import firrtl.options._ +import chipyard.stage._ + +/** Writes FIRRTL annotations into a file */ +class GenerateFirrtlAnnos extends Phase with PreservesAll with HasChipyardStageUtils { + + override val prerequisites = Seq(Dependency[chipyard.stage.ChipyardChiselStage]) + + override def transform(annotations: AnnotationSeq): AnnotationSeq = { + val targetDir = view[StageOptions](annotations).targetDir + val fileName = s"${view[ChipyardOptions](annotations).longName.get}.anno.json" + + val annos = annotations.view.flatMap { + // Remove TargetDirAnnotation so that we can pass as argument to FIRRTL + // Remove CustomFileEmission, those are serialized automatically by Stages + case (_: Unserializable | _: TargetDirAnnotation | _: CustomFileEmission) => + None + case a => + Some(a) + } + + writeOutputFile(targetDir, fileName, JsonProtocol.serialize(annos.toSeq)) + + annotations + } + +} diff --git a/tools/stage/src/main/scala/phases/GenerateTestSuiteMakefrags.scala b/tools/stage/src/main/scala/phases/GenerateTestSuiteMakefrags.scala new file mode 100644 index 00000000..18e73121 --- /dev/null +++ b/tools/stage/src/main/scala/phases/GenerateTestSuiteMakefrags.scala @@ -0,0 +1,49 @@ +// See LICENSE for license details. +// Based on Rocket Chip's stage implementation + +package chipyard.stage.phases + +import scala.collection.mutable + +import firrtl.AnnotationSeq +import firrtl.annotations.{Annotation, NoTargetAnnotation} +import firrtl.options.{Phase, StageOptions, Unserializable, Dependency} +import firrtl.options.Viewer.view +import chipyard.stage._ +import freechips.rocketchip.system.TestGeneration + +trait MakefragSnippet { self: Annotation => + def toMakefrag: String +} + +case class CustomMakefragSnippet(val toMakefrag: String) extends NoTargetAnnotation with MakefragSnippet with Unserializable + +/** Generates a make script to run tests in [[RocketTestSuiteAnnotation]]. */ +class GenerateTestSuiteMakefrags extends Phase with HasChipyardStageUtils { + + // Our annotations tend not to be serializable, but are not marked as such. + override val prerequisites = Seq(Dependency[chipyard.stage.phases.GenerateFirrtlAnnos], + Dependency[chipyard.stage.phases.AddDefaultTests]) + + override def transform(annotations: AnnotationSeq): AnnotationSeq = { + val targetDir = view[StageOptions](annotations).targetDir + val fileName = s"${view[ChipyardOptions](annotations).longName.get}.d" + + val makefragBuilder = new mutable.StringBuilder() + val outputAnnotations = annotations.flatMap { + case ChipyardTestSuiteAnnotation(tests) => + // Unfortunately the gen method of TestGeneration is rocketchip package + // private, so we either have to copy code in or use the stateful form + TestGeneration.addSuites(tests) + None + case a: MakefragSnippet => + makefragBuilder :+ ("\n" + a.toMakefrag) + None + case a => Some(a) + } + writeOutputFile(targetDir, fileName, TestGeneration.generateMakeFrag ++ makefragBuilder.toString) + outputAnnotations + } + + override final def invalidates(a: Phase): Boolean = false +} diff --git a/tools/stage/src/main/scala/phases/PreElaboration.scala b/tools/stage/src/main/scala/phases/PreElaboration.scala new file mode 100644 index 00000000..646d54c3 --- /dev/null +++ b/tools/stage/src/main/scala/phases/PreElaboration.scala @@ -0,0 +1,43 @@ +// See LICENSE + +package chipyard.stage.phases + +import chisel3.RawModule +import chisel3.stage.ChiselGeneratorAnnotation +import firrtl.AnnotationSeq +import firrtl.options.Viewer.view +import firrtl.options.{Dependency, Phase, StageOptions} +import org.chipsalliance.cde.config.{Field, Parameters} +import freechips.rocketchip.diplomacy._ +import chipyard.stage._ + +case object TargetDirKey extends Field[String](".") + +/** Constructs a generator function that returns a top module with given config parameters */ +class PreElaboration extends Phase with PreservesAll with HasChipyardStageUtils { + + override val prerequisites = Seq(Dependency[Checks]) + override val optionalPrerequisiteOf = Seq(Dependency[chisel3.stage.phases.Elaborate]) + + override def transform(annotations: AnnotationSeq): AnnotationSeq = { + + val stageOpts = view[StageOptions](annotations) + val rOpts = view[ChipyardOptions](annotations) + val topMod = rOpts.topModule.get + + val config = getConfig(rOpts.configNames.get).alterPartial { + case TargetDirKey => stageOpts.targetDir + } + + val gen = () => + topMod + .getConstructor(classOf[Parameters]) + .newInstance(config) match { + case a: RawModule => a + case a: LazyModule => LazyModule(a).module + } + + ChiselGeneratorAnnotation(gen) +: annotations + } + +} diff --git a/tools/stage/src/main/scala/phases/PreservesAll.scala b/tools/stage/src/main/scala/phases/PreservesAll.scala new file mode 100644 index 00000000..30884be4 --- /dev/null +++ b/tools/stage/src/main/scala/phases/PreservesAll.scala @@ -0,0 +1,8 @@ +package chipyard.stage.phases + +import firrtl.AnnotationSeq +import firrtl.options.{Dependency, DependencyManagerException, Phase, PhaseManager} + +trait PreservesAll { this: Phase => + override def invalidates(phase: Phase) = false +} diff --git a/tools/stage/src/main/scala/phases/TransformAnnotations.scala b/tools/stage/src/main/scala/phases/TransformAnnotations.scala new file mode 100644 index 00000000..71640841 --- /dev/null +++ b/tools/stage/src/main/scala/phases/TransformAnnotations.scala @@ -0,0 +1,21 @@ +// See LICENSE + +package chipyard.stage.phases + +import chisel3.stage.ChiselOutputFileAnnotation +import firrtl.AnnotationSeq +import firrtl.options.Viewer.view +import firrtl.options.{Dependency, Phase} +import chipyard.stage._ + +/** Transforms RocketChipAnnotations into those used by other stages */ +class TransformAnnotations extends Phase with PreservesAll with HasChipyardStageUtils { + + override val prerequisites = Seq(Dependency[Checks]) + override val optionalPrerequisiteOf = Seq(Dependency[chisel3.stage.phases.AddImplicitOutputFile]) + + override def transform(annotations: AnnotationSeq): AnnotationSeq = { + /** Construct output file annotation for emission */ + new ChiselOutputFileAnnotation(view[ChipyardOptions](annotations).longName.get) +: annotations + } +} diff --git a/tools/tapeout/src/main/scala/macrolib/ConfReader.scala b/tools/tapeout/src/main/scala/macrolib/ConfReader.scala new file mode 100644 index 00000000..ec701d6e --- /dev/null +++ b/tools/tapeout/src/main/scala/macrolib/ConfReader.scala @@ -0,0 +1,95 @@ +package mdf.macrolib + +object ConfReader { + import scala.util.matching.Regex._ + + type ConfPort = (String, Boolean) // prefix (e.g. "RW0") and true if masked + + /** Rename ports like "read" to R0, "write" to W0, and "rw" to RW0, and + * return a count of read, write, and readwrite ports. + */ + def renamePorts(ports: Seq[String]): (Seq[ConfPort], Int, Int, Int) = { + var readCount = 0 + var writeCount = 0 + var readWriteCount = 0 + ( + ports.map { + _ match { + case "read" => readCount += 1; (s"R${readCount - 1}", false) + case "write" => writeCount += 1; (s"W${writeCount - 1}", false) + case "mwrite" => writeCount += 1; (s"W${writeCount - 1}", true) + case "rw" => readWriteCount += 1; (s"RW${readWriteCount - 1}", false) + case "mrw" => readWriteCount += 1; (s"RW${readWriteCount - 1}", true) + } + }, + readCount, + writeCount, + readWriteCount + ) + } + + def generateFirrtlPort(port: ConfPort, width: Int, depth: Int, maskGran: Option[Int]): MacroPort = { + val (prefix, masked) = port + val isReadWriter = prefix.startsWith("RW") + val isReader = prefix.startsWith("R") && !isReadWriter + val isWriter = prefix.startsWith("W") + val r = if (isReadWriter) "r" else "" + val w = if (isReadWriter) "w" else "" + MacroPort( + address = PolarizedPort(s"${prefix}_addr", ActiveHigh), + clock = Some(PolarizedPort(s"${prefix}_clk", PositiveEdge)), + writeEnable = if (isReadWriter) Some(PolarizedPort(s"${prefix}_${w}mode", ActiveHigh)) else None, + output = if (isReader || isReadWriter) Some(PolarizedPort(s"${prefix}_${w}data", ActiveHigh)) else None, + input = if (isWriter || isReadWriter) Some(PolarizedPort(s"${prefix}_${r}data", ActiveHigh)) else None, + maskPort = if (masked) Some(PolarizedPort(s"${prefix}_${w}mask", ActiveHigh)) else None, + maskGran = if (masked) maskGran else None, + width = Some(width), + depth = Some(depth) + ) + } + + /** Read a conf line into a SRAMMacro, but returns an error string in Left + * instead of throwing errors if the line is malformed. + */ + def readSingleLineSafe(line: String): Either[String, SRAMMacro] = { + val pattern = """name ([^\s]+) depth (\d+) width (\d+) ports ([a-z,]+)\s?(?:mask_gran (\d+))?""".r + pattern.findFirstMatchIn(line) match { + case Some(m: Match) => { + val name: String = m.group(1) + val depth: Int = (m.group(2)).toInt + val width: Int = (m.group(3)).toInt + val ports: Seq[String] = (m.group(4)).split(",") + val (firrtlPorts, readPortCount, writePortCount, readWritePortCount) = renamePorts(ports) + val familyStr = + (if (readPortCount > 0) s"${readPortCount}r" else "") + + (if (writePortCount > 0) s"${writePortCount}w" else "") + + (if (readWritePortCount > 0) s"${readWritePortCount}rw" else "") + val maskGran: Option[Int] = Option(m.group(5)).map(_.toInt) + Right( + SRAMMacro( + name = name, + width = width, + depth = depth, + family = familyStr, + vt = "", + mux = 1, + ports = firrtlPorts.map(generateFirrtlPort(_, width, depth, maskGran)), + extraPorts = List() + ) + ) + } + case _ => Left("Input line did not match conf regex") + } + } + + /** Read a conf line into a SRAMMacro. */ + def readSingleLine(line: String): SRAMMacro = { + readSingleLineSafe(line).right.get + } + + /** Read the contents of the conf file into a seq of SRAMMacro. */ + def readFromString(contents: String): Seq[SRAMMacro] = { + // Trim, remove empty lines, then pass to readSingleLine + contents.split("\n").map(_.trim).filter(_ != "").map(readSingleLine(_)) + } +} diff --git a/tools/tapeout/src/main/scala/macrolib/FillerMacroBase.scala b/tools/tapeout/src/main/scala/macrolib/FillerMacroBase.scala new file mode 100644 index 00000000..688871b5 --- /dev/null +++ b/tools/tapeout/src/main/scala/macrolib/FillerMacroBase.scala @@ -0,0 +1,61 @@ +package mdf.macrolib + +import play.api.libs.json._ +import scala.language.implicitConversions + +// Filler and metal filler +abstract class FillerMacroBase(name: String, vt: String) extends Macro { + override def toString(): String = { + s"${this.getClass.getSimpleName}(name=${name}, vt=${vt})" + } + + override def toJSON(): JsObject = { + JsObject( + Seq( + "type" -> JsString(typeStr), + "name" -> Json.toJson(name), + "vt" -> Json.toJson(vt) + ) + ) + } +} +object FillerMacroBase { + def parseJSON(json: Map[String, JsValue]): Option[FillerMacroBase] = { + val typee: String = json.get("type") match { + case Some(x: JsString) => + x.value match { + case "" => return None + case x => x + } + case _ => return None + } + val name: String = json.get("name") match { + case Some(x: JsString) => + x.value match { + case "" => return None + case x => x + } + case _ => return None + } + val vt: String = json.get("vt") match { + case Some(x: JsString) => + x.value match { + case "" => return None + case x => x + } + case _ => return None + } + typee match { + case "metal filler cell" => Some(MetalFillerMacro(name, vt)) + case "filler cell" => Some(FillerMacro(name, vt)) + case _ => None + } + } +} + +case class FillerMacro(name: String, vt: String) extends FillerMacroBase(name, vt) { + override def typeStr = "filler cell" +} +case class MetalFillerMacro(name: String, vt: String) extends FillerMacroBase(name, vt) { + override def typeStr = "metal filler cell" +} diff --git a/tools/tapeout/src/main/scala/macrolib/FlipChipMacro.scala b/tools/tapeout/src/main/scala/macrolib/FlipChipMacro.scala new file mode 100644 index 00000000..88a20aea --- /dev/null +++ b/tools/tapeout/src/main/scala/macrolib/FlipChipMacro.scala @@ -0,0 +1,72 @@ +package mdf.macrolib + +import play.api.libs.json._ +import scala.collection.mutable.ListBuffer +import scala.language.implicitConversions + +// Flip Chip Macro +case class FlipChipMacro( + name: String, + bumpDimensions: (Int, Int), + bumpLocations: Seq[Seq[String]]) + extends Macro { + override def toJSON(): JsObject = { + + val output = new ListBuffer[(String, JsValue)]() + output.appendAll( + Seq( + "name" -> Json.toJson(name), + "type" -> Json.toJson(typeStr), + "bump_dimensions" -> JsArray(Seq(bumpDimensions._1, bumpDimensions._2).map { JsNumber(_) }), + "bump_locations" -> JsArray(bumpLocations.map(l => JsArray(l.map(JsString)))) + ) + ) + + JsObject(output) + } + val maxIONameSize = bumpLocations.foldLeft(0) { (size, row) => + row.foldLeft(size) { (size, str) => scala.math.max(size, str.length) } + } + def visualize: String = { + val output = new StringBuffer() + for (x <- 0 until bumpDimensions._1) { + for (y <- 0 until bumpDimensions._2) { + val name = bumpLocations(x)(y).drop(1).dropRight(1) + val extra = maxIONameSize - name.length() + val leftSpace = " " * (extra / 2) + val rightSpace = " " * (extra / 2 + extra % 2) + output.append(leftSpace + name + rightSpace + "|") + } + output.append("\n") + } + output.toString() + } + + override def typeStr = "flipchip" +} + +object FlipChipMacro { + def parseJSON(json: Map[String, JsValue]): Option[FlipChipMacro] = { + val name: String = json.get("name") match { + case Some(x: JsString) => x.as[String] + case _ => return None + } + + val bumpDimensions: (Int, Int) = json.get("bump_dimensions") match { + case Some(JsArray(x)) if x.size == 2 => + val z = x.map(_.as[JsNumber].value.intValue) + (z(0), z(1)) + case None => return None + } + val bumpLocations: Seq[Seq[String]] = json.get("bump_locations") match { + case Some(JsArray(array)) => + array.collect { case JsArray(a2) => a2.map(_.toString).toSeq }.toSeq + case _ => return None + } + // Can't have dimensions and locations which don't match + if (bumpLocations.size != bumpDimensions._1) return None + if (bumpLocations.collect { case x if x.size != bumpDimensions._2 => x }.nonEmpty) return None + + Some(FlipChipMacro(name, bumpDimensions, bumpLocations)) + } +} diff --git a/tools/tapeout/src/main/scala/macrolib/IOMacro.scala b/tools/tapeout/src/main/scala/macrolib/IOMacro.scala new file mode 100644 index 00000000..3f8ead8c --- /dev/null +++ b/tools/tapeout/src/main/scala/macrolib/IOMacro.scala @@ -0,0 +1,147 @@ +package mdf.macrolib + +import play.api.libs.json._ +import scala.collection.mutable.ListBuffer +import scala.language.implicitConversions + +sealed abstract class PortType { def toJSON(): JsString = JsString(toString) } +case object Digital extends PortType { override def toString: String = "digital" } +case object Analog extends PortType { override def toString: String = "analog" } +case object Power extends PortType { override def toString: String = "power" } +case object Ground extends PortType { override def toString: String = "ground" } +case object NoConnect extends PortType { override def toString: String = "NC" } + +sealed abstract class Direction { def toJSON(): JsString = JsString(toString) } +case object Input extends Direction { override def toString: String = "input" } +case object Output extends Direction { override def toString: String = "output" } +case object InOut extends Direction { override def toString: String = "inout" } + +sealed abstract class Termination { def toJSON(): JsValue } +case object CMOS extends Termination { override def toJSON(): JsString = JsString("CMOS") } +case class Resistive(ohms: Int) extends Termination { override def toJSON(): JsNumber = JsNumber(ohms) } + +sealed abstract class TerminationType { def toJSON(): JsString } +case object Single extends TerminationType { override def toJSON(): JsString = JsString("single") } +case object Differential extends TerminationType { override def toJSON(): JsString = JsString("differential") } + +// IO macro +case class IOMacro( + name: String, + tpe: PortType, + direction: Option[Direction] = None, + termination: Option[Termination] = None, + terminationType: Option[TerminationType] = None, + terminationReference: Option[String] = None, + matching: Seq[String] = Seq.empty[String], + bbname: Option[String] = None) + extends Macro { + override def toJSON(): JsObject = { + + val output = new ListBuffer[(String, JsValue)]() + output.appendAll( + Seq( + "name" -> Json.toJson(name), + "type" -> tpe.toJSON() + ) + ) + if (direction.isDefined) output.append("direction" -> direction.get.toJSON) + if (termination.isDefined) output.append("termination" -> termination.get.toJSON) + if (terminationType.isDefined) output.append("terminationType" -> terminationType.get.toJSON) + if (terminationReference.isDefined) output.append("terminationReference" -> JsString(terminationReference.get)) + if (matching.nonEmpty) output.append("match" -> JsArray(matching.map(JsString))) + if (bbname.nonEmpty) output.append("blackBox" -> JsString(bbname.get)) + + JsObject(output) + } + + override def typeStr = "iomacro" +} +object IOMacro { + def parseJSON(json: Map[String, JsValue]): Option[IOMacro] = { + val name: String = json.get("name") match { + case Some(x: JsString) => x.as[String] + case _ => return None + } + val tpe: PortType = json.get("type") match { + case Some(JsString("power")) => Power + case Some(JsString("ground")) => Ground + case Some(JsString("digital")) => Digital + case Some(JsString("analog")) => Analog + case Some(JsString("NC")) => NoConnect + case _ => return None + } + val direction: Option[Direction] = json.get("direction") match { + case Some(JsString("input")) => Some(Input) + case Some(JsString("output")) => Some(Output) + case Some(JsString("inout")) => Some(InOut) + case _ => None + } + val termination: Option[Termination] = json.get("termination") match { + case Some(JsNumber(x)) => Some(Resistive(x.toInt)) + case Some(JsString("CMOS")) => Some(CMOS) + case _ => None + } + val terminationType: Option[TerminationType] = json.get("terminationType") match { + case Some(JsString("differential")) => Some(Differential) + case Some(JsString("single")) => Some(Single) + case _ => None + } + val terminationRef: Option[String] = json.get("terminationReference") match { + case Some(JsString(x)) => Some(x) + case _ if terminationType.isDefined => return None + case _ => None + } + val matching: Seq[String] = json.get("match") match { + case Some(JsArray(array)) => array.map(_.as[JsString].value).toList + case _ => Seq.empty[String] + } + val bbname: Option[String] = json.get("blackBox") match { + case Some(JsString(module)) => Some(module) + case Some(_) => return None + case _ => None + } + Some(IOMacro(name, tpe, direction, termination, terminationType, terminationRef, matching, bbname)) + } +} + +case class IOProperties(name: String, top: String, ios: Seq[IOMacro]) extends Macro { + override def toJSON(): JsObject = { + val output = new ListBuffer[(String, JsValue)]() + output.appendAll( + Seq( + "name" -> Json.toJson(name), + "top" -> Json.toJson(top), + "type" -> Json.toJson(typeStr), + "ios" -> JsArray(ios.map(_.toJSON)) + ) + ) + JsObject(output) + } + + override def typeStr = "io_properties" + +} + +object IOProperties { + def parseJSON(json: Map[String, JsValue]): Option[IOProperties] = { + val name: String = json.get("name") match { + case Some(x: JsString) => x.as[String] + case _ => return None + } + val top: String = json.get("top") match { + case Some(x: JsString) => x.as[String] + case _ => return None + } + val ios: Seq[IOMacro] = json.get("ios") match { + case Some(x: JsArray) => + x.as[List[Map[String, JsValue]]].map { a => + val b = IOMacro.parseJSON(a); + if (b == None) { + return None + } else b.get + } + case _ => List() + } + Some(IOProperties(name, top, ios)) + } +} diff --git a/tools/tapeout/src/main/scala/macrolib/MacroLib.scala b/tools/tapeout/src/main/scala/macrolib/MacroLib.scala new file mode 100644 index 00000000..569c4dac --- /dev/null +++ b/tools/tapeout/src/main/scala/macrolib/MacroLib.scala @@ -0,0 +1,19 @@ +package mdf.macrolib + +import play.api.libs.json._ +import scala.collection.mutable.ListBuffer +import scala.language.implicitConversions + +// TODO: decide if we should always silently absorb errors + +// See macro_format.yml for the format description. + +// "Base class" for macros +abstract class Macro { + def name: String + + // Type of macro is determined by subclass + def typeStr: String + + def toJSON(): JsObject +} diff --git a/tools/tapeout/src/main/scala/macrolib/SRAM.scala b/tools/tapeout/src/main/scala/macrolib/SRAM.scala new file mode 100644 index 00000000..ea51b049 --- /dev/null +++ b/tools/tapeout/src/main/scala/macrolib/SRAM.scala @@ -0,0 +1,444 @@ +package mdf.macrolib + +import play.api.libs.json._ +import scala.collection.mutable.ListBuffer +import scala.language.implicitConversions + +// SRAM macro +case class SRAMMacro( + name: String, + width: Int, + depth: BigInt, + family: String, + ports: Seq[MacroPort], + vt: String = "", + mux: Int = 1, + extraPorts: Seq[MacroExtraPort] = List()) + extends Macro { + override def toJSON(): JsObject = { + val output = new ListBuffer[(String, JsValue)]() + output.appendAll( + Seq( + "type" -> JsString("sram"), + "name" -> Json.toJson(name), + "width" -> Json.toJson(width), + "depth" -> Json.toJson(depth.toString), + "mux" -> Json.toJson(mux), + "mask" -> Json.toJson(ports.exists(p => p.maskPort.isDefined)), + "ports" -> JsArray(ports.map { _.toJSON }) + ) + ) + if (family != "") { + output.appendAll(Seq("family" -> Json.toJson(family))) + } + if (vt != "") { + output.appendAll(Seq("vt" -> Json.toJson(vt))) + } + if (extraPorts.length > 0) { + output.appendAll(Seq("extra ports" -> JsArray(extraPorts.map { _.toJSON }))) + } + + JsObject(output) + } + + override def typeStr = "sram" +} +object SRAMMacro { + def parseJSON(json: Map[String, JsValue]): Option[SRAMMacro] = { + val name: String = json.get("name") match { + case Some(x: JsString) => x.as[String] + case _ => return None + } + val width: Int = json.get("width") match { + case Some(x: JsNumber) => x.value.intValue + case _ => return None + } + val depth: BigInt = json.get("depth") match { + case Some(x: JsString) => + try { BigInt(x.as[String]) } + catch { case _: Throwable => return None } + case _ => return None + } + val family: String = json.get("family") match { + case Some(x: JsString) => x.as[String] + case _ => "" // optional + } + val vt: String = json.get("vt") match { + case Some(x: JsString) => x.as[String] + case _ => "" // optional + } + val mux: Int = json.get("mux") match { + case Some(x: JsNumber) => x.value.intValue + case _ => 1 // default + } + val ports: Seq[MacroPort] = json.get("ports") match { + case Some(x: JsArray) => + x.as[List[Map[String, JsValue]]].map { a => + val b = MacroPort.parseJSON(a, width, depth); + if (b == None) { + return None + } else b.get + } + case _ => List() + } + if (ports.length == 0) { + // Can't have portless memories. + return None + } + val extraPorts: Seq[MacroExtraPort] = json.get("extra ports") match { + case Some(x: JsArray) => + x.as[List[Map[String, JsValue]]].map { a => + val b = MacroExtraPort.parseJSON(a); + if (b == None) { + return None + } else b.get + } + case _ => List() + } + Some(SRAMMacro(name, width, depth, family, ports, vt, mux, extraPorts)) + } +} + +// SRAM compiler +case class SRAMGroup( + name: Seq[String], + family: String, + vt: Seq[String], + mux: Int, + depth: Range, + width: Range, + ports: Seq[MacroPort], + extraPorts: Seq[MacroExtraPort] = List()) { + def toJSON: JsObject = { + val output = new ListBuffer[(String, JsValue)]() + output.appendAll( + Seq( + "name" -> JsArray(name.map(Json.toJson(_))), + "vt" -> JsArray(vt.map(Json.toJson(_))), + "mux" -> Json.toJson(mux), + "depth" -> JsArray(Seq(depth.start, depth.end, depth.step).map { x => Json.toJson(x) }), + "width" -> JsArray(Seq(width.start, width.end, width.step).map { x => Json.toJson(x) }), + "ports" -> JsArray(ports.map { _.toJSON }) + ) + ) + if (family != "") { + output.appendAll(Seq("family" -> Json.toJson(family))) + } + if (extraPorts.length > 0) { + output.appendAll(Seq("extra ports" -> JsArray(extraPorts.map { _.toJSON }))) + } + JsObject(output) + } +} +object SRAMGroup { + def parseJSON(json: Map[String, JsValue]): Option[SRAMGroup] = { + val family: String = json.get("family") match { + case Some(x: JsString) => x.as[String] + case _ => "" // optional + } + val name: Seq[String] = json.get("name") match { + case Some(x: JsArray) => x.as[List[JsString]].map(_.as[String]) + case _ => return None + } + val vt: Seq[String] = json.get("vt") match { + case Some(x: JsArray) => x.as[List[JsString]].map(_.as[String]) + case _ => return None + } + val mux: Int = json.get("mux") match { + case Some(x: JsNumber) => x.value.intValue + case _ => return None + } + val depth: Range = json.get("depth") match { + case Some(x: JsArray) => + val seq = x.as[List[JsNumber]].map(_.value.intValue) + Range.inclusive(seq(0), seq(1), seq(2)) + case _ => return None + } + val width: Range = json.get("width") match { + case Some(x: JsArray) => + val seq = x.as[List[JsNumber]].map(_.value.intValue) + Range.inclusive(seq(0), seq(1), seq(2)) + case _ => return None + } + val ports: Seq[MacroPort] = json.get("ports") match { + case Some(x: JsArray) => + x.as[List[Map[String, JsValue]]].map { a => + { + val b = MacroPort.parseJSON(a, None, None); + if (b == None) { + return None + } else b.get + } + } + case _ => List() + } + if (ports.length == 0) { + // Can't have portless memories. + return None + } + val extraPorts: Seq[MacroExtraPort] = json.get("extra ports") match { + case Some(x: JsArray) => + x.as[List[Map[String, JsValue]]].map { a => + { + val b = MacroExtraPort.parseJSON(a); + if (b == None) { + return None + } else b.get + } + } + case _ => List() + } + Some(SRAMGroup(name, family, vt, mux, depth, width, ports, extraPorts)) + } +} + +case class SRAMCompiler( + name: String, + groups: Seq[SRAMGroup]) + extends Macro { + override def toJSON(): JsObject = { + val output = new ListBuffer[(String, JsValue)]() + output.appendAll( + Seq( + "type" -> Json.toJson("sramcompiler"), + "name" -> Json.toJson(name), + "groups" -> JsArray(groups.map { _.toJSON }) + ) + ) + + JsObject(output) + } + + override def typeStr = "sramcompiler" +} +object SRAMCompiler { + def parseJSON(json: Map[String, JsValue]): Option[SRAMCompiler] = { + val name: String = json.get("name") match { + case Some(x: JsString) => x.as[String] + case _ => return None + } + val groups: Seq[SRAMGroup] = json.get("groups") match { + case Some(x: JsArray) => + x.as[List[Map[String, JsValue]]].map { a => + { + val b = SRAMGroup.parseJSON(a); + if (b == None) { return None } + else b.get + } + } + case _ => List() + } + if (groups.length == 0) { + // Can't have portless memories. + return None + } + Some(SRAMCompiler(name, groups)) + } +} + +// Type of extra port +sealed abstract class MacroExtraPortType +case object Constant extends MacroExtraPortType +object MacroExtraPortType { + implicit def toMacroExtraPortType(s: Any): Option[MacroExtraPortType] = { + s match { + case "constant" => Some(Constant) + case _ => None + } + } + + implicit def toString(t: MacroExtraPortType): String = { + t match { + case Constant => "constant" + case _ => "" + } + } +} + +// Extra port in SRAM +case class MacroExtraPort( + name: String, + width: Int, + portType: MacroExtraPortType, + value: BigInt) { + def toJSON(): JsObject = { + JsObject( + Seq( + "name" -> Json.toJson(name), + "width" -> Json.toJson(width), + "type" -> JsString(MacroExtraPortType.toString(portType)), + "value" -> JsNumber(BigDecimal(value)) + ) + ) + } +} +object MacroExtraPort { + def parseJSON(json: Map[String, JsValue]): Option[MacroExtraPort] = { + val name = json.get("name") match { + case Some(x: JsString) => x.value + case _ => return None + } + val width = json.get("width") match { + case Some(x: JsNumber) => x.value.intValue + case _ => return None + } + val portType: MacroExtraPortType = json.get("type") match { + case Some(x: JsString) => + MacroExtraPortType.toMacroExtraPortType(x.value) match { + case Some(t: MacroExtraPortType) => t + case _ => return None + } + case _ => return None + } + val value = json.get("value") match { + case Some(x: JsNumber) => x.value.toBigInt + case _ => return None + } + Some(MacroExtraPort(name, width, portType, value)) + } +} + +// A named port that also has polarity. +case class PolarizedPort(name: String, polarity: PortPolarity) { + def toSeqMap(prefix: String): Seq[Tuple2[String, JsValue]] = { + Seq( + prefix + " port name" -> Json.toJson(name), + prefix + " port polarity" -> JsString(polarity) + ) + } +} +object PolarizedPort { + // Parse a pair of " port name" and " port polarity" keys into a + // polarized port definition. + def parseJSON(json: Map[String, JsValue], prefix: String): Option[PolarizedPort] = { + val name = json.get(prefix + " port name") match { + case Some(x: JsString) => Some(x.value) + case _ => None + } + val polarity: Option[PortPolarity] = json.get(prefix + " port polarity") match { + case Some(x: JsString) => Some(x.value) + case _ => None + } + + (name, polarity) match { + case (Some(n: String), Some(p: PortPolarity)) => Some(PolarizedPort(n, p)) + case _ => None + } + } +} + +// A SRAM memory port +case class MacroPort( + address: PolarizedPort, + clock: Option[PolarizedPort] = None, + writeEnable: Option[PolarizedPort] = None, + readEnable: Option[PolarizedPort] = None, + chipEnable: Option[PolarizedPort] = None, + output: Option[PolarizedPort] = None, + input: Option[PolarizedPort] = None, + maskPort: Option[PolarizedPort] = None, + maskGran: Option[Int] = None, + // For internal use only; these aren't port-specific. + width: Option[Int], + depth: Option[BigInt]) { + def effectiveMaskGran = maskGran.getOrElse(width.get) + + def toJSON(): JsObject = { + val keys: Seq[Tuple2[String, Option[Any]]] = Seq( + "address" -> Some(address), + "clock" -> clock, + "write enable" -> writeEnable, + "read enable" -> readEnable, + "chip enable" -> chipEnable, + "output" -> output, + "input" -> input, + "mask" -> maskPort, + "mask granularity" -> maskGran + ) + JsObject(keys.flatMap(k => { + val (key, value) = k + value match { + case Some(x: Int) => Seq(key -> JsNumber(x)) + case Some(x: PolarizedPort) => x.toSeqMap(key) + case _ => List() + } + })) + } + + // Check that all port names are unique. + private val polarizedPorts = + List(Some(address), clock, writeEnable, readEnable, chipEnable, output, input, maskPort).flatten + assert(polarizedPorts.distinct.size == polarizedPorts.size, "All port names must be unique") +} +object MacroPort { + def parseJSON(json: Map[String, JsValue]): Option[MacroPort] = parseJSON(json, None, None) + def parseJSON(json: Map[String, JsValue], width: Int, depth: BigInt): Option[MacroPort] = + parseJSON(json, Some(width), Some(depth)) + def parseJSON(json: Map[String, JsValue], width: Option[Int], depth: Option[BigInt]): Option[MacroPort] = { + val address = PolarizedPort.parseJSON(json, "address") + if (address == None) { + return None + } + + val clock = PolarizedPort.parseJSON(json, "clock") + // TODO: validate based on family (e.g. 1rw must have a write enable, etc) + val writeEnable = PolarizedPort.parseJSON(json, "write enable") + val readEnable = PolarizedPort.parseJSON(json, "read enable") + val chipEnable = PolarizedPort.parseJSON(json, "chip enable") + + val output = PolarizedPort.parseJSON(json, "output") + val input = PolarizedPort.parseJSON(json, "input") + + val maskPort = PolarizedPort.parseJSON(json, "mask") + val maskGran: Option[Int] = json.get("mask granularity") match { + case Some(x: JsNumber) => Some(x.value.intValue) + case _ => None + } + + if (maskPort.isDefined != maskGran.isDefined) { + return None + } + + Some( + MacroPort( + width = width, + depth = depth, + address = address.get, + clock = clock, + writeEnable = writeEnable, + readEnable = readEnable, + chipEnable = chipEnable, + output = output, + input = input, + maskPort = maskPort, + maskGran = maskGran + ) + ) + } +} + +// Port polarity +trait PortPolarity +case object ActiveLow extends PortPolarity +case object ActiveHigh extends PortPolarity +case object NegativeEdge extends PortPolarity +case object PositiveEdge extends PortPolarity +object PortPolarity { + implicit def toPortPolarity(s: String): PortPolarity = (s: @unchecked) match { + case "active low" => ActiveLow + case "active high" => ActiveHigh + case "negative edge" => NegativeEdge + case "positive edge" => PositiveEdge + } + implicit def toPortPolarity(s: Option[String]): Option[PortPolarity] = + s.map(toPortPolarity) + + implicit def toString(p: PortPolarity): String = { + p match { + case ActiveLow => "active low" + case ActiveHigh => "active high" + case NegativeEdge => "negative edge" + case PositiveEdge => "positive edge" + } + } +} diff --git a/tools/tapeout/src/main/scala/macrolib/Utils.scala b/tools/tapeout/src/main/scala/macrolib/Utils.scala new file mode 100644 index 00000000..547f910c --- /dev/null +++ b/tools/tapeout/src/main/scala/macrolib/Utils.scala @@ -0,0 +1,96 @@ +package mdf.macrolib + +import play.api.libs.json._ + +import java.io.FileNotFoundException +import scala.collection.mutable.ListBuffer +import scala.language.implicitConversions + +object Utils { + // Read a MDF file from a String. + def readMDFFromString(str: String): Option[Seq[Macro]] = { + Json.parse(str) match { + // Make sure that the document is a list. + case arr: JsArray => { + val result: List[Option[Macro]] = arr.as[List[Map[String, JsValue]]].map { obj => + // Check the type of object. + val objTypeStr: String = obj.get("type") match { + case Some(x: JsString) => x.as[String] + case _ => return None // error, no type found + } + objTypeStr match { + case "filler cell" | "metal filler cell" => FillerMacroBase.parseJSON(obj) + case "sram" => SRAMMacro.parseJSON(obj) + case "sramcompiler" => SRAMCompiler.parseJSON(obj) + case "io_properties" => IOProperties.parseJSON(obj) + case "flipchip" => FlipChipMacro.parseJSON(obj) + case _ => None // skip unknown macro types + } + } + // Remove all the Nones and convert back to Seq[Macro] + Some(result.filter { x => x != None }.map { x => x.get }) + } + case _ => None + } + } + + // Read a MDF file from a path. + def readMDFFromPath(path: Option[String]): Option[Seq[Macro]] = { + path match { + case None => None + // Read file into string and parse + case Some(p) => + try { + Utils.readMDFFromString(scala.io.Source.fromFile(p).mkString) + } catch { + case f: FileNotFoundException => + println(s"FILE NOT FOUND $p in dir ${os.pwd}") + throw f + } + } + } + + // Write a MDF file to a String. + def writeMDFToString(s: Seq[Macro]): String = { + Json.prettyPrint(JsArray(s.map(_.toJSON))) + } + + // Write a MDF file from a path. + // Returns true upon success. + def writeMDFToPath(path: Option[String], s: Seq[Macro]): Boolean = { + path match { + case None => false + // Read file into string and parse + case Some(p: String) => { + import java.io._ + val pw = new PrintWriter(new File(p)) + pw.write(writeMDFToString(s)) + val error = pw.checkError + pw.close() + !error + } + } + } + + // Write a macro file to a String. + def writeMacroToString(s: Macro): String = { + Json.prettyPrint(s.toJSON) + } + + // Write a Macro file from a path. + // Returns true upon success. + def writeMacroToPath(path: Option[String], s: Macro): Boolean = { + path match { + case None => false + // Read file into string and parse + case Some(p: String) => { + import java.io._ + val pw = new PrintWriter(new File(p)) + pw.write(writeMacroToString(s)) + val error = pw.checkError + pw.close() + !error + } + } + } +} diff --git a/tools/tapeout/src/main/scala/macros/CostMetric.scala b/tools/tapeout/src/main/scala/macros/CostMetric.scala new file mode 100644 index 00000000..1be33967 --- /dev/null +++ b/tools/tapeout/src/main/scala/macros/CostMetric.scala @@ -0,0 +1,205 @@ +// See LICENSE for license details. + +package tapeout.macros + +/** Trait which can calculate the cost of compiling a memory against a certain + * library memory macro using a cost function. + */ +// TODO: eventually explore compiling a single target memory using multiple +// different kinds of target memory. +trait CostMetric extends Serializable { + + /** Cost function that returns the cost of compiling a memory using a certain + * macro. + * + * @param mem Memory macro to compile (target memory) + * @param lib Library memory macro to use (library memory) + * @return The cost of this compile, defined by this cost metric, or None if + * it cannot be compiled. + */ + def cost(mem: Macro, lib: Macro): Option[Double] + + /** Helper function to return the map of arguments (or an empty map if there are none). + */ + def commandLineParams(): Map[String, String] + + // We also want this to show up for the class itself. + def name(): String +} + +// Is there a better way to do this? (static method associated to CostMetric) +trait CostMetricCompanion { + def name(): String + + /** Construct this cost metric from a command line mapping. */ + def construct(m: Map[String, String]): CostMetric +} + +// Some default cost functions. + +/** Palmer's old metric. + * TODO: figure out what is the difference between this metric and the current + * default metric and either revive or delete this metric. + */ +object OldMetric extends CostMetric with CostMetricCompanion { + override def cost(mem: Macro, lib: Macro): Option[Double] = { + /* Palmer: A quick cost function (that must be kept in sync with + * memory_cost()) that attempts to avoid compiling unnecessary + * memories. This is a lower bound on the cost of compiling a + * memory: it assumes 100% bit-cell utilization when mapping. */ + // val cost = 100 * (mem.depth * mem.width) / (lib.depth * lib.width) + + // (mem.depth * mem.width) + ??? + } + + override def commandLineParams() = Map.empty[String, String] + override def name() = "OldMetric" + override def construct(m: Map[String, String]): CostMetric = OldMetric +} + +/** An external cost function. + * Calls the specified path with paths to the JSON MDF representation of the mem + * and lib macros. The external executable should print a Double. + * None will be returned if the external executable does not print a valid + * Double. + */ +class ExternalMetric(path: String) extends CostMetric { + import mdf.macrolib.Utils.writeMacroToPath + + import java.io._ + import scala.language.postfixOps + import sys.process._ + + override def cost(mem: Macro, lib: Macro): Option[Double] = { + // Create temporary files. + val memFile = File.createTempFile("_macrocompiler_mem_", ".json") + val libFile = File.createTempFile("_macrocompiler_lib_", ".json") + + writeMacroToPath(Some(memFile.getAbsolutePath), mem.src) + writeMacroToPath(Some(libFile.getAbsolutePath), lib.src) + + // !! executes the given command + val result: String = (s"$path ${memFile.getAbsolutePath} ${libFile.getAbsolutePath}" !!).trim + + // Remove temporary files. + memFile.delete() + libFile.delete() + + try { + Some(result.toDouble) + } catch { + case _: NumberFormatException => None + } + } + + override def commandLineParams() = Map("path" -> path) + override def name(): String = ExternalMetric.name() +} + +object ExternalMetric extends CostMetricCompanion { + override def name() = "ExternalMetric" + + /** Construct this cost metric from a command line mapping. */ + override def construct(m: Map[String, String]): ExternalMetric = { + val pathOption = m.get("path") + pathOption match { + case Some(path: String) => new ExternalMetric(path) + case _ => throw new IllegalArgumentException("ExternalMetric missing option 'path'") + } + } +} + +/** The current default metric in barstools, re-defined by Donggyu. */ +// TODO: write tests for this function to make sure it selects the right things +object DefaultMetric extends CostMetric with CostMetricCompanion { + override def cost(mem: Macro, lib: Macro): Option[Double] = { + val memMask = mem.src.ports.map(_.maskGran).find(_.isDefined).flatten + val libMask = lib.src.ports.map(_.maskGran).find(_.isDefined).flatten + val memWidth = (memMask, libMask) match { + case (None, _) => mem.src.width + case (Some(p), None) => + (mem.src.width / p) * math.ceil( + p.toDouble / lib.src.width + ) * lib.src.width //We map the mask to distinct memories + case (Some(p), Some(m)) => + if (m <= p) (mem.src.width / p) * math.ceil(p.toDouble / m) * m //Using multiple m's to create a p (integrally) + else (mem.src.width / p) * m //Waste the extra maskbits + } + val maskPenalty = (memMask, libMask) match { + case (None, Some(_)) => 0.001 + case (_, _) => 0 + } + val depthCost = math.ceil(mem.src.depth.toDouble / lib.src.depth.toDouble) + val widthCost = math.ceil(memWidth / lib.src.width.toDouble) + val bitsCost = (lib.src.depth * lib.src.width).toDouble + // Fraction of wasted bits plus const per mem + val requestedBits = (mem.src.depth * mem.src.width).toDouble + val bitsWasted = depthCost * widthCost * bitsCost - requestedBits + val wastedConst = 0.05 // 0 means waste as few bits with no regard for instance count + val costPerInst = wastedConst * depthCost * widthCost + Some(1.0 * bitsWasted / requestedBits + costPerInst + maskPenalty) + } + + override def commandLineParams() = Map.empty[String, String] + override def name() = "DefaultMetric" + override def construct(m: Map[String, String]): CostMetric = DefaultMetric +} + +object MacroCompilerUtil { + import java.io._ + import java.util.Base64 + + // Adapted from https://stackoverflow.com/a/134918 + + /** Serialize an arbitrary object to String. + * Used to pass structured values through as an annotation. + */ + def objToString(o: Serializable): String = { + val byteOutput: ByteArrayOutputStream = new ByteArrayOutputStream + val objectOutput: ObjectOutputStream = new ObjectOutputStream(byteOutput) + objectOutput.writeObject(o) + objectOutput.close() + Base64.getEncoder.encodeToString(byteOutput.toByteArray) + } + + /** Deserialize an arbitrary object from String. */ + def objFromString(s: String): AnyRef = { + val data = Base64.getDecoder.decode(s) + val ois: ObjectInputStream = new ObjectInputStream(new ByteArrayInputStream(data)) + val o = ois.readObject + ois.close() + o + } +} + +object CostMetric { + + /** Define some default metric. */ + val default: CostMetric = DefaultMetric + + val costMetricCreators: scala.collection.mutable.Map[String, CostMetricCompanion] = scala.collection.mutable.Map() + + // Register some default metrics + registerCostMetric(OldMetric) + registerCostMetric(ExternalMetric) + registerCostMetric(DefaultMetric) + + /** Register a cost metric. + * @param createFuncHelper Companion object to fetch the name and construct + * the metric. + */ + def registerCostMetric(createFuncHelper: CostMetricCompanion): Unit = { + costMetricCreators.update(createFuncHelper.name(), createFuncHelper) + } + + /** Select a cost metric from string. */ + def getCostMetric(m: String, params: Map[String, String]): CostMetric = { + if (m == "default") { + CostMetric.default + } else if (!costMetricCreators.contains(m)) { + throw new IllegalArgumentException("Invalid cost metric " + m) + } else { + costMetricCreators(m).construct(params) + } + } +} diff --git a/tools/tapeout/src/main/scala/macros/MacroCompiler.scala b/tools/tapeout/src/main/scala/macros/MacroCompiler.scala new file mode 100644 index 00000000..fbf857fe --- /dev/null +++ b/tools/tapeout/src/main/scala/macros/MacroCompiler.scala @@ -0,0 +1,981 @@ +// See LICENSE for license details. + +/** Terminology note: + * mem - target memory to compile, in design (e.g. Mem() in rocket) + * lib - technology SRAM(s) to use to compile mem + */ + +package tapeout.macros + +import tapeout.macros.Utils._ +import firrtl.Utils.{one, zero, BoolType} +import firrtl.annotations._ +import firrtl.ir._ +import firrtl.options.Dependency +import firrtl.stage.TransformManager.TransformDependency +import firrtl.stage.{FirrtlSourceAnnotation, FirrtlStage, Forms, OutputFileAnnotation, RunFirrtlTransformAnnotation} +import firrtl.{PrimOps, _} +import mdf.macrolib.{PolarizedPort, PortPolarity, SRAMCompiler, SRAMGroup, SRAMMacro} + +import java.io.{File, FileWriter} +import scala.annotation.tailrec +import scala.collection.mutable +import scala.collection.mutable.ArrayBuffer + +case class MacroCompilerException(msg: String) extends Exception(msg) + +// TODO The parameters could be unpacked here instead of keeping it in a serialized form +case class MacroCompilerAnnotation(content: String) extends NoTargetAnnotation { + import MacroCompilerAnnotation.Params + + def params: Params = MacroCompilerUtil.objFromString(content).asInstanceOf[Params] +} + +/** The MacroCompilerAnnotation to trigger the macro compiler. + * Note that this annotation does NOT actually target any modules for + * compilation. It simply holds all the settings for the memory compiler. The + * actual selection of which memories to compile is set in the Params. + * + * To use, simply annotate the entire circuit itself with this annotation and + * include [[MacroCompilerTransform]]. + */ +object MacroCompilerAnnotation { + + /** Macro compiler mode. */ + sealed trait CompilerMode + + /** Strict mode - must compile all memories or error out. */ + case object Strict extends CompilerMode + + /** Synflops mode - compile all memories with synflops (do not map to lib at all). */ + case object Synflops extends CompilerMode + + /** CompileAndSynflops mode - compile all memories and create mock versions of the target libs with synflops. */ + case object CompileAndSynflops extends CompilerMode + + /** FallbackSynflops - compile all memories to SRAM when possible and fall back to synflops if a memory fails. * */ + case object FallbackSynflops extends CompilerMode + + /** CompileAvailable - compile what is possible and do nothing with uncompiled memories. * */ + case object CompileAvailable extends CompilerMode + + /** The default mode for the macro compiler. + * TODO: Maybe set the default to FallbackSynflops (typical for + * vlsi_mem_gen-like scripts) once it's implemented? + */ + val Default: CompilerMode = CompileAvailable + + // Options as list of (CompilerMode, command-line name, description) + val options: Seq[(CompilerMode, String, String)] = Seq( + (Default, "default", "Select the default option from below."), + (Strict, "strict", "Compile all memories to library or return an error."), + ( + Synflops, + "synflops", + "Produces synthesizable flop-based memories for all memories (do not map to lib at all); likely useful for simulation purposes." + ), + ( + CompileAndSynflops, + "compileandsynflops", + "Compile all memories and create mock versions of the target libs with synflops; likely also useful for simulation purposes." + ), + ( + FallbackSynflops, + "fallbacksynflops", + "Compile all memories to library when possible and fall back to synthesizable flop-based memories when library synth is not possible." + ), + ( + CompileAvailable, + "compileavailable", + "Compile all memories to library when possible and do nothing in case of errors. (default)" + ) + ) + + /** Helper function to select a compiler mode. */ + def stringToCompilerMode(str: String): CompilerMode = options.collectFirst { + case (mode, cmd, _) if cmd == str => mode + } match { + case Some(x) => x + case None => throw new IllegalArgumentException("No such compiler mode " + str) + } + + /** Parameters associated to this MacroCompilerAnnotation. + * + * @param mem Path to memory lib + * @param memFormat Type of memory lib (Some("conf"), Some("mdf"), or None (defaults to mdf)) + * @param lib Path to library lib or None if no libraries + * @param hammerIR Path to HammerIR output or None (not generated in this case) + * @param costMetric Cost metric to use + * @param mode Compiler mode (see CompilerMode) + * @param forceCompile Set of memories to force compiling to lib regardless of the mode + * @param forceSynflops Set of memories to force compiling as flops regardless of the mode + */ + case class Params( + mem: String, + memFormat: Option[String], + lib: Option[String], + hammerIR: Option[String], + costMetric: CostMetric, + mode: CompilerMode, + useCompiler: Boolean, + forceCompile: Set[String], + forceSynflops: Set[String]) + extends Serializable + + /** Create a MacroCompilerAnnotation. + * @param c Top-level circuit name (see class description) + * @param p Parameters (see above). + */ + def apply(c: String, p: Params): MacroCompilerAnnotation = + MacroCompilerAnnotation(MacroCompilerUtil.objToString(p)) + +} + +class MacroCompilerPass( + mems: Option[Seq[Macro]], + libs: Option[Seq[Macro]], + compilers: Option[SRAMCompiler], + hammerIR: Option[String], + costMetric: CostMetric = CostMetric.default, + mode: MacroCompilerAnnotation.CompilerMode = MacroCompilerAnnotation.Default) + extends firrtl.passes.Pass { + // Helper function to check the legality of bitPairs. + // e.g. ((0,21), (22,43)) is legal + // ((0,21), (22,21)) is illegal and will throw an assert + private def checkBitPairs(bitPairs: Seq[(BigInt, BigInt)]): Unit = { + bitPairs.foldLeft(BigInt(-1))((lastBit, nextPair) => { + assert(lastBit + 1 == nextPair._1, s"Pair's first bit ${nextPair._1} does not follow last bit $lastBit") + assert(nextPair._2 >= nextPair._1, s"Pair $nextPair in bitPairs $bitPairs is illegal") + nextPair._2 + }) + } + + /** Calculate bit pairs. + * This is a list of submemories by width. + * The tuples are (lsb, msb) inclusive. + * Example: (0, 7) and (8, 15) might be a split for a width=16 memory into two width=8 target memories. + * Another example: (0, 3), (4, 7), (8, 11) may be a split for a width-12 memory into 3 width-4 target memories. + * + * @param mem Memory to compile + * @param lib Lib to compile with + * @return Bit pairs or empty list if there was an error. + */ + private def calculateBitPairs(mem: Macro, lib: Macro): Seq[(BigInt, BigInt)] = { + val pairedPorts = mem.sortedPorts.zip(lib.sortedPorts) + + val bitPairs = ArrayBuffer[(BigInt, BigInt)]() + var currentLSB: BigInt = 0 + + // Process every bit in the mem width. + for (memBit <- 0 until mem.src.width) { + val bitsInCurrentMem = memBit - currentLSB + + // We'll need to find a bitPair that works for *all* the ports of the memory. + // e.g. unmasked read port and masked write port. + // For each port, store a tentative candidate for the split. + // Afterwards, figure out which one to use. + val bitPairCandidates = ArrayBuffer[(BigInt, BigInt)]() + for ((memPort, libPort) <- pairedPorts) { + + // Sanity check to make sure we only split once per bit, once per port. + var alreadySplit: Boolean = false + + // Helper function to check if it's time to split memories. + // @param effectiveLibWidth Split memory when we have this many bits. + def splitMemory(effectiveLibWidth: Int): Unit = { + assert(!alreadySplit) + + if (bitsInCurrentMem == effectiveLibWidth) { + bitPairCandidates += ((currentLSB, memBit - 1)) + alreadySplit = true + } + } + + // Make sure we don't have a maskGran larger than the width of the memory. + assert(memPort.src.effectiveMaskGran <= memPort.src.width.get) + assert(libPort.src.effectiveMaskGran <= libPort.src.width.get) + + val libWidth = libPort.src.width.get + + // Don't consider cases of maskGran == width as "masked" since those masks + // effectively function as write-enable bits. + val memMask = if (memPort.src.effectiveMaskGran == memPort.src.width.get) None else memPort.src.maskGran + val libMask = if (libPort.src.effectiveMaskGran == libPort.src.width.get) None else libPort.src.maskGran + + (memMask, libMask) match { + // Neither lib nor mem is masked. + // No problems here. + case (None, None) => splitMemory(libWidth) + + // Only the lib is masked. + // Not an issue; we can just make all the bits in the lib mask enabled. + case (None, Some(_)) => splitMemory(libWidth) + + // Only the mem is masked. + case (Some(p), None) => + if (p % libPort.src.width.get == 0) { + // If the mem mask is a multiple of the lib width, then we're good. + // Just roll over every lib width as usual. + // e.g. lib width=4, mem maskGran={4, 8, 12, 16, ...} + splitMemory(libWidth) + } else if (libPort.src.width.get % p == 0) { + // Lib width is a multiple of the mem mask. + // Consider the case where mem mask = 4 but lib width = 8, unmasked. + // We can still compile, but will need to waste the extra bits. + splitMemory(memMask.get) + } else { + // No neat multiples. + // We might still be able to compile extremely inefficiently. + if (p < libPort.src.width.get) { + // Compile using mem mask as the effective width. (note that lib is not masked) + // e.g. mem mask = 3, lib width = 8 + splitMemory(memMask.get) + } else { + // e.g. mem mask = 13, lib width = 8 + System.err.println( + s"Unmasked target memory: unaligned mem maskGran $p with lib (${lib.src.name}) width ${libPort.src.width.get} not supported" + ) + return Seq() + } + } + + // Both lib and mem are masked. + case (Some(m), Some(l)) => + if (m == l) { + // Lib maskGran == mem maskGran, no problems + splitMemory(libWidth) + } else if (m > l) { + // Mem maskGran > lib maskGran + if (m % l == 0) { + // Mem maskGran is a multiple of lib maskGran, carry on as normal. + splitMemory(libWidth) + } else { + System.err.println(s"Mem maskGran $m is not a multiple of lib maskGran $l: currently not supported") + return Seq() + } + } else { // m < l + // Lib maskGran > mem maskGran. + if (l % m == 0) { + // Lib maskGran is a multiple of mem maskGran. + // e.g. lib maskGran = 8, mem maskGran = 4. + // In this case we can only compile very wastefully (by treating + // lib as a mem maskGran width memory) :( + splitMemory(memMask.get) + + // TODO: there's an optimization that could allow us to pack more + // bits in and be more efficient. + // e.g. say if mem maskGran = 4, lib maskGran = 8, libWidth = 32 + // We could use 16 of bit (bits 0-3, 8-11, 16-19, 24-27) instead + // of treating it as simply a width 4 (!!!) memory. + // This would require a major refactor though. + } else { + System.err.println(s"Lib maskGran $m is not a multiple of mem maskGran $l: currently not supported") + return Seq() + } + } + } + } + + // Choose an actual bit pair to add. + // We'll have to choose the smallest one (e.g. unmasked read port might be more tolerant of a bigger split than the masked write port). + if (bitPairCandidates.isEmpty) { + // No pair needed to split, just continue + } else { + val bestPair = bitPairCandidates.reduceLeft((leftPair, rightPair) => { + if (leftPair._2 - leftPair._1 + 1 > rightPair._2 - rightPair._1 + 1) leftPair else rightPair + }) + bitPairs += bestPair + currentLSB = bestPair._2 + BigInt(1) // advance the LSB pointer + } + } + // Add in the last chunk if there are any leftovers + bitPairs += ((currentLSB, mem.src.width - 1)) + + bitPairs + }.toSeq + + def compile(mem: Macro, lib: Macro): Option[(Module, Macro)] = { + assert( + mem.sortedPorts.lengthCompare(lib.sortedPorts.length) == 0, + "mem and lib should have an equal number of ports" + ) + val pairedPorts = mem.sortedPorts.zip(lib.sortedPorts) + + // Width mapping. See calculateBitPairs. + val bitPairs: Seq[(BigInt, BigInt)] = calculateBitPairs(mem, lib) + if (bitPairs.isEmpty) { + System.err.println("Error occurred during bitPairs calculations (bitPairs is empty).") + return None + } + // Check bit pairs. + checkBitPairs(bitPairs) + + // Depth mapping + val stmts = ArrayBuffer[Statement]() + val outputs = mutable.HashMap[String, ArrayBuffer[(Expression, Expression)]]() + val selects = mutable.HashMap[String, Expression]() + val selectRegs = mutable.HashMap[String, Expression]() + /* Palmer: If we've got a parallel memory then we've got to take the + * address bits into account. */ + if (mem.src.depth > lib.src.depth) { + mem.src.ports.foreach { port => + val high = MacroCompilerMath.ceilLog2(mem.src.depth) + val low = MacroCompilerMath.ceilLog2(lib.src.depth) + val ref = WRef(port.address.name) + val nodeName = s"${ref.name}_sel" + val tpe = UIntType(IntWidth(high - low)) + selects(ref.name) = WRef(nodeName, tpe) + stmts += DefNode(NoInfo, nodeName, bits(ref, high - 1, low)) + // Donggyu: output selection should be piped + if (port.output.isDefined) { + val regName = s"${ref.name}_sel_reg" + val enable = (port.chipEnable, port.readEnable) match { + case (Some(ce), Some(re)) => + and(WRef(ce.name, BoolType), WRef(re.name, BoolType)) + case (Some(ce), None) => WRef(ce.name, BoolType) + case (None, Some(re)) => WRef(re.name, BoolType) + case (None, None) => one + } + selectRegs(ref.name) = WRef(regName, tpe) + stmts += DefRegister(NoInfo, regName, tpe, WRef(port.clock.get.name), zero, WRef(regName)) + stmts += Connect(NoInfo, WRef(regName), Mux(enable, WRef(nodeName), WRef(regName), tpe)) + } + } + } + for ((_, i) <- BigInt(0).until(mem.src.depth, lib.src.depth).zipWithIndex) { + for (j <- bitPairs.indices) { + val name = s"mem_${i}_$j" + // Create the instance. + stmts += WDefInstance(NoInfo, name, lib.src.name, lib.tpe) + // Connect extra ports of the lib. + stmts ++= lib.extraPorts.map { case (portName, portValue) => + Connect(NoInfo, WSubField(WRef(name), portName), portValue) + } + } + for ((memPort, libPort) <- pairedPorts) { + val addrMatch = selects.get(memPort.src.address.name) match { + case None => one + case Some(addr) => + val index = UIntLiteral(i, IntWidth(bitWidth(addr.tpe))) + DoPrim(PrimOps.Eq, Seq(addr, index), Nil, index.tpe) + } + val addrMatchReg = selectRegs.get(memPort.src.address.name) match { + case None => one + case Some(reg) => + val index = UIntLiteral(i, IntWidth(bitWidth(reg.tpe))) + DoPrim(PrimOps.Eq, Seq(reg, index), Nil, index.tpe) + } + def andAddrMatch(e: Expression) = { + and(e, addrMatch) + } + val cats = ArrayBuffer[Expression]() + for (((low, high), j) <- bitPairs.zipWithIndex) { + val inst = WRef(s"mem_${i}_$j", lib.tpe) + + def connectPorts2(mem: Expression, lib: String, polarity: Option[PortPolarity]): Statement = + Connect(NoInfo, WSubField(inst, lib), portToExpression(mem, polarity)) + def connectPorts(mem: Expression, lib: String, polarity: PortPolarity): Statement = + connectPorts2(mem, lib, Some(polarity)) + + // Clock port mapping + /* Palmer: FIXME: I don't handle memories with read/write clocks yet. */ + /* Colin not all libPorts have clocks but all memPorts do*/ + libPort.src.clock.foreach { cPort => + stmts += connectPorts(WRef(memPort.src.clock.get.name), cPort.name, cPort.polarity) + } + + // Adress port mapping + /* Palmer: The address port to a memory is just the low-order bits of + * the top address. */ + stmts += connectPorts(WRef(memPort.src.address.name), libPort.src.address.name, libPort.src.address.polarity) + + // Output port mapping + (memPort.src.output, libPort.src.output) match { + case (Some(PolarizedPort(mem, _)), Some(PolarizedPort(lib, lib_polarity))) => + /* Palmer: In order to produce the output of a memory we need to cat + * together a bunch of narrower memories, which can only be + * done after generating all the memories. This saves up the + * output statements for later. */ + val name = s"${mem}_${i}_$j" // This name is the output from the instance (mem vs ${mem}). + val exp = portToExpression(bits(WSubField(inst, lib), high - low, 0), Some(lib_polarity)) + stmts += DefNode(NoInfo, name, exp) + cats += WRef(name) + case (None, Some(_)) => + /* Palmer: If the inner memory has an output port but the outer + * one doesn't then it's safe to just leave the outer + * port floating. */ + case (None, None) => + /* Palmer: If there's no output ports at all (ie, read-only + * port on the memory) then just don't worry about it, + * there's nothing to do. */ + case (Some(PolarizedPort(mem, _)), None) => + System.err.println("WARNING: Unable to match output ports on memory") + System.err.println(s" outer output port: $mem") + return None + } + + // Input port mapping + (memPort.src.input, libPort.src.input) match { + case (Some(PolarizedPort(mem, _)), Some(PolarizedPort(lib, lib_polarity))) => + /* Palmer: The input port to a memory just needs to happen in parallel, + * this does a part select to narrow the memory down. */ + stmts += connectPorts(bits(WRef(mem), high, low), lib, lib_polarity) + case (None, Some(lib)) => + /* Palmer: If the inner memory has an input port but the other + * one doesn't then it's safe to just leave the inner + * port floating. This should be handled by the + * default value of the write enable, so nothing should + * every make it into the memory. */ + //Firrtl cares about dangling inputs now tie it off + stmts += IsInvalid(NoInfo, WSubField(inst, lib.name)) + case (None, None) => + /* Palmer: If there's no input ports at all (ie, read-only + * port on the memory) then just don't worry about it, + * there's nothing to do. */ + case (Some(PolarizedPort(mem, _)), None) => + System.err.println("WARNING: Unable to match input ports on memory") + System.err.println(s" outer input port: $mem") + return None + } + + // Mask port mapping + val memMask = memPort.src.maskPort match { + case Some(PolarizedPort(mem, _)) => + /* Palmer: The bits from the outer memory's write mask that will be + * used as the write mask for this inner memory. */ + if (libPort.src.effectiveMaskGran == libPort.src.width.get) { + bits(WRef(mem), low / memPort.src.effectiveMaskGran) + } else { + require(isPowerOfTwo(libPort.src.effectiveMaskGran), "only powers of two masks supported for now") + + // How much of this lib's width we are effectively using. + // If we have a mem maskGran less than the lib's maskGran, we'll have to take the smaller maskGran. + // Example: if we have a lib whose maskGran is 8 but our mem's maskGran is 4. + // The other case is if we're using a larger lib than mem. + val usingLessThanLibMaskGran = memPort.src.maskGran.get < libPort.src.effectiveMaskGran + val effectiveLibWidth = + if (usingLessThanLibMaskGran) + memPort.src.maskGran.get + else + libPort.src.width.get + + cat( + (0 until libPort.src.width.get by libPort.src.effectiveMaskGran) + .map(i => { + if (usingLessThanLibMaskGran && i >= effectiveLibWidth) { + // If the memMaskGran is smaller than the lib's gran, then + // zero out the upper bits. + zero + } else { + if ((low + i) >= memPort.src.width.get) { + // If our bit is larger than the whole width of the mem, just zero out the upper bits. + zero + } else { + // Pick the appropriate bit from the mem mask. + bits(WRef(mem), (low + i) / memPort.src.effectiveMaskGran) + } + } + }) + .reverse + ) + } + case None => + /* If there is a lib mask port but no mem mask port, just turn on + * all bits of the lib mask port. */ + if (libPort.src.maskPort.isDefined) { + val width = libPort.src.width.get / libPort.src.effectiveMaskGran + val value = (BigInt(1) << width) - 1 + UIntLiteral(value, IntWidth(width)) + } else { + // No mask ports on either side. + // We treat a "mask" of a single bit to be equivalent to a write + // enable (as used below). + one + } + } + + // Write enable port mapping + val memWriteEnable = memPort.src.writeEnable match { + case Some(PolarizedPort(mem, _)) => + /* Palmer: The outer memory's write enable port, or a constant 1 if + * there isn't a write enable port. */ + WRef(mem) + case None => + /* Palmer: If there is no input port on the source memory port + * then we don't ever want to turn on this write + * enable. Otherwise, we just _always_ turn on the + * write enable port on the inner memory. */ + if (memPort.src.input.isEmpty) zero else one + } + + // Chip enable port mapping + val memChipEnable = memPort.src.chipEnable match { + case Some(PolarizedPort(mem, _)) => WRef(mem) + case None => one + } + + // Read enable port mapping + /* Palmer: It's safe to ignore read enables, but we pass them through + * to the vendor memory if there's a port on there that + * implements the read enables. */ + (memPort.src.readEnable, libPort.src.readEnable) match { + case (_, None) => + case (Some(PolarizedPort(mem, _)), Some(PolarizedPort(lib, lib_polarity))) => + stmts += connectPorts(andAddrMatch(WRef(mem)), lib, lib_polarity) + case (None, Some(PolarizedPort(lib, lib_polarity))) => + stmts += connectPorts(andAddrMatch(and(not(memWriteEnable), memChipEnable)), lib, lib_polarity) + } + + /* Palmer: This is actually the memory compiler: it figures out how to + * implement the outer memory's collection of ports using what + * the inner memory has availiable. */ + ((libPort.src.maskPort, libPort.src.writeEnable, libPort.src.chipEnable): @unchecked) match { + case ( + Some(PolarizedPort(mask, mask_polarity)), + Some(PolarizedPort(we, we_polarity)), + Some(PolarizedPort(en, en_polarity)) + ) => + /* Palmer: This is the simple option: every port exists. */ + stmts += connectPorts(memMask, mask, mask_polarity) + stmts += connectPorts(andAddrMatch(memWriteEnable), we, we_polarity) + stmts += connectPorts(andAddrMatch(memChipEnable), en, en_polarity) + case (Some(PolarizedPort(mask, mask_polarity)), Some(PolarizedPort(we, we_polarity)), None) => + /* Palmer: If we don't have a chip enable but do have mask ports. */ + stmts += connectPorts(memMask, mask, mask_polarity) + stmts += connectPorts(andAddrMatch(and(memWriteEnable, memChipEnable)), we, we_polarity) + case (None, Some(PolarizedPort(we, we_polarity)), chipEnable) => + if (bitWidth(memMask.tpe) == 1) { + /* Palmer: If we're expected to provide mask ports without a + * memory that actually has them then we can use the + * write enable port instead of the mask port. */ + chipEnable match { + case Some(PolarizedPort(en, en_polarity)) => + stmts += connectPorts(andAddrMatch(and(memWriteEnable, memMask)), we, we_polarity) + stmts += connectPorts(andAddrMatch(memChipEnable), en, en_polarity) + case _ => + stmts += connectPorts( + andAddrMatch(and(and(memWriteEnable, memChipEnable), memMask)), + we, + we_polarity + ) + } + } else { + System.err.println("cannot emulate multi-bit mask ports with write enable") + return None + } + case (None, None, None) => + // No write ports to match up (this may be a read-only port). + // This isn't necessarily an error condition. + } + } + // Cat macro outputs for selection + memPort.src.output match { + case Some(PolarizedPort(mem, _)) if cats.nonEmpty => + val name = s"${mem}_$i" + stmts += DefNode(NoInfo, name, cat(cats.toSeq.reverse)) + outputs.getOrElseUpdate(mem, ArrayBuffer[(Expression, Expression)]()) += + (addrMatchReg -> WRef(name)) + case _ => + } + } + } + // Connect mem outputs + val zeroOutputValue: Expression = UIntLiteral(0, IntWidth(mem.src.width)) + mem.src.ports.foreach { port => + port.output match { + case Some(PolarizedPort(mem, _)) => + outputs.get(mem) match { + case Some(select) => + val output = select.foldRight(zeroOutputValue) { case ((cond, tval), fval) => + Mux(cond, tval, fval, fval.tpe) + } + stmts += Connect(NoInfo, WRef(mem), output) + case None => + } + case None => + } + } + + Some((mem.module(Block(stmts.toSeq)), lib)) + } + + def run(c: Circuit): Circuit = { + var firstLib = true + val modules = (mems, libs) match { + case (Some(mems), Some(libs)) => + // Try to compile each of the memories in mems. + // The 'state' is c.modules, which is a list of all the firrtl modules + // in the 'circuit'. + mems.foldLeft(c.modules) { (modules, mem) => + val sram = mem.src + def groupMatchesMask(group: SRAMGroup, mem: SRAMMacro): Boolean = { + val memMask = mem.ports.map(_.maskGran).find(_.isDefined).flatten + val libMask = group.ports.map(_.maskGran).find(_.isDefined).flatten + (memMask, libMask) match { + case (None, _) => true + case (Some(_), None) => false + case (Some(m), Some(l)) => l <= m //Ignore memories that don't have nice mask + } + } + // Add compiler memories that might map well to libs + val compLibs = compilers match { + case Some(SRAMCompiler(_, groups)) => + groups + .filter(g => g.family == sram.family && groupMatchesMask(g, sram)) + .map(g => { + for { + w <- g.width + d <- g.depth if (sram.width % w == 0) && (sram.depth % d == 0) + } yield Seq(new Macro(buildSRAMMacro(g, d, w, g.vt.head))) + }) + case None => Seq() + } + val fullLibs = libs ++ compLibs.flatten.flatten + + // Try to compile mem against each lib in libs, keeping track of the + // best compiled version, external lib used, and cost. + val (best, _) = fullLibs.foldLeft(None: Option[(Module, Macro)], Double.MaxValue) { + case ((best, cost), lib) if mem.src.ports.size != lib.src.ports.size => + /* Palmer: FIXME: This just assumes the Chisel and vendor ports are in the same + * order, but I'm starting with what actually gets generated. */ + System.err.println(s"INFO: unable to compile ${mem.src.name} using ${lib.src.name} port count must match") + (best, cost) + case ((best, cost), lib) => + // Run the cost function to evaluate this potential compile. + costMetric.cost(mem, lib) match { + case Some(newCost) => + //System.err.println(s"Cost of ${lib.src.name} for ${mem.src.name}: ${newCost}") + // Try compiling + compile(mem, lib) match { + // If it was successful and the new cost is lower + case Some(p) if newCost < cost => (Some(p), newCost) + case _ => (best, cost) + } + case _ => (best, cost) // Cost function rejected this combination. + } + } + + // If we were able to compile anything, then replace the original module + // in the modules list with a compiled version, as well as the extmodule + // stub for the lib. + best match { + case None => + if (mode == MacroCompilerAnnotation.Strict) + throw MacroCompilerException( + s"Target memory ${mem.src.name} could not be compiled and strict mode is activated - aborting." + ) + else + modules + case Some((mod, bb)) => + hammerIR match { + case Some(f) => + val hammerIRWriter = new FileWriter(new File(f), !firstLib) + if (firstLib) hammerIRWriter.write("[\n") + hammerIRWriter.write(bb.src.toJSON().toString()) + hammerIRWriter.write("\n,\n") + hammerIRWriter.close() + firstLib = false + case None => + } + modules.filterNot(m => m.name == mod.name || m.name == bb.blackbox.name) ++ Seq(mod, bb.blackbox) + } + } + case _ => c.modules + } + c.copy(modules = modules) + } +} + +class MacroCompilerTransform extends Transform with DependencyAPIMigration { + override def prerequisites: Seq[TransformDependency] = Forms.LowForm + override def optionalPrerequisites: Seq[TransformDependency] = Forms.LowFormOptimized + override def optionalPrerequisiteOf: Seq[Dependency[Emitter]] = Forms.LowEmitters + override def invalidates(a: Transform) = false + + def execute(state: CircuitState): CircuitState = state.annotations.collect { case a: MacroCompilerAnnotation => + a + } match { + case Seq(anno: MacroCompilerAnnotation) => + val MacroCompilerAnnotation.Params( + memFile, + memFileFormat, + libFile, + hammerIR, + costMetric, + mode, + useCompiler, + forceCompile, + forceSynflops + ) = anno.params + if (mode == MacroCompilerAnnotation.FallbackSynflops) { + throw new UnsupportedOperationException("Not implemented yet") + } + + // Check that we don't have any modules both forced to compile and synflops. + assert(forceCompile.intersect(forceSynflops).isEmpty, "Cannot have modules both forced to compile and synflops") + + // Read, eliminate None, get only SRAM, make firrtl macro + val mems: Option[Seq[Macro]] = (memFileFormat match { + case Some("conf") => readConfFromPath(Some(memFile)) + case _ => mdf.macrolib.Utils.readMDFFromPath(Some(memFile)) + }) match { + case Some(x: Seq[mdf.macrolib.Macro]) => + Some(filterForSRAM(Some(x)).getOrElse(List()).map { new Macro(_) }) + case _ => None + } + val libs: Option[Seq[Macro]] = mdf.macrolib.Utils.readMDFFromPath(libFile) match { + case Some(x: Seq[mdf.macrolib.Macro]) => + Some(filterForSRAM(Some(x)).getOrElse(List()).map { new Macro(_) }) + case _ => None + } + val compilers: Option[mdf.macrolib.SRAMCompiler] = mdf.macrolib.Utils.readMDFFromPath(libFile) match { + case Some(x: Seq[mdf.macrolib.Macro]) => + if (useCompiler) { + findSRAMCompiler(Some(x)) + } else None + case _ => None + } + + // Helper function to turn a set of mem names into a Seq[Macro]. + def setToSeqMacro(names: Set[String]): Seq[Macro] = { + names.toSeq.map(memName => mems.get.collectFirst { case m if m.src.name == memName => m }.get) + } + + // Build lists of memories for compilation and synflops. + val memCompile = mems.map { actualMems => + val memsAdjustedForMode = if (mode == MacroCompilerAnnotation.Synflops) Seq.empty else actualMems + memsAdjustedForMode.filterNot(m => forceSynflops.contains(m.src.name)) ++ setToSeqMacro(forceCompile) + } + val memSynflops: Seq[Macro] = mems.map { actualMems => + // + val memsAdjustedForMode = if (mode == MacroCompilerAnnotation.Synflops) actualMems else Seq.empty + memsAdjustedForMode.filterNot(m => forceCompile.contains(m.src.name)) ++ setToSeqMacro(forceSynflops) + }.getOrElse(Seq.empty) + + val transforms = Seq( + new MacroCompilerPass(memCompile, libs, compilers, hammerIR, costMetric, mode), + new SynFlopsPass( + true, + memSynflops ++ (if (mode == MacroCompilerAnnotation.CompileAndSynflops) { + libs.get + } else { + Seq.empty + }) + ) + ) + transforms.foldLeft(state)((s, xform) => xform.runTransform(s)) + case _ => state + } +} + +class MacroCompilerOptimizations extends SeqTransform with DependencyAPIMigration { + override def prerequisites: Seq[TransformDependency] = Forms.LowForm + override def optionalPrerequisites: Seq[TransformDependency] = Forms.LowFormOptimized + override def optionalPrerequisiteOf: Seq[Dependency[Emitter]] = Forms.LowEmitters + override def invalidates(a: Transform) = false + + def transforms: Seq[Transform] = Seq( + passes.RemoveValidIf, + new firrtl.transforms.ConstantPropagation, + passes.memlib.VerilogMemDelays, + new firrtl.transforms.ConstantPropagation, + passes.SplitExpressions, + passes.CommonSubexpressionElimination + ) +} + +object MacroCompiler extends App { + sealed trait MacroParam + case object Macros extends MacroParam + case object MacrosFormat extends MacroParam + case object Library extends MacroParam + case object Verilog extends MacroParam + case object Firrtl extends MacroParam + case object HammerIR extends MacroParam + case object CostFunc extends MacroParam + case object Mode extends MacroParam + case object UseCompiler extends MacroParam + + type MacroParamMap = Map[MacroParam, String] + type CostParamMap = Map[String, String] + type ForcedMemories = (Set[String], Set[String]) + val modeOptions: Seq[String] = MacroCompilerAnnotation.options.map { case (_, cmd, description) => + s" $cmd: $description" + } + val usage: String = (Seq( + "Options:", + " -n, --macro-conf: The set of macros to compile in firrtl-generated conf format (exclusive with -m)", + " -m, --macro-mdf: The set of macros to compile in MDF JSON format (exclusive with -n)", + " -l, --library: The set of macros that have blackbox instances", + " -u, --use-compiler: Flag, whether to use the memory compiler defined in library", + " -v, --verilog: Verilog output", + " -f, --firrtl: FIRRTL output (optional)", + " -hir, --hammer-ir: Hammer-IR output currently only needed for IP compilers", + " -c, --cost-func: Cost function to use. Optional (default: \"default\")", + " -cp, --cost-param: Cost function parameter. (Optional depending on the cost function.). e.g. -c ExternalMetric -cp path /path/to/my/cost/script", + " --force-compile [mem]: Force the given memory to be compiled to target libs regardless of the mode", + " --force-synflops [mem]: Force the given memory to be compiled via synflops regardless of the mode", + " --mode:" + ) ++ modeOptions).mkString("\n") + + @tailrec + def parseArgs( + map: MacroParamMap, + costMap: CostParamMap, + forcedMemories: ForcedMemories, + args: List[String] + ): (MacroParamMap, CostParamMap, ForcedMemories) = + args match { + case Nil => (map, costMap, forcedMemories) + case ("-n" | "--macro-conf") :: value :: tail => + parseArgs(map + (Macros -> value) + (MacrosFormat -> "conf"), costMap, forcedMemories, tail) + case ("-m" | "--macro-mdf") :: value :: tail => + parseArgs(map + (Macros -> value) + (MacrosFormat -> "mdf"), costMap, forcedMemories, tail) + case ("-l" | "--library") :: value :: tail => + parseArgs(map + (Library -> value), costMap, forcedMemories, tail) + case ("-u" | "--use-compiler") :: tail => + parseArgs(map + (UseCompiler -> ""), costMap, forcedMemories, tail) + case ("-v" | "--verilog") :: value :: tail => + parseArgs(map + (Verilog -> value), costMap, forcedMemories, tail) + case ("-f" | "--firrtl") :: value :: tail => + parseArgs(map + (Firrtl -> value), costMap, forcedMemories, tail) + case ("-hir" | "--hammer-ir") :: value :: tail => + parseArgs(map + (HammerIR -> value), costMap, forcedMemories, tail) + case ("-c" | "--cost-func") :: value :: tail => + parseArgs(map + (CostFunc -> value), costMap, forcedMemories, tail) + case ("-cp" | "--cost-param") :: value1 :: value2 :: tail => + parseArgs(map, costMap + (value1 -> value2), forcedMemories, tail) + case "--force-compile" :: value :: tail => + parseArgs(map, costMap, forcedMemories.copy(_1 = forcedMemories._1 + value), tail) + case "--force-synflops" :: value :: tail => + parseArgs(map, costMap, forcedMemories.copy(_2 = forcedMemories._2 + value), tail) + case "--mode" :: value :: tail => + parseArgs(map + (Mode -> value), costMap, forcedMemories, tail) + case arg :: _ => + println(s"Unknown field $arg\n") + println(usage) + sys.exit(1) + } + + def run(args: List[String]): Unit = { + val (params, costParams, forcedMemories) = + parseArgs(Map[MacroParam, String](), Map[String, String](), (Set.empty, Set.empty), args) + try { + val macros = params.get(MacrosFormat) match { + case Some("conf") => + filterForSRAM(readConfFromPath(params.get(Macros))).get.map(x => new Macro(x).blackbox) + case _ => + filterForSRAM(mdf.macrolib.Utils.readMDFFromPath(params.get(Macros))).get + .map(x => new Macro(x).blackbox) + } + + if (macros.nonEmpty) { + // Note: the last macro in the input list is (seemingly arbitrarily) + // determined as the firrtl "top-level module". + val circuit = Circuit(NoInfo, macros, macros.last.name) + val annotations = AnnotationSeq( + Seq( + MacroCompilerAnnotation( + circuit.main, + MacroCompilerAnnotation.Params( + params(Macros), + params.get(MacrosFormat), + params.get(Library), + params.get(HammerIR), + CostMetric.getCostMetric(params.getOrElse(CostFunc, "default"), costParams), + MacroCompilerAnnotation.stringToCompilerMode(params.getOrElse(Mode, "default")), + params.contains(UseCompiler), + forceCompile = forcedMemories._1, + forceSynflops = forcedMemories._2 + ) + ) + ) + ) + + // The actual MacroCompilerTransform basically just generates an input circuit + val macroCompilerInput = CircuitState(circuit, annotations) + val macroCompiled = (new MacroCompilerTransform).execute(macroCompilerInput) + + // Run FIRRTL compiler + // For each generated module, have to create a new circuit with that module + // as top, and all other modules as ExtModules. This guarantees all modules + // are elaborated + val verilog = macroCompiled.circuit.modules + .map(_.name) + .map { macroName => + val (mainMod, otherMods) = macroCompiled.circuit.modules.partition(_.name == macroName) + val extMods = otherMods.map(m => ExtModule(NoInfo, m.name, m.ports, m.name, Nil)) + + val circuit = Circuit(NoInfo, mainMod ++ extMods, macroName) + (new FirrtlStage) + .execute( + Array.empty, + Seq( + OutputFileAnnotation(params.get(Verilog).get), + RunFirrtlTransformAnnotation(new VerilogEmitter), + EmitCircuitAnnotation(classOf[VerilogEmitter]), + FirrtlSourceAnnotation(circuit.serialize) + ) + ) + .collect { case c: EmittedVerilogCircuitAnnotation => c } + .head + .value + .value + } + .mkString("\n") + + val verilogWriter = new FileWriter(new File(params.get(Verilog).get)) + verilogWriter.write(verilog) + verilogWriter.close() + + params.get(HammerIR) match { + case Some(hammerIRFile: String) => + val lines = FileUtils.getLines(hammerIRFile).toList + val hammerIRWriter = new FileWriter(new File(hammerIRFile)) + // JSON means we need to destroy the last comma :( + lines.dropRight(1).foreach(l => hammerIRWriter.write(l + "\n")) + hammerIRWriter.write("]\n") + hammerIRWriter.close() + case None => + } + } else { + // Warn user + System.err.println("WARNING: Empty *.mems.conf file. No memories generated.") + + // Emit empty verilog file if no macros found + params.get(Verilog) match { + case Some(verilogFile: String) => + // Create an empty verilog file + val verilogWriter = new FileWriter(new File(verilogFile)) + verilogWriter.close() + case None => + } + params.get(HammerIR) match { + case Some(hammerIRFile: String) => + // Create an empty HammerIR file + val hammerIRWriter = new FileWriter(new File(hammerIRFile)) + hammerIRWriter.write("[]\n") + hammerIRWriter.close() + case None => + } + } + } catch { + case e: java.util.NoSuchElementException => + if (args.isEmpty) { + println("Command line arguments must be specified") + } else { + e.printStackTrace() + } + e.printStackTrace() + sys.exit(1) + case e: MacroCompilerException => + println(usage) + e.printStackTrace() + sys.exit(1) + case e: Throwable => + throw e + } + } + + run(args.toList) +} diff --git a/tools/tapeout/src/main/scala/macros/SynFlopsPass.scala b/tools/tapeout/src/main/scala/macros/SynFlopsPass.scala new file mode 100644 index 00000000..0c1dd804 --- /dev/null +++ b/tools/tapeout/src/main/scala/macros/SynFlopsPass.scala @@ -0,0 +1,152 @@ +// See LICENSE for license details. + +package tapeout.macros + +import tapeout.macros.Utils._ +import firrtl.Utils.{one, zero} +import firrtl._ +import firrtl.ir._ +import firrtl.passes.MemPortUtils.memPortField + +import scala.collection.mutable + +class SynFlopsPass(synflops: Boolean, libs: Seq[Macro]) extends firrtl.passes.Pass { + val extraMods: mutable.ArrayBuffer[Module] = scala.collection.mutable.ArrayBuffer.empty[Module] + lazy val libMods: Map[String, Module] = libs.map { lib => + lib.src.name -> { + val (dataType, dataWidth) = lib.src.ports.foldLeft(None: Option[BigInt])((res, port) => + (res, port.maskPort) match { + case (_, None) => + res + case (None, Some(_)) => + Some(port.effectiveMaskGran) + case (Some(x), Some(_)) => + assert(x == port.effectiveMaskGran) + res + } + ) match { + case None => (UIntType(IntWidth(lib.src.width)), lib.src.width) + case Some(gran) => (UIntType(IntWidth(gran)), gran.intValue) + } + + val maxDepth = firrtl.Utils.min(lib.src.depth, 1 << 26) + + // Change macro to be mapped onto to look like the below mem + // by changing its depth, and width + val lib_macro = new Macro( + lib.src.copy( + name = "split_" + lib.src.name, + depth = maxDepth, + width = dataWidth, + ports = lib.src.ports.map(p => + p.copy( + width = p.width.map(_ => dataWidth), + depth = p.depth.map(_ => maxDepth), + maskGran = p.maskGran.map(_ => dataWidth) + ) + ) + ) + ) + val mod_macro = new MacroCompilerPass(None, None, None, None).compile(lib, lib_macro) + val (real_mod, real_macro) = mod_macro.get + + val mem = DefMemory( + NoInfo, + "ram", + dataType, + maxDepth, + 1, // writeLatency + 1, // readLatency. This is possible because of VerilogMemDelays + real_macro.readers.indices.map(i => s"R_$i"), + real_macro.writers.indices.map(i => s"W_$i"), + real_macro.readwriters.indices.map(i => s"RW_$i") + ) + + val readConnects = real_macro.readers.zipWithIndex.flatMap { case (r, i) => + val clock = portToExpression(r.src.clock.get) + val address = portToExpression(r.src.address) + val enable = (r.src.chipEnable, r.src.readEnable) match { + case (Some(en_port), Some(re_port)) => + and(portToExpression(en_port), portToExpression(re_port)) + case (Some(en_port), None) => portToExpression(en_port) + case (None, Some(re_port)) => portToExpression(re_port) + case (None, None) => one + } + val data = memPortField(mem, s"R_$i", "data") + val read = data + Seq( + Connect(NoInfo, memPortField(mem, s"R_$i", "clk"), clock), + Connect(NoInfo, memPortField(mem, s"R_$i", "addr"), address), + Connect(NoInfo, memPortField(mem, s"R_$i", "en"), enable), + Connect(NoInfo, WRef(r.src.output.get.name), read) + ) + } + + val writeConnects = real_macro.writers.zipWithIndex.flatMap { case (w, i) => + val clock = portToExpression(w.src.clock.get) + val address = portToExpression(w.src.address) + val enable = (w.src.chipEnable, w.src.writeEnable) match { + case (Some(en), Some(we)) => + and(portToExpression(en), portToExpression(we)) + case (Some(en), None) => portToExpression(en) + case (None, Some(we)) => portToExpression(we) + case (None, None) => zero // is it possible? + } + val mask = w.src.maskPort match { + case Some(m) => portToExpression(m) + case None => one + } + val data = memPortField(mem, s"W_$i", "data") + val write = portToExpression(w.src.input.get) + Seq( + Connect(NoInfo, memPortField(mem, s"W_$i", "clk"), clock), + Connect(NoInfo, memPortField(mem, s"W_$i", "addr"), address), + Connect(NoInfo, memPortField(mem, s"W_$i", "en"), enable), + Connect(NoInfo, memPortField(mem, s"W_$i", "mask"), mask), + Connect(NoInfo, data, write) + ) + } + + val readwriteConnects = real_macro.readwriters.zipWithIndex.flatMap { case (rw, i) => + val clock = portToExpression(rw.src.clock.get) + val address = portToExpression(rw.src.address) + val wmode = rw.src.writeEnable match { + case Some(we) => portToExpression(we) + case None => zero // is it possible? + } + val wmask = rw.src.maskPort match { + case Some(wm) => portToExpression(wm) + case None => one + } + val enable = (rw.src.chipEnable, rw.src.readEnable) match { + case (Some(en), Some(re)) => + and(portToExpression(en), or(portToExpression(re), wmode)) + case (Some(en), None) => portToExpression(en) + case (None, Some(re)) => or(portToExpression(re), wmode) + case (None, None) => one + } + val wdata = memPortField(mem, s"RW_$i", "wdata") + val rdata = memPortField(mem, s"RW_$i", "rdata") + val write = portToExpression(rw.src.input.get) + val read = rdata + Seq( + Connect(NoInfo, memPortField(mem, s"RW_$i", "clk"), clock), + Connect(NoInfo, memPortField(mem, s"RW_$i", "addr"), address), + Connect(NoInfo, memPortField(mem, s"RW_$i", "en"), enable), + Connect(NoInfo, memPortField(mem, s"RW_$i", "wmode"), wmode), + Connect(NoInfo, memPortField(mem, s"RW_$i", "wmask"), wmask), + Connect(NoInfo, WRef(rw.src.output.get.name), read), + Connect(NoInfo, wdata, write) + ) + } + + extraMods.append(real_macro.module(Block(mem +: (readConnects ++ writeConnects ++ readwriteConnects)))) + real_mod + } + }.toMap + + def run(c: Circuit): Circuit = { + if (!synflops) c + else c.copy(modules = c.modules.map(m => libMods.getOrElse(m.name, m)) ++ extraMods) + } +} diff --git a/tools/tapeout/src/main/scala/macros/Utils.scala b/tools/tapeout/src/main/scala/macros/Utils.scala new file mode 100644 index 00000000..8715ec10 --- /dev/null +++ b/tools/tapeout/src/main/scala/macros/Utils.scala @@ -0,0 +1,262 @@ +// See LICENSE for license details. + +package tapeout.macros + +import firrtl.Utils.BoolType +import firrtl.ir._ +import firrtl.passes.memlib._ +import firrtl.{PrimOps, _} +import mdf.macrolib.{Input => _, Output => _, _} + +import scala.language.implicitConversions + +object MacroCompilerMath { + def ceilLog2(x: BigInt): Int = (x - 1).bitLength +} + +class FirrtlMacroPort(port: MacroPort) { + val src: MacroPort = port + + val isReader: Boolean = port.output.nonEmpty && port.input.isEmpty + val isWriter: Boolean = port.input.nonEmpty && port.output.isEmpty + val isReadWriter: Boolean = port.input.nonEmpty && port.output.nonEmpty + + val addrType: UIntType = UIntType(IntWidth(MacroCompilerMath.ceilLog2(port.depth.get).max(1))) + val dataType: UIntType = UIntType(IntWidth(port.width.get)) + val maskType: UIntType = UIntType(IntWidth(port.width.get / port.effectiveMaskGran)) + + // Bundle representing this macro port. + val tpe: BundleType = BundleType( + Seq(Field(port.address.name, Flip, addrType)) ++ + port.clock.map(p => Field(p.name, Flip, ClockType)) ++ + port.input.map(p => Field(p.name, Flip, dataType)) ++ + port.output.map(p => Field(p.name, Default, dataType)) ++ + port.chipEnable.map(p => Field(p.name, Flip, BoolType)) ++ + port.readEnable.map(p => Field(p.name, Flip, BoolType)) ++ + port.writeEnable.map(p => Field(p.name, Flip, BoolType)) ++ + port.maskPort.map(p => Field(p.name, Flip, maskType)) + ) + val ports: Seq[Port] = tpe.fields.map(f => + Port( + NoInfo, + f.name, + f.flip match { + case Default => Output + case Flip => Input + }, + f.tpe + ) + ) +} + +// Reads an SRAMMacro and generates firrtl blackboxes. +class Macro(srcMacro: SRAMMacro) { + val src: SRAMMacro = srcMacro + + val firrtlPorts: Seq[FirrtlMacroPort] = srcMacro.ports.map { new FirrtlMacroPort(_) } + + val writers: Seq[FirrtlMacroPort] = firrtlPorts.filter(p => p.isWriter) + val readers: Seq[FirrtlMacroPort] = firrtlPorts.filter(p => p.isReader) + val readwriters: Seq[FirrtlMacroPort] = firrtlPorts.filter(p => p.isReadWriter) + + val sortedPorts: Seq[FirrtlMacroPort] = writers ++ readers ++ readwriters + val extraPorts: Seq[(String, UIntLiteral)] = srcMacro.extraPorts.map { p => + assert(p.portType == Constant) // TODO: release it? + val name = p.name + val width = BigInt(p.width.toLong) + val value = BigInt(p.value.toLong) + name -> UIntLiteral(value, IntWidth(width)) + } + + // Bundle representing this memory blackbox + val tpe: BundleType = BundleType(firrtlPorts.flatMap(_.tpe.fields)) + + private val modPorts = firrtlPorts.flatMap(_.ports) ++ + extraPorts.map { case (name, value) => Port(NoInfo, name, Input, value.tpe) } + val blackbox: ExtModule = ExtModule(NoInfo, srcMacro.name, modPorts, srcMacro.name, Nil) + def module(body: Statement): Module = Module(NoInfo, srcMacro.name, modPorts, body) +} + +object Utils { + def filterForSRAM(s: Option[Seq[mdf.macrolib.Macro]]): Option[Seq[mdf.macrolib.SRAMMacro]] = { + s match { + case Some(l: Seq[mdf.macrolib.Macro]) => + Some(l.filter { _.isInstanceOf[mdf.macrolib.SRAMMacro] }.map { m => m.asInstanceOf[mdf.macrolib.SRAMMacro] }) + case _ => None + } + } + // This utility reads a conf in and returns MDF like mdf.macrolib.Utils.readMDFFromPath + def readConfFromPath(path: Option[String]): Option[Seq[mdf.macrolib.Macro]] = { + path.map(p => Utils.readConfFromString(FileUtils.getText(p))) + } + def readConfFromString(str: String): Seq[mdf.macrolib.Macro] = { + MemConf.fromString(str).map { m: MemConf => + val ports = m.ports.map { case (port, num) => Seq.fill(num)(port) }.reduce(_ ++ _) + SRAMMacro( + m.name, + m.width, + m.depth, + Utils.portSpecToFamily(ports), + Utils.portSpecToMacroPort(m.width, m.depth, m.maskGranularity, ports) + ) + } + } + def portSpecToFamily(ports: Seq[MemPort]): String = { + val numR = ports.count { case ReadPort => true; case _ => false } + val numW = ports.count { case WritePort | MaskedWritePort => true; case _ => false } + val numRW = ports.count { case ReadWritePort | MaskedReadWritePort => true; case _ => false } + val numRStr = if (numR > 0) s"${numR}r" else "" + val numWStr = if (numW > 0) s"${numW}w" else "" + val numRWStr = if (numRW > 0) s"${numRW}rw" else "" + numRStr + numWStr + numRWStr + } + // This translates between two represenations of ports + def portSpecToMacroPort(width: Int, depth: BigInt, maskGran: Option[Int], ports: Seq[MemPort]): Seq[MacroPort] = { + var numR = 0 + var numW = 0 + var numRW = 0 + ports.map { + case ReadPort => + val portName = s"R$numR" + numR += 1 + MacroPort( + width = Some(width), + depth = Some(depth), + address = PolarizedPort(s"${portName}_addr", ActiveHigh), + clock = Some(PolarizedPort(s"${portName}_clk", PositiveEdge)), + readEnable = Some(PolarizedPort(s"${portName}_en", ActiveHigh)), + output = Some(PolarizedPort(s"${portName}_data", ActiveHigh)) + ) + case WritePort => + val portName = s"W$numW" + numW += 1 + MacroPort( + width = Some(width), + depth = Some(depth), + address = PolarizedPort(s"${portName}_addr", ActiveHigh), + clock = Some(PolarizedPort(s"${portName}_clk", PositiveEdge)), + writeEnable = Some(PolarizedPort(s"${portName}_en", ActiveHigh)), + input = Some(PolarizedPort(s"${portName}_data", ActiveHigh)) + ) + case MaskedWritePort => + val portName = s"W$numW" + numW += 1 + MacroPort( + width = Some(width), + depth = Some(depth), + address = PolarizedPort(s"${portName}_addr", ActiveHigh), + clock = Some(PolarizedPort(s"${portName}_clk", PositiveEdge)), + writeEnable = Some(PolarizedPort(s"${portName}_en", ActiveHigh)), + maskPort = Some(PolarizedPort(s"${portName}_mask", ActiveHigh)), + maskGran = maskGran, + input = Some(PolarizedPort(s"${portName}_data", ActiveHigh)) + ) + case ReadWritePort => + val portName = s"RW$numRW" + numRW += 1 + MacroPort( + width = Some(width), + depth = Some(depth), + address = PolarizedPort(s"${portName}_addr", ActiveHigh), + clock = Some(PolarizedPort(s"${portName}_clk", PositiveEdge)), + chipEnable = Some(PolarizedPort(s"${portName}_en", ActiveHigh)), + writeEnable = Some(PolarizedPort(s"${portName}_wmode", ActiveHigh)), + input = Some(PolarizedPort(s"${portName}_wdata", ActiveHigh)), + output = Some(PolarizedPort(s"${portName}_rdata", ActiveHigh)) + ) + case MaskedReadWritePort => + val portName = s"RW$numRW" + numRW += 1 + MacroPort( + width = Some(width), + depth = Some(depth), + address = PolarizedPort(s"${portName}_addr", ActiveHigh), + clock = Some(PolarizedPort(s"${portName}_clk", PositiveEdge)), + chipEnable = Some(PolarizedPort(s"${portName}_en", ActiveHigh)), + writeEnable = Some(PolarizedPort(s"${portName}_wmode", ActiveHigh)), + maskPort = Some(PolarizedPort(s"${portName}_wmask", ActiveHigh)), + maskGran = maskGran, + input = Some(PolarizedPort(s"${portName}_wdata", ActiveHigh)), + output = Some(PolarizedPort(s"${portName}_rdata", ActiveHigh)) + ) + } + } + def findSRAMCompiler(s: Option[Seq[mdf.macrolib.Macro]]): Option[mdf.macrolib.SRAMCompiler] = { + s match { + case Some(l: Seq[mdf.macrolib.Macro]) => + l.collectFirst { case x: mdf.macrolib.SRAMCompiler => + x + } + case _ => None + } + } + def buildSRAMMacros(s: mdf.macrolib.SRAMCompiler): Seq[mdf.macrolib.SRAMMacro] = { + for { + g <- s.groups + d <- g.depth + w <- g.width + vt <- g.vt + } yield mdf.macrolib.SRAMMacro( + makeName(g, d, w, vt), + w, + d, + g.family, + g.ports.map(_.copy(width = Some(w), depth = Some(d))), + vt, + g.mux, + g.extraPorts + ) + } + def buildSRAMMacro(g: mdf.macrolib.SRAMGroup, d: Int, w: Int, vt: String): mdf.macrolib.SRAMMacro = { + mdf.macrolib.SRAMMacro( + makeName(g, d, w, vt), + w, + d, + g.family, + g.ports.map(_.copy(width = Some(w), depth = Some(d))), + vt, + g.mux, + g.extraPorts + ) + } + def makeName(g: mdf.macrolib.SRAMGroup, depth: Int, width: Int, vt: String): String = { + g.name.foldLeft("") { (builder, next) => + next match { + case "depth" | "DEPTH" => builder + depth + case "width" | "WIDTH" => builder + width + case "vt" => builder + vt.toLowerCase + case "VT" => builder + vt.toUpperCase + case "family" => builder + g.family.toLowerCase + case "FAMILY" => builder + g.family.toUpperCase + case "mux" | "MUX" => builder + g.mux + case other => builder + other + } + } + } + + def and(e1: Expression, e2: Expression): DoPrim = + DoPrim(PrimOps.And, Seq(e1, e2), Nil, e1.tpe) + def or(e1: Expression, e2: Expression): DoPrim = + DoPrim(PrimOps.Or, Seq(e1, e2), Nil, e1.tpe) + def bits(e: Expression, high: BigInt, low: BigInt): Expression = + DoPrim(PrimOps.Bits, Seq(e), Seq(high, low), UIntType(IntWidth(high - low + 1))) + def bits(e: Expression, idx: BigInt): Expression = bits(e, idx, idx) + def cat(es: Seq[Expression]): Expression = + if (es.size == 1) es.head + else DoPrim(PrimOps.Cat, Seq(es.head, cat(es.tail)), Nil, UnknownType) + def not(e: Expression): DoPrim = + DoPrim(PrimOps.Not, Seq(e), Nil, e.tpe) + + // Convert a port to a FIRRTL expression, handling polarity along the way. + def portToExpression(pp: PolarizedPort): Expression = + portToExpression(WRef(pp.name), Some(pp.polarity)) + + def portToExpression(exp: Expression, polarity: Option[PortPolarity]): Expression = + polarity match { + case Some(ActiveLow) | Some(NegativeEdge) => not(exp) + case _ => exp + } + + // Check if a number is a power of two + def isPowerOfTwo(x: Int): Boolean = (x & (x - 1)) == 0 +} diff --git a/variables.mk b/variables.mk index 55dacd04..9878590a 100644 --- a/variables.mk +++ b/variables.mk @@ -9,7 +9,6 @@ HELP_COMPILATION_VARIABLES = \ " SBT_OPTS = set additional sbt command line options (these take the form -Dsbt.