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Fix SerialTL HarnessRAM BridgeBinder

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This commit is contained in:
Jerry Zhao
2021-03-15 15:09:29 -07:00
parent edd54e776c
commit a013f0d561
1 changed files with 3 additions and 1 deletions
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4
generators/firechip/src/main/scala/BridgeBinders.scala
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@@ -71,7 +71,9 @@ class WithSerialBridge extends OverrideHarnessBinder({
ports.map { port => ports.map { port =>
implicit val p = GetSystemParameters(system) implicit val p = GetSystemParameters(system)
val bits = SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset) val bits = SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset)
val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset) val ram = withClockAndReset(th.harnessClock, th.harnessReset) {
SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset)
}
SerialBridge(th.harnessClock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName)) SerialBridge(th.harnessClock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName))
} }
Nil Nil