From a013f0d561fb06a1118e3cbf766d734da427a847 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 15 Mar 2021 15:09:29 -0700 Subject: [PATCH] Fix SerialTL HarnessRAM BridgeBinder --- generators/firechip/src/main/scala/BridgeBinders.scala | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index f0b376d0..95f0bf3b 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -71,7 +71,9 @@ class WithSerialBridge extends OverrideHarnessBinder({ ports.map { port => implicit val p = GetSystemParameters(system) val bits = SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset) - val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset) + val ram = withClockAndReset(th.harnessClock, th.harnessReset) { + SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset) + } SerialBridge(th.harnessClock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName)) } Nil