Fix SerialTL HarnessRAM BridgeBinder

2021-03-15 15:09:29 -07:00
parent edd54e776c
commit a013f0d561
1 changed files with 3 additions and 1 deletions
--- a/generators/firechip/src/main/scala/BridgeBinders.scala
+++ b/generators/firechip/src/main/scala/BridgeBinders.scala
@@ -71,7 +71,9 @@ class WithSerialBridge extends OverrideHarnessBinder({
    ports.map { port =>
      implicit val p = GetSystemParameters(system)
      val bits = SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset)
-      val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset)
+      val ram = withClockAndReset(th.harnessClock, th.harnessReset) {
+        SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset)
+      }
      SerialBridge(th.harnessClock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName))
    }
    Nil