fully switch to chisel3
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Submodule rocket-chip updated: f5a8ba280d...f3299ae91d
@@ -4,13 +4,13 @@ import util.GeneratorApp
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import diplomacy.LazyModule
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import rocketchip._
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import testchipip._
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import Chisel._
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import chisel3._
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import cde.Parameters
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class TestHarness(implicit val p: Parameters) extends Module {
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val io = new Bundle {
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val success = Bool(OUTPUT)
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}
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val io = IO(new Bundle {
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val success = Output(Bool())
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})
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def buildTop(p: Parameters): ExampleTop = LazyModule(new ExampleTop(p))
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@@ -9,12 +9,12 @@ import diplomacy._
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import rocketchip._
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class PWMBase extends Module {
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val io = new Bundle {
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val pwmout = Bool(OUTPUT)
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val period = UInt(INPUT, 64)
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val duty = UInt(INPUT, 64)
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val enable = Bool(INPUT)
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}
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val io = IO(new Bundle {
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val pwmout = Output(Bool())
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val period = Input(UInt(64.W))
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val duty = Input(UInt(64.W))
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val enable = Input(Bool())
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})
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// The counter should count up until period is reached
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val counter = Reg(UInt(width = 64))
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@@ -31,10 +31,10 @@ class PWMBase extends Module {
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}
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class PWMTL(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val pwmout = Bool(OUTPUT)
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val tl = new ClientUncachedTileLinkIO().flip
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}
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val io = IO(new Bundle {
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val pwmout = Output(Bool())
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val tl = Flipped(new ClientUncachedTileLinkIO())
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})
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// How many clock cycles in a PWM cycle?
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val period = Reg(UInt(width = 64))
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@@ -95,10 +95,10 @@ class PWMTL(implicit p: Parameters) extends Module {
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}
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class PWMAXI(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val pwmout = Bool(OUTPUT)
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val axi = new NastiIO().flip
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}
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val io = IO(new Bundle {
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val pwmout = Output(Bool())
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val axi = Flipped(new NastiIO())
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})
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// How many clock cycles in a PWM cycle?
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val period = Reg(UInt(width = 64))
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@@ -158,7 +158,7 @@ trait PeripheryPWM extends LazyModule {
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}
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trait PeripheryPWMBundle {
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val pwmout = Bool(OUTPUT)
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val pwmout = Output(Bool())
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}
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case object BuildPWM extends Field[(ClientUncachedTileLinkIO, Parameters) => Bool]
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Submodule testchipip updated: 63bf093975...69b66e4b1d
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