restructure macros for better submoduling

2017-07-25 13:48:58 -07:00
parent 607e810b1d
commit 9de1f5f2c0
28 changed files with 27 additions and 26 deletions
--- a/macros/src/main/scala/MacroCompiler.scala
+++ b/macros/src/main/scala/MacroCompiler.scala
@@ -0,0 +1,429 @@
+// See LICENSE for license details.
+
+package barstools.macros
+
+import firrtl._
+import firrtl.ir._
+import firrtl.PrimOps
+import firrtl.Utils._
+import firrtl.annotations._
+import firrtl.CompilerUtils.getLoweringTransforms
+import mdf.macrolib.{PolarizedPort, PortPolarity}
+import scala.collection.mutable.{ArrayBuffer, HashMap}
+import java.io.{File, FileWriter}
+import Utils._
+
+object MacroCompilerAnnotation {
+  def apply(c: String, mem: String, lib: Option[String], synflops: Boolean) = {
+    Annotation(CircuitName(c), classOf[MacroCompilerTransform],
+      s"${mem} %s ${synflops}".format(lib map (_.toString) getOrElse ""))
+  }
+  private val matcher = "([^ ]+) ([^ ]*) (true|false)".r
+  def unapply(a: Annotation) = a match {
+    case Annotation(CircuitName(c), t, matcher(mem, lib, synflops)) if t == classOf[MacroCompilerTransform] =>
+      Some((c, Some(mem), if (lib.isEmpty) None else Some(lib), synflops.toBoolean))
+    case _ => None
+  }
+}
+
+class MacroCompilerPass(mems: Option[Seq[Macro]],
+                        libs: Option[Seq[Macro]]) extends firrtl.passes.Pass {
+  def compile(mem: Macro, lib: Macro): Option[(Module, ExtModule)] = {
+    val pairedPorts = mem.sortedPorts zip lib.sortedPorts
+
+    // Parallel mapping
+    val pairs = ArrayBuffer[(BigInt, BigInt)]()
+    var last = 0
+    for (i <- 0 until mem.src.width) {
+      if (i <= last + 1) {
+        /* Palmer: Every memory is going to have to fit at least a single bit. */
+        // continue
+      } else if ((i - last) % lib.src.width.toInt == 0) {
+        /* Palmer: It's possible that we rolled over a memory's width here,
+                   if so generate one. */
+        pairs += ((last, i-1))
+        last = i
+      } else {
+        /* Palmer: FIXME: This is a mess, I must just be super confused. */
+        for ((memPort, libPort) <- pairedPorts) {
+          (memPort.src.maskGran, libPort.src.maskGran) match {
+            case (_, Some(p)) if p == 1 => // continue
+            case (Some(p), _) if i % p == 0 =>
+              pairs += ((last, i-1))
+              last = i
+            case (_, None) => // continue
+            case (_, Some(p)) if p == lib.src.width => // continue
+            case _ =>
+              System.err println "Bit-mask (or unmasked) target memories are supported only"
+              return None
+          }
+        }
+      }
+    }
+    pairs += ((last, mem.src.width.toInt - 1))
+
+    // Serial mapping
+    val stmts = ArrayBuffer[Statement]()
+    val selects = HashMap[String, Expression]()
+    val outputs = HashMap[String, ArrayBuffer[(Expression, Expression)]]()
+    /* Palmer: If we've got a parallel memory then we've got to take the
+      * address bits into account. */
+    if (mem.src.depth > lib.src.depth) {
+      mem.src.ports foreach { port =>
+        val high = ceilLog2(mem.src.depth)
+        val low = ceilLog2(lib.src.depth)
+        val ref = WRef(port.address.name)
+        val name = s"${ref.name}_sel"
+        selects(ref.name) =  WRef(name, UIntType(IntWidth(high-low)))
+        stmts += DefNode(NoInfo, name, bits(ref, high-1, low))
+      }
+    }
+    for ((off, i) <- (0 until mem.src.depth by lib.src.depth).zipWithIndex) {
+      for (j <- pairs.indices) {
+        val name = s"mem_${i}_${j}"
+        stmts += WDefInstance(NoInfo, name, lib.src.name, lib.tpe)
+        // connect extra ports
+        stmts ++= lib.extraPorts map { case (portName, portValue) =>
+          Connect(NoInfo, WSubField(WRef(name), portName), portValue)
+        }
+      }
+      for ((memPort, libPort) <- pairedPorts) {
+        val addrMatch = selects get memPort.src.address.name match {
+          case None => one
+          case Some(addr) =>
+            val index = UIntLiteral(i, IntWidth(bitWidth(addr.tpe)))
+            DoPrim(PrimOps.Eq, Seq(addr, index), Nil, index.tpe)
+        }
+        def andAddrMatch(e: Expression) = and(e, addrMatch)
+        val cats = ArrayBuffer[Expression]()
+        for (((low, high), j) <- pairs.zipWithIndex) {
+          val inst = WRef(s"mem_${i}_${j}", lib.tpe)
+
+          def connectPorts2(mem: Expression,
+                           lib: String,
+                           polarity: Option[PortPolarity]): Statement =
+            Connect(NoInfo, WSubField(inst, lib), portToExpression(mem, polarity))
+          def connectPorts(mem: Expression,
+                           lib: String,
+                           polarity: PortPolarity): Statement =
+            connectPorts2(mem, lib, Some(polarity))
+
+          // Clock port mapping
+          /* Palmer: FIXME: I don't handle memories with read/write clocks yet. */
+          stmts += connectPorts(WRef(memPort.src.clock.name),
+                                libPort.src.clock.name,
+                                libPort.src.clock.polarity)
+
+          // Adress port mapping
+          /* Palmer: The address port to a memory is just the low-order bits of
+           * the top address. */
+          stmts += connectPorts(WRef(memPort.src.address.name),
+                                libPort.src.address.name,
+                                libPort.src.address.polarity)
+
+          // Output port mapping
+          (memPort.src.output, libPort.src.output) match {
+            case (Some(PolarizedPort(mem, _)), Some(PolarizedPort(lib, lib_polarity))) =>
+              /* Palmer: In order to produce the output of a memory we need to cat
+               * together a bunch of narrower memories, which can only be
+               * done after generating all the memories.  This saves up the
+               * output statements for later. */
+              val name = s"${mem}_${i}_${j}"
+              val exp = portToExpression(bits(WSubField(inst, lib), high-low, 0), Some(lib_polarity))
+              stmts += DefNode(NoInfo, name, exp)
+              cats += WRef(name)
+            case (None, Some(lib)) =>
+              /* Palmer: If the inner memory has an output port but the outer
+               * one doesn't then it's safe to just leave the outer
+               * port floating. */
+            case (None, None) =>
+              /* Palmer: If there's no output ports at all (ie, read-only
+               * port on the memory) then just don't worry about it,
+               * there's nothing to do. */
+            case (Some(PolarizedPort(mem, _)), None) =>
+              System.err println "WARNING: Unable to match output ports on memory"
+              System.err println s"  outer output port: ${mem}"
+              return None
+          }
+
+          // Input port mapping
+          (memPort.src.input, libPort.src.input) match {
+            case (Some(PolarizedPort(mem, _)), Some(PolarizedPort(lib, lib_polarity))) =>
+              /* Palmer: The input port to a memory just needs to happen in parallel,
+               * this does a part select to narrow the memory down. */
+              stmts += connectPorts(bits(WRef(mem), high, low), lib, lib_polarity)
+            case (None, Some(lib)) =>
+              /* Palmer: If the inner memory has an input port but the other
+               * one doesn't then it's safe to just leave the inner
+               * port floating.  This should be handled by the
+               * default value of the write enable, so nothing should
+               * every make it into the memory. */
+            case (None, None) =>
+              /* Palmer: If there's no input ports at all (ie, read-only
+               * port on the memory) then just don't worry about it,
+               * there's nothing to do. */
+            case (Some(PolarizedPort(mem, _)), None) =>
+              System.err println "WARNING: Unable to match input ports on memory"
+              System.err println s"  outer input port: ${mem}"
+              return None
+          }
+
+          // Mask port mapping
+          val memMask = memPort.src.maskPort match {
+            case Some(PolarizedPort(mem, _)) =>
+              /* Palmer: The bits from the outer memory's write mask that will be
+               * used as the write mask for this inner memory. */
+              if (libPort.src.effectiveMaskGran == libPort.src.width) {
+                bits(WRef(mem), low / memPort.src.effectiveMaskGran)
+              } else {
+                require(libPort.src.effectiveMaskGran == 1, "only single-bit mask supported for now")
+
+                require(isPowerOfTwo(memPort.src.effectiveMaskGran), "only powers of two masks supported for now")
+                require(isPowerOfTwo(libPort.src.effectiveMaskGran), "only powers of two masks supported for now")
+
+                cat(((low to high) map (i => bits(WRef(mem), i / memPort.src.effectiveMaskGran))).reverse)
+              }
+            case None =>
+              /* Palmer: If there is no input port on the source memory port
+               * then we don't ever want to turn on this write
+               * enable.  Otherwise, we just _always_ turn on the
+               * write enable port on the inner memory. */
+              if (libPort.src.maskPort.isEmpty) one
+              else {
+                val width = libPort.src.width / libPort.src.effectiveMaskGran
+                val value = (BigInt(1) << width.toInt) - 1
+                UIntLiteral(value, IntWidth(width))
+              }
+          }
+
+          // Write enable port mapping
+          val memWriteEnable = memPort.src.writeEnable match {
+            case Some(PolarizedPort(mem, _)) =>
+              /* Palmer: The outer memory's write enable port, or a constant 1 if
+               * there isn't a write enable port. */
+              WRef(mem)
+            case None =>
+              /* Palmer: If there is no input port on the source memory port
+               * then we don't ever want to turn on this write
+               * enable.  Otherwise, we just _always_ turn on the
+               * write enable port on the inner memory. */
+              if (memPort.src.input.isEmpty) zero else one
+          }
+
+          // Chip enable port mapping
+          val memChipEnable = memPort.src.chipEnable match {
+            case Some(PolarizedPort(mem, _)) => WRef(mem)
+            case None      => one
+          }
+
+          // Read enable port mapping
+          /* Palmer: It's safe to ignore read enables, but we pass them through
+           * to the vendor memory if there's a port on there that
+           * implements the read enables. */
+          (memPort.src.readEnable, libPort.src.readEnable) match {
+            case (_, None) =>
+            case (Some(PolarizedPort(mem, _)), Some(PolarizedPort(lib, lib_polarity))) =>
+              stmts += connectPorts(andAddrMatch(WRef(mem)), lib, lib_polarity)
+            case (None, Some(PolarizedPort(lib, lib_polarity))) =>
+              stmts += connectPorts(andAddrMatch(not(memWriteEnable)), lib, lib_polarity)
+          }
+
+          /* Palmer: This is actually the memory compiler: it figures out how to
+           * implement the outer memory's collection of ports using what
+           * the inner memory has availiable. */
+          ((libPort.src.maskPort, libPort.src.writeEnable, libPort.src.chipEnable): @unchecked) match {
+            case (Some(PolarizedPort(mask, mask_polarity)), Some(PolarizedPort(we, we_polarity)), Some(PolarizedPort(en, en_polarity))) =>
+              /* Palmer: This is the simple option: every port exists. */
+              stmts += connectPorts(memMask, mask, mask_polarity)
+              stmts += connectPorts(andAddrMatch(memWriteEnable), we, we_polarity)
+              stmts += connectPorts(andAddrMatch(memChipEnable), en, en_polarity)
+            case (Some(PolarizedPort(mask, mask_polarity)), Some(PolarizedPort(we, we_polarity)), None) =>
+              /* Palmer: If we don't have a chip enable but do have mask ports. */
+              stmts += connectPorts(memMask, mask, mask_polarity)
+              stmts += connectPorts(andAddrMatch(and(memWriteEnable, memChipEnable)),
+                                    we, mask_polarity)
+            case (None, Some(PolarizedPort(we, we_polarity)), chipEnable) if bitWidth(memMask.tpe) == 1 =>
+              /* Palmer: If we're expected to provide mask ports without a
+               * memory that actually has them then we can use the
+               * write enable port instead of the mask port. */
+              stmts += connectPorts(andAddrMatch(and(memWriteEnable, memMask)),
+                                    we, we_polarity)
+              chipEnable match {
+                case Some(PolarizedPort(en, en_polarity)) => {
+                  stmts += connectPorts(andAddrMatch(memChipEnable), en, en_polarity)
+                }
+                case _ => // TODO: do we care about the case where mem has chipEnable but lib doesn't?
+              }
+            case (None, Some(PolarizedPort(we, we_polarity)), Some(PolarizedPort(en, en_polarity))) =>
+              // TODO
+              System.err.println("cannot emulate multi-bit mask ports with write enable")
+              return None
+            case (None, None, None) =>
+              /* Palmer: There's nothing to do here since there aren't any
+               * ports to match up. */
+          }
+        }
+        // Cat macro outputs for selection
+        memPort.src.output match {
+          case Some(PolarizedPort(mem, _)) if cats.nonEmpty =>
+            val name = s"${mem}_${i}"
+            stmts += DefNode(NoInfo, name, cat(cats.toSeq.reverse))
+            (outputs getOrElseUpdate (mem, ArrayBuffer[(Expression, Expression)]())) +=
+              (addrMatch -> WRef(name))
+          case _ =>
+        }
+      }
+    }
+    // Connect mem outputs
+    mem.src.ports foreach { port =>
+      port.output match {
+        case Some(PolarizedPort(mem, _)) => outputs get mem match {
+          case Some(select) =>
+            val output = (select foldRight (zero: Expression)) {
+              case ((cond, tval), fval) => Mux(cond, tval, fval, fval.tpe) }
+            stmts += Connect(NoInfo, WRef(mem), output)
+          case None =>
+        }
+        case None =>
+      }
+    }
+
+    Some((mem.module(Block(stmts.toSeq)), lib.blackbox))
+  }
+
+  def run(c: Circuit): Circuit = {
+    val modules = (mems, libs) match {
+      case (Some(mems), Some(libs)) => (mems foldLeft c.modules){ (modules, mem) =>
+        val (best, cost) = (libs foldLeft (None: Option[(Module, ExtModule)], BigInt(Long.MaxValue))){
+          case ((best, area), lib) if mem.src.ports.size != lib.src.ports.size =>
+            /* Palmer: FIXME: This just assumes the Chisel and vendor ports are in the same
+             * order, but I'm starting with what actually gets generated. */
+            System.err println s"INFO: unable to compile ${mem.src.name} using ${lib.src.name} port count must match"
+            (best, area)
+          case ((best, area), lib) =>
+            /* Palmer: A quick cost function (that must be kept in sync with
+             * memory_cost()) that attempts to avoid compiling unncessary
+             * memories.  This is a lower bound on the cost of compiling a
+             * memory: it assumes 100% bit-cell utilization when mapping. */
+            // val cost = 100 * (mem.depth * mem.width) / (lib.depth * lib.width) +
+            //                  (mem.depth * mem.width)
+            // Donggyu: I re-define cost
+            val cost = (((mem.src.depth - 1) / lib.src.depth) + 1) *
+                       (((mem.src.width - 1) / lib.src.width) + 1) *
+                       (lib.src.depth * lib.src.width + 1) // weights on # cells
+            System.err.println(s"Cost of ${lib.src.name} for ${mem.src.name}: ${cost}")
+            if (cost > area) (best, area)
+            else compile(mem, lib) match {
+              case None => (best, area)
+              case Some(p) => (Some(p), cost)
+            }
+        }
+        best match {
+          case None => modules
+          case Some((mod, bb)) =>
+            (modules filterNot (m => m.name == mod.name || m.name == bb.name)) ++ Seq(mod, bb)
+        }
+      }
+      case _ => c.modules
+    }
+    c.copy(modules = modules)
+  }
+}
+
+class MacroCompilerTransform extends Transform {
+  def inputForm = HighForm
+  def outputForm = HighForm
+  def execute(state: CircuitState) = getMyAnnotations(state) match {
+    case Seq(MacroCompilerAnnotation(state.circuit.main, memFile, libFile, synflops)) =>
+      require(memFile.isDefined)
+      // Read, eliminate None, get only SRAM, make firrtl macro
+      val mems: Option[Seq[Macro]] = mdf.macrolib.Utils.readMDFFromPath(memFile) match {
+        case Some(x:Seq[mdf.macrolib.Macro]) =>
+          Some(Utils.filterForSRAM(Some(x)) getOrElse(List()) map {new Macro(_)})
+        case _ => None
+      }
+      val libs: Option[Seq[Macro]] = mdf.macrolib.Utils.readMDFFromPath(libFile) match {
+        case Some(x:Seq[mdf.macrolib.Macro]) =>
+          Some(Utils.filterForSRAM(Some(x)) getOrElse(List()) map {new Macro(_)})
+        case _ => None
+      }
+      val transforms = Seq(
+        new MacroCompilerPass(mems, libs),
+        new SynFlopsPass(synflops, libs getOrElse mems.get),
+        firrtl.passes.SplitExpressions
+      )
+      ((transforms foldLeft state)((s, xform) => xform runTransform s))
+  }
+}
+
+class MacroCompiler extends Compiler {
+  def emitter = new VerilogEmitter
+  def transforms =
+    Seq(new MacroCompilerTransform) ++
+    getLoweringTransforms(firrtl.HighForm, firrtl.LowForm) // ++
+    // Seq(new LowFirrtlOptimization) // Todo: This is dangerous
+}
+
+object MacroCompiler extends App {
+  sealed trait MacroParam
+  case object Macros extends MacroParam
+  case object Library extends MacroParam
+  case object Verilog extends MacroParam
+  type MacroParamMap = Map[MacroParam, String]
+  val usage = Seq(
+    "Options:",
+    "  -m, --macro-list: The set of macros to compile",
+    "  -l, --library: The set of macros that have blackbox instances",
+    "  -v, --verilog: Verilog output",
+    "  --syn-flop: Produces synthesizable flop-based memories (for all memories and library memory macros); likely useful for simulation purposes") mkString "\n"
+
+  def parseArgs(map: MacroParamMap, synflops: Boolean, args: List[String]): (MacroParamMap, Boolean) =
+    args match {
+      case Nil => (map, synflops)
+      case ("-m" | "--macro-list") :: value :: tail =>
+        parseArgs(map + (Macros  -> value), synflops, tail)
+      case ("-l" | "--library") :: value :: tail =>
+        parseArgs(map + (Library -> value), synflops, tail)
+      case ("-v" | "--verilog") :: value :: tail =>
+        parseArgs(map + (Verilog -> value), synflops, tail)
+      case "--syn-flops" :: tail =>
+        parseArgs(map, true, tail)
+      case arg :: tail =>
+        println(s"Unknown field $arg\n")
+        throw new Exception(usage)
+    }
+
+  def run(args: List[String]) {
+    val (params, synflops) = parseArgs(Map[MacroParam, String](), false, args)
+    try {
+      val macros = Utils.filterForSRAM(mdf.macrolib.Utils.readMDFFromPath(params.get(Macros))).get map (x => (new Macro(x)).blackbox)
+
+      // Open the writer for the output Verilog file.
+      val verilogWriter = new FileWriter(new File(params.get(Verilog).get))
+
+      if (macros.nonEmpty) {
+        val circuit = Circuit(NoInfo, macros, macros.last.name)
+        val annotations = AnnotationMap(Seq(MacroCompilerAnnotation(
+          circuit.main, params.get(Macros).get, params.get(Library), synflops)))
+        val state = CircuitState(circuit, HighForm, Some(annotations))
+
+        // Run the compiler.
+        val result = new MacroCompiler().compileAndEmit(state)
+
+        // Extract Verilog circuit and write it.
+        verilogWriter.write(result.getEmittedCircuit.value)
+      }
+
+      // Close the writer.
+      verilogWriter.close()
+
+    } catch {
+      case e: java.util.NoSuchElementException =>
+        throw new Exception(usage)
+      case e: Throwable =>
+        throw e
+    }
+  }
+
+  run(args.toList)
+}
--- a/macros/src/main/scala/SynFlops.scala
+++ b/macros/src/main/scala/SynFlops.scala
@@ -0,0 +1,110 @@
+// See LICENSE for license details.
+
+package barstools.macros
+
+import firrtl._
+import firrtl.ir._
+import firrtl.Utils._
+import firrtl.passes.MemPortUtils.{memPortField, memType}
+import Utils._
+
+class SynFlopsPass(synflops: Boolean, libs: Seq[Macro]) extends firrtl.passes.Pass {
+  lazy val libMods = (libs map { lib => lib.src.name -> {
+    val dataType = (lib.src.ports foldLeft (None: Option[BigInt]))((res, port) =>
+      (res, port.maskPort) match {
+        case (_, None) =>
+          res
+        case (None, Some(_)) =>
+          Some(port.effectiveMaskGran)
+        case (Some(x), Some(_)) =>
+          assert(x == port.effectiveMaskGran)
+          res
+      }
+    ) match {
+      case None => UIntType(IntWidth(lib.src.width))
+      case Some(gran) => VectorType(UIntType(IntWidth(gran)), (lib.src.width / gran).toInt)
+    }
+
+    val mem = DefMemory(
+      NoInfo,
+      "ram",
+      dataType,
+      lib.src.depth,
+      1, // writeLatency
+      0, // readLatency
+      (lib.readers ++ lib.readwriters).indices map (i => s"R_$i"),
+      (lib.writers ++ lib.readwriters).indices map (i => s"W_$i"),
+      Nil
+    )
+
+    val readConnects = (lib.readers ++ lib.readwriters).zipWithIndex flatMap { case (r, i) =>
+      val clock = portToExpression(r.src.clock)
+      val address = portToExpression(r.src.address)
+      val enable = (r.src chipEnable, r.src readEnable) match {
+        case (Some(en_port), Some(re_port)) =>
+          and(portToExpression(en_port),
+              portToExpression(re_port))
+        case (Some(en_port), None) => portToExpression(en_port)
+        case (None, Some(re_port)) => portToExpression(re_port)
+        case (None, None) => one
+      }
+      val data = memPortField(mem, s"R_$i", "data")
+      val read = (dataType: @unchecked) match {
+        case VectorType(tpe, size) => cat(((0 until size) map (k =>
+          WSubIndex(data, k, tpe, UNKNOWNGENDER))).reverse)
+        case _: UIntType => data
+      }
+      val addrReg = WRef(s"R_${i}_addr_reg", r.addrType, RegKind)
+      Seq(
+        DefRegister(NoInfo, addrReg.name, r.addrType, clock, zero, addrReg),
+        Connect(NoInfo, memPortField(mem, s"R_$i", "clk"), clock),
+        Connect(NoInfo, memPortField(mem, s"R_$i", "addr"), addrReg),
+        Connect(NoInfo, memPortField(mem, s"R_$i", "en"), enable),
+        Connect(NoInfo, WRef(r.src.output.get.name), read),
+        Connect(NoInfo, addrReg, Mux(enable, address, addrReg, UnknownType))
+      )
+    }
+
+    val writeConnects = (lib.writers ++ lib.readwriters).zipWithIndex flatMap { case (w, i) =>
+      val clock = portToExpression(w.src.clock)
+      val address = portToExpression(w.src.address)
+      val enable = (w.src.chipEnable, w.src.writeEnable) match {
+        case (Some(en), Some(we)) =>
+          and(portToExpression(en),
+              portToExpression(we))
+        case (Some(en), None) => portToExpression(en)
+        case (None, Some(we)) => portToExpression(we)
+        case (None, None) => zero // is it possible?
+      }
+      val mask = memPortField(mem, s"W_$i", "mask")
+      val data = memPortField(mem, s"W_$i", "data")
+      val write = portToExpression(w.src.input.get)
+      Seq(
+        Connect(NoInfo, memPortField(mem, s"W_$i", "clk"), clock),
+        Connect(NoInfo, memPortField(mem, s"W_$i", "addr"), address),
+        Connect(NoInfo, memPortField(mem, s"W_$i", "en"), enable)
+      ) ++ (dataType match {
+        case VectorType(tpe, size) =>
+          val width = bitWidth(tpe).toInt
+          ((0 until size) map (k =>
+            Connect(NoInfo, WSubIndex(data, k, tpe, UNKNOWNGENDER),
+                            bits(write, (k + 1) * width - 1, k * width)))) ++
+          ((0 until size) map (k =>
+            Connect(NoInfo, WSubIndex(mask, k, BoolType, UNKNOWNGENDER),
+                            bits(WRef(w.src.maskPort.get.name), k))))
+        case _: UIntType =>
+          Seq(Connect(NoInfo, data, write), Connect(NoInfo, mask, one))
+      })
+    }
+    lib.module(Block(mem +: (readConnects ++ writeConnects)))
+  }}).toMap
+
+  def run(c: Circuit): Circuit = {
+    if (!synflops) c
+    else {
+      val circuit = c.copy(modules = (c.modules map (m => libMods getOrElse (m.name, m))))
+      // print(circuit.serialize)
+      circuit
+    }
+  }
+}
--- a/macros/src/main/scala/Utils.scala
+++ b/macros/src/main/scala/Utils.scala
@@ -0,0 +1,99 @@
+// See LICENSE for license details.
+
+package barstools.macros
+
+import firrtl._
+import firrtl.ir._
+import firrtl.PrimOps
+import firrtl.Utils.{ceilLog2, BoolType}
+import mdf.macrolib.{Constant, MacroPort, SRAMMacro}
+import mdf.macrolib.{PolarizedPort, PortPolarity, ActiveLow, ActiveHigh, NegativeEdge, PositiveEdge}
+import java.io.File
+import scala.language.implicitConversions
+
+class FirrtlMacroPort(port: MacroPort) {
+  val src = port
+
+  val isReader = !port.readEnable.isEmpty && port.writeEnable.isEmpty
+  val isWriter = !port.writeEnable.isEmpty && port.readEnable.isEmpty
+  val isReadWriter = !port.writeEnable.isEmpty && !port.readEnable.isEmpty
+
+  val addrType = UIntType(IntWidth(ceilLog2(port.depth) max 1))
+  val dataType = UIntType(IntWidth(port.width))
+  val maskType = UIntType(IntWidth(port.width / port.effectiveMaskGran))
+
+  // Bundle representing this macro port.
+  val tpe = BundleType(Seq(
+    Field(port.clock.name, Flip, ClockType),
+    Field(port.address.name, Flip, addrType)) ++
+    (port.input map (p => Field(p.name, Flip, dataType))) ++
+    (port.output map (p => Field(p.name, Default, dataType))) ++
+    (port.chipEnable map (p => Field(p.name, Flip, BoolType))) ++
+    (port.readEnable map (p => Field(p.name, Flip, BoolType))) ++
+    (port.writeEnable map (p => Field(p.name, Flip, BoolType))) ++
+    (port.maskPort map (p => Field(p.name, Flip, maskType)))
+  )
+  val ports = tpe.fields map (f => Port(
+     NoInfo, f.name, f.flip match { case Default => Output case Flip => Input }, f.tpe))
+}
+
+// Reads an SRAMMacro and generates firrtl blackboxes.
+class Macro(srcMacro: SRAMMacro) {
+  val src = srcMacro
+
+  val firrtlPorts = srcMacro.ports map { new FirrtlMacroPort(_) }
+
+  val writers = firrtlPorts filter (p => p.isReader)
+  val readers = firrtlPorts filter (p => p.isWriter)
+  val readwriters = firrtlPorts filter (p => p.isReadWriter)
+
+  val sortedPorts = writers ++ readers ++ readwriters
+  val extraPorts = srcMacro.extraPorts map { p =>
+    assert(p.portType == Constant) // TODO: release it?
+    val name = p.name
+    val width = BigInt(p.width.toLong)
+    val value = BigInt(p.value.toLong)
+    (name -> UIntLiteral(value, IntWidth(width)))
+  }
+
+  // Bundle representing this memory blackbox
+  val tpe = BundleType(firrtlPorts flatMap (_.tpe.fields))
+
+  private val modPorts = (firrtlPorts flatMap (_.ports)) ++
+    (extraPorts map { case (name, value) => Port(NoInfo, name, Input, value.tpe) })
+  val blackbox = ExtModule(NoInfo, srcMacro.name, modPorts, srcMacro.name, Nil)
+  def module(body: Statement) = Module(NoInfo, srcMacro.name, modPorts, body)
+}
+
+object Utils {
+  def filterForSRAM(s: Option[Seq[mdf.macrolib.Macro]]): Option[Seq[mdf.macrolib.SRAMMacro]] = {
+    s match {
+      case Some(l:Seq[mdf.macrolib.Macro]) => Some(l filter { _.macroType == mdf.macrolib.SRAM } map { m => m.asInstanceOf[mdf.macrolib.SRAMMacro] })
+      case _ => None
+    }
+  }
+
+  def and(e1: Expression, e2: Expression) =
+    DoPrim(PrimOps.And, Seq(e1, e2), Nil, e1.tpe)
+  def bits(e: Expression, high: BigInt, low: BigInt): Expression =
+    DoPrim(PrimOps.Bits, Seq(e), Seq(high, low), UIntType(IntWidth(high-low+1)))
+  def bits(e: Expression, idx: BigInt): Expression = bits(e, idx, idx)
+  def cat(es: Seq[Expression]): Expression =
+    if (es.size == 1) es.head
+    else DoPrim(PrimOps.Cat, Seq(es.head, cat(es.tail)), Nil, UnknownType)
+  def not(e: Expression) =
+    DoPrim(PrimOps.Not, Seq(e), Nil, e.tpe)
+
+  // Convert a port to a FIRRTL expression, handling polarity along the way.
+  def portToExpression(pp: PolarizedPort): Expression =
+    portToExpression(WRef(pp.name), Some(pp.polarity))
+
+  def portToExpression(exp: Expression, polarity: Option[PortPolarity]): Expression =
+    polarity match {
+      case Some(ActiveLow) | Some(NegativeEdge) => not(exp)
+      case _ => exp
+    }
+
+  // Check if a number is a power of two
+  def isPowerOfTwo(x: Int): Boolean = (x & (x - 1)) == 0
+}
--- a/macros/src/test/resources/lib-1024x8-mrw.json
+++ b/macros/src/test/resources/lib-1024x8-mrw.json
@@ -0,0 +1,36 @@
+[
+  {
+    "type": "sram",
+    "name": "vendor_sram",
+    "depth": 1024,
+    "width": 8,
+    "family": "1rw",
+    "ports": [
+      {
+        "clock port name": "clock",
+        "mask granularity": 8,
+        "output port name": "RW0O",
+        "input port name": "RW0I",
+        "address port name": "RW0A",
+        "mask port name": "RW0M",
+        "chip enable port name": "RW0E",
+        "write enable port name": "RW0W",
+        "clock port polarity": "positive edge",
+        "output port polarity": "active high",
+        "input port polarity": "active high",
+        "address port polarity": "active high",
+        "mask port polarity": "active high",
+        "chip enable port polarity": "active high",
+        "write enable port polarity": "active high"
+      }
+    ]
+  },
+  {
+    "type": "metal filler cell",
+    "name": "vender_dcap"
+  },
+  {
+    "type": "filler cell",
+    "name": "vender_fill"
+  }
+]
--- a/macros/src/test/resources/lib-1024x8-n28.json
+++ b/macros/src/test/resources/lib-1024x8-n28.json
@@ -0,0 +1,27 @@
+[
+  {
+    "type": "sram",
+    "name": "vendor_sram",
+    "depth": 1024,
+    "width": 8,
+    "ports": [
+      {
+        "clock port name": "clock",
+        "mask granularity": 1,
+        "output port name": "RW0O",
+        "input port name": "RW0I",
+        "address port name": "RW0A",
+        "mask port name": "RW0M",
+        "chip enable port name": "RW0E",
+        "write enable port name": "RW0W",
+        "clock port polarity": "positive edge",
+        "output port polarity": "active high",
+        "input port polarity": "active high",
+        "address port polarity": "active high",
+        "mask port polarity": "active high",
+        "chip enable port polarity": "active high",
+        "write enable port polarity": "active high"
+      }
+    ]
+  }
+]
--- a/macros/src/test/resources/lib-1024x8-r-mw.json
+++ b/macros/src/test/resources/lib-1024x8-r-mw.json
@@ -0,0 +1,34 @@
+[
+  {
+    "type": "sram",
+    "name": "vendor_sram",
+    "depth": 1024,
+    "width": 8,
+    "ports": [
+      {
+        "clock port name": "clock",
+        "mask granularity": 8,
+        "output port name": "R0O",
+        "address port name": "R0A",
+        "clock port polarity": "positive edge",
+        "output port polarity": "active high",
+        "address port polarity": "active high"
+      },
+      {
+        "clock port name": "clock",
+        "mask granularity": 8,
+        "input port name": "W0I",
+        "address port name": "W0A",
+        "mask port name": "W0M",
+        "chip enable port name": "W0E",
+        "write enable port name": "W0W",
+        "clock port polarity": "positive edge",
+        "input port polarity": "active high",
+        "address port polarity": "active high",
+        "mask port polarity": "active high",
+        "chip enable port polarity": "active high",
+        "write enable port polarity": "active high"
+      }
+    ]
+  }
+]
--- a/macros/src/test/resources/lib-1024x8-sleep.json
+++ b/macros/src/test/resources/lib-1024x8-sleep.json
@@ -0,0 +1,35 @@
+[
+  {
+    "type": "sram",
+    "name": "vendor_sram",
+    "depth": 1024,
+    "width": 8,
+    "ports": [
+      {
+        "clock port name": "clock",
+        "mask granularity": 8,
+        "output port name": "RW0O",
+        "input port name": "RW0I",
+        "address port name": "RW0A",
+        "mask port name": "RW0M",
+        "chip enable port name": "RW0E",
+        "write enable port name": "RW0W",
+        "clock port polarity": "positive edge",
+        "output port polarity": "active high",
+        "input port polarity": "active high",
+        "address port polarity": "active high",
+        "mask port polarity": "active high",
+        "chip enable port polarity": "active high",
+        "write enable port polarity": "active high"
+      }
+    ],
+    "extra ports": [
+      {
+        "name": "sleep",
+        "type": "constant",
+        "width": 1,
+        "value": 0
+      }
+    ]
+  }
+]
--- a/macros/src/test/resources/lib-2048x10-rw.json
+++ b/macros/src/test/resources/lib-2048x10-rw.json
@@ -0,0 +1,24 @@
+[
+  {
+    "type": "sram",
+    "name": "vendor_sram",
+    "depth": 2048,
+    "width": 10,
+    "ports": [
+      {
+        "clock port name": "clock",
+        "output port name": "RW0O",
+        "input port name": "RW0I",
+        "address port name": "RW0A",
+        "chip enable port name": "RW0E",
+        "write enable port name": "RW0W",
+        "clock port polarity": "positive edge",
+        "output port polarity": "active high",
+        "input port polarity": "active high",
+        "address port polarity": "active high",
+        "chip enable port polarity": "active high",
+        "write enable port polarity": "active high"
+      }
+    ]
+  }
+]
--- a/macros/src/test/resources/lib-2048x16-n28.json
+++ b/macros/src/test/resources/lib-2048x16-n28.json
@@ -0,0 +1,52 @@
+[
+  {
+    "type": "sram",
+    "name": "vendor_sram_16",
+    "depth": 2048,
+    "width": 16,
+    "ports": [
+      {
+        "clock port name": "clock",
+        "mask granularity": 1,
+        "output port name": "RW0O",
+        "input port name": "RW0I",
+        "address port name": "RW0A",
+        "mask port name": "RW0M",
+        "chip enable port name": "RW0E",
+        "write enable port name": "RW0W",
+        "clock port polarity": "positive edge",
+        "output port polarity": "active high",
+        "input port polarity": "active high",
+        "address port polarity": "active high",
+        "mask port polarity": "active high",
+        "chip enable port polarity": "active high",
+        "write enable port polarity": "active high"
+      }
+    ]
+  },
+  {
+    "type": "sram",
+    "name": "vendor_sram_4",
+    "depth": 2048,
+    "width": 4,
+    "ports": [
+      {
+        "clock port name": "clock",
+        "mask granularity": 1,
+        "output port name": "RW0O",
+        "input port name": "RW0I",
+        "address port name": "RW0A",
+        "mask port name": "RW0M",
+        "chip enable port name": "RW0E",
+        "write enable port name": "RW0W",
+        "clock port polarity": "positive edge",
+        "output port polarity": "active high",
+        "input port polarity": "active high",
+        "address port polarity": "active high",
+        "mask port polarity": "active high",
+        "chip enable port polarity": "active high",
+        "write enable port polarity": "active high"
+      }
+    ]
+  }
+]
--- a/macros/src/test/resources/lib-2048x8-mrw-re.json
+++ b/macros/src/test/resources/lib-2048x8-mrw-re.json
@@ -0,0 +1,29 @@
+[
+  {
+    "type": "sram",
+    "name": "vendor_sram",
+    "depth": 2048,
+    "width": 8,
+    "ports": [
+      {
+        "clock port name": "clock",
+        "mask granularity": 8,
+        "output port name": "RW0O",
+        "input port name": "RW0I",
+        "address port name": "RW0A",
+        "mask port name": "RW0M",
+        "chip enable port name": "RW0E",
+        "write enable port name": "RW0W",
+        "read enable port name": "RW0R",
+        "clock port polarity": "positive edge",
+        "output port polarity": "active high",
+        "input port polarity": "active high",
+        "address port polarity": "active high",
+        "mask port polarity": "active high",
+        "chip enable port polarity": "active high",
+        "write enable port polarity": "active high",
+        "read enable port polarity": "active low"
+      }
+    ]
+  }
+]
--- a/macros/src/test/resources/lib-2048x8-mrw.json
+++ b/macros/src/test/resources/lib-2048x8-mrw.json
@@ -0,0 +1,27 @@
+[
+  {
+    "type": "sram",
+    "name": "vendor_sram",
+    "depth": 2048,
+    "width": 8,
+    "ports": [
+      {
+        "clock port name": "clock",
+        "mask granularity": 8,
+        "output port name": "RW0O",
+        "input port name": "RW0I",
+        "address port name": "RW0A",
+        "mask port name": "RW0M",
+        "chip enable port name": "RW0E",
+        "write enable port name": "RW0W",
+        "clock port polarity": "positive edge",
+        "output port polarity": "active high",
+        "input port polarity": "active high",
+        "address port polarity": "active high",
+        "mask port polarity": "active high",
+        "chip enable port polarity": "active high",
+        "write enable port polarity": "active high"
+      }
+    ]
+  }
+]
--- a/macros/src/test/resources/lib-32x32-2rw.json
+++ b/macros/src/test/resources/lib-32x32-2rw.json
@@ -0,0 +1,43 @@
+[
+  {
+    "name": "SRAM2RW32x32",
+    "type": "sram",
+    "family": "2rw",
+    "depth": 32,
+    "width": 32,
+    "ports": [
+      {
+        "clock port name": "CE1",
+        "clock port polarity": "positive edge",
+        "address port name": "A1",
+        "address port polarity": "active high",
+        "input port name": "I1",
+        "input port polarity": "active high",
+        "output port name": "O1",
+        "output port polarity": "active high",
+        "read enable port name": "OEB1",
+        "read enable port polarity": "active low",
+        "write enable port name": "WEB1",
+        "write enable port polarity": "active low",
+        "chip enable port name": "CSB1",
+        "chip enable port polarity": "active low"
+      },
+      {
+        "clock port name": "CE2",
+        "clock port polarity": "positive edge",
+        "address port name": "A2",
+        "address port polarity": "active high",
+        "input port name": "I2",
+        "input port polarity": "active high",
+        "output port name": "O2",
+        "output port polarity": "active high",
+        "read enable port name": "OEB2",
+        "read enable port polarity": "active low",
+        "write enable port name": "WEB2",
+        "write enable port polarity": "active low",
+        "chip enable port name": "CSB2",
+        "chip enable port polarity": "active low"
+      }
+    ]
+  }
+]
--- a/macros/src/test/resources/lib-32x80-mrw.json
+++ b/macros/src/test/resources/lib-32x80-mrw.json
@@ -0,0 +1,27 @@
+[
+  {
+    "type": "sram",
+    "name": "vendor_sram",
+    "depth": 32,
+    "width": 80,
+    "ports": [
+      {
+        "clock port name": "clock",
+        "mask granularity": 1,
+        "output port name": "RW0O",
+        "input port name": "RW0I",
+        "address port name": "RW0A",
+        "mask port name": "RW0M",
+        "chip enable port name": "RW0E",
+        "write enable port name": "RW0W",
+        "clock port polarity": "positive edge",
+        "output port polarity": "active high",
+        "input port polarity": "active high",
+        "address port polarity": "active high",
+        "mask port polarity": "active high",
+        "chip enable port polarity": "active high",
+        "write enable port polarity": "active high"
+      }
+    ]
+  }
+]
--- a/macros/src/test/resources/mem-2000x8-mrw.json
+++ b/macros/src/test/resources/mem-2000x8-mrw.json
@@ -0,0 +1,27 @@
+[
+  {
+    "type": "sram",
+    "name": "name_of_sram_module",
+    "depth": 2000,
+    "width": 8,
+    "ports": [
+      {
+        "clock port name": "clock",
+        "clock port polarity": "positive edge",
+        "mask granularity": 8,
+        "output port name": "RW0O",
+        "output port polarity": "active high",
+        "input port name": "RW0I",
+        "input port polarity": "active high",
+        "address port name": "RW0A",
+        "address port polarity": "active high",
+        "mask port name": "RW0M",
+        "mask port polarity": "active high",
+        "chip enable port name": "RW0E",
+        "chip enable port polarity": "active high",
+        "write enable port name": "RW0W",
+        "write enable port polarity": "active high"
+      }
+    ]
+  }
+]
--- a/macros/src/test/resources/mem-2048x16-mrw-2.json
+++ b/macros/src/test/resources/mem-2048x16-mrw-2.json
@@ -0,0 +1,27 @@
+[
+  {
+    "type": "sram",
+    "name": "name_of_sram_module",
+    "depth": 2048,
+    "width": 16,
+    "ports": [
+      {
+        "clock port name": "clock",
+        "clock port polarity": "positive edge",
+        "mask granularity": 2,
+        "output port name": "RW0O",
+        "output port polarity": "active high",
+        "input port name": "RW0I",
+        "input port polarity": "active high",
+        "address port name": "RW0A",
+        "address port polarity": "active high",
+        "mask port name": "RW0M",
+        "mask port polarity": "active high",
+        "chip enable port name": "RW0E",
+        "chip enable port polarity": "active high",
+        "write enable port name": "RW0W",
+        "write enable port polarity": "active high"
+      }
+    ]
+  }
+]
--- a/macros/src/test/resources/mem-2048x16-mrw.json
+++ b/macros/src/test/resources/mem-2048x16-mrw.json
@@ -0,0 +1,27 @@
+[
+  {
+    "type": "sram",
+    "name": "name_of_sram_module",
+    "depth": 2048,
+    "width": 16,
+    "ports": [
+      {
+        "clock port name": "clock",
+        "clock port polarity": "positive edge",
+        "mask granularity": 8,
+        "output port name": "RW0O",
+        "output port polarity": "active high",
+        "input port name": "RW0I",
+        "input port polarity": "active high",
+        "address port name": "RW0A",
+        "address port polarity": "active high",
+        "mask port name": "RW0M",
+        "mask port polarity": "active high",
+        "chip enable port name": "RW0E",
+        "chip enable port polarity": "active high",
+        "write enable port name": "RW0W",
+        "write enable port polarity": "active high"
+      }
+    ]
+  }
+]
--- a/macros/src/test/resources/mem-2048x20-mrw.json
+++ b/macros/src/test/resources/mem-2048x20-mrw.json
@@ -0,0 +1,28 @@
+[
+  {
+    "type": "sram",
+    "name": "name_of_sram_module",
+    "depth": 2048,
+    "width": 20,
+    "ports": [
+      {
+        "clock port name": "clock",
+        "clock port polarity": "positive edge",
+        "mask granularity": 10,
+        "output port name": "RW0O",
+        "output port polarity": "active high",
+        "input port name": "RW0I",
+        "input port polarity": "active high",
+        "address port name": "RW0A",
+        "address port polarity": "active high",
+        "mask port name": "RW0M",
+        "mask port polarity": "active high",
+        "chip enable port name": "RW0E",
+        "chip enable port polarity": "active high",
+        "write enable port name": "RW0W",
+        "write enable port polarity": "active high"
+      }
+    ]
+  }
+]
+
--- a/macros/src/test/resources/mem-2048x8-mrw.json
+++ b/macros/src/test/resources/mem-2048x8-mrw.json
@@ -0,0 +1,28 @@
+[
+  {
+    "type": "sram",
+    "name": "name_of_sram_module",
+    "depth": 2048,
+    "width": 8,
+    "family": "1rw",
+    "ports": [
+      {
+        "clock port name": "clock",
+        "clock port polarity": "positive edge",
+        "mask granularity": 8,
+        "output port name": "RW0O",
+        "output port polarity": "active high",
+        "input port name": "RW0I",
+        "input port polarity": "active high",
+        "address port name": "RW0A",
+        "address port polarity": "active high",
+        "mask port name": "RW0M",
+        "mask port polarity": "active high",
+        "chip enable port name": "RW0E",
+        "chip enable port polarity": "active high",
+        "write enable port name": "RW0W",
+        "write enable port polarity": "active high"
+      }
+    ]
+  }
+]
--- a/macros/src/test/resources/mem-2048x8-r-mw.json
+++ b/macros/src/test/resources/mem-2048x8-r-mw.json
@@ -0,0 +1,31 @@
+[
+  {
+    "type": "sram",
+    "name": "name_of_sram_module",
+    "depth": 2048,
+    "width": 8,
+    "ports": [
+      {
+        "clock port name": "clock",
+        "clock port polarity": "positive edge",
+        "mask granularity": 8,
+        "input port name": "W0I",
+        "input port polarity": "active high",
+        "address port name": "W0A",
+        "address port polarity": "active high",
+        "mask port name": "W0M",
+        "mask port polarity": "active high",
+        "chip enable port name": "W0E",
+        "chip enable port polarity": "active high"
+      },
+      {
+        "clock port name": "clock",
+        "clock port polarity": "positive edge",
+        "output port name": "R0O",
+        "output port polarity": "active high",
+        "address port name": "R0A",
+        "address port polarity": "active high"
+      }
+    ]
+  }
+]
--- a/macros/src/test/resources/mem-24x52-r-w.json
+++ b/macros/src/test/resources/mem-24x52-r-w.json
@@ -0,0 +1,22 @@
+[
+  {
+    "type": "sram",
+    "name": "entries_info_ext",
+    "depth": 24,
+    "width": 52,
+    "ports": [
+      {
+        "clock port name": "R0_clk",
+        "output port name": "R0_data",
+        "address port name": "R0_addr",
+        "chip enable port name": "R0_en"
+      },
+      {
+        "clock port name": "W0_clk",
+        "input port name": "W0_data",
+        "address port name": "W0_addr",
+        "chip enable port name": "W0_en"
+      }
+    ]
+  }
+]
--- a/macros/src/test/resources/mem-32x160-mrw.json
+++ b/macros/src/test/resources/mem-32x160-mrw.json
@@ -0,0 +1,27 @@
+[
+  {
+    "type": "sram",
+    "name": "name_of_sram_module",
+    "depth": 32,
+    "width": 160,
+    "ports": [
+      {
+        "clock port name": "clock",
+        "clock port polarity": "positive edge",
+        "mask granularity": 20,
+        "output port name": "RW0O",
+        "output port polarity": "active high",
+        "input port name": "RW0I",
+        "input port polarity": "active high",
+        "address port name": "RW0A",
+        "address port polarity": "active high",
+        "mask port name": "RW0M",
+        "mask port polarity": "active high",
+        "chip enable port name": "RW0E",
+        "chip enable port polarity": "active high",
+        "write enable port name": "RW0W",
+        "write enable port polarity": "active high"
+      }
+    ]
+  }
+]
--- a/macros/src/test/resources/mylib.json
+++ b/macros/src/test/resources/mylib.json
@@ -0,0 +1,186 @@
+[
+  {
+    "type": "sram",
+    "name": "SRAM1RW1024x8",
+    "width": 8,
+    "depth": 1024,
+    "ports": [
+      {
+        "address port name": "A",
+        "address port polarity": "active high",
+        "clock port name": "CE",
+        "clock port polarity": "positive edge",
+        "write enable port name": "WEB",
+        "write enable port polarity": "active low",
+        "read enable port name": "OEB",
+        "read enable port polarity": "active low",
+        "chip enable port name": "CEB",
+        "chip enable port polarity": "active low",
+        "output port name": "O",
+        "output port polarity": "active high",
+        "input port name": "I",
+        "input port polarity": "active high"
+      }
+    ]
+  },
+  {
+    "type": "sram",
+    "name": "SRAM1RW512x32",
+    "width": 32,
+    "depth": 512,
+    "ports": [
+      {
+        "address port name": "A",
+        "address port polarity": "active high",
+        "clock port name": "CE",
+        "clock port polarity": "positive edge",
+        "write enable port name": "WEB",
+        "write enable port polarity": "active low",
+        "read enable port name": "OEB",
+        "read enable port polarity": "active low",
+        "chip enable port name": "CEB",
+        "chip enable port polarity": "active low",
+        "output port name": "O",
+        "output port polarity": "active high",
+        "input port name": "I",
+        "input port polarity": "active high"
+      }
+    ]
+  },
+  {
+    "type": "sram",
+    "name": "SRAM1RW64x128",
+    "width": 128,
+    "depth": 64,
+    "ports": [
+      {
+        "address port name": "A",
+        "address port polarity": "active high",
+        "clock port name": "CE",
+        "clock port polarity": "positive edge",
+        "write enable port name": "WEB",
+        "write enable port polarity": "active low",
+        "read enable port name": "OEB",
+        "read enable port polarity": "active low",
+        "chip enable port name": "CEB",
+        "chip enable port polarity": "active low",
+        "output port name": "O",
+        "output port polarity": "active high",
+        "input port name": "I",
+        "input port polarity": "active high"
+      }
+    ]
+  },
+  {
+    "type": "sram",
+    "name": "SRAM1RW64x32",
+    "width": 32,
+    "depth": 64,
+    "ports": [
+      {
+        "address port name": "A",
+        "address port polarity": "active high",
+        "clock port name": "CE",
+        "clock port polarity": "positive edge",
+        "write enable port name": "WEB",
+        "write enable port polarity": "active low",
+        "read enable port name": "OEB",
+        "read enable port polarity": "active low",
+        "chip enable port name": "CEB",
+        "chip enable port polarity": "active low",
+        "output port name": "O",
+        "output port polarity": "active high",
+        "input port name": "I",
+        "input port polarity": "active high"
+      }
+    ]
+  },
+  {
+    "type": "sram",
+    "name": "SRAM1RW64x8",
+    "width": 8,
+    "depth": 64,
+    "ports": [
+      {
+        "address port name": "A",
+        "address port polarity": "active high",
+        "clock port name": "CE",
+        "clock port polarity": "positive edge",
+        "write enable port name": "WEB",
+        "write enable port polarity": "active low",
+        "read enable port name": "OEB",
+        "read enable port polarity": "active low",
+        "chip enable port name": "CEB",
+        "chip enable port polarity": "active low",
+        "output port name": "O",
+        "output port polarity": "active high",
+        "input port name": "I",
+        "input port polarity": "active high"
+      }
+    ]
+  },
+  {
+    "type": "sram",
+    "name": "SRAM1RW512x8",
+    "width": 8,
+    "depth": 512,
+    "ports": [
+      {
+        "address port name": "A",
+        "address port polarity": "active high",
+        "clock port name": "CE",
+        "clock port polarity": "positive edge",
+        "write enable port name": "WEB",
+        "write enable port polarity": "active low",
+        "read enable port name": "OEB",
+        "read enable port polarity": "active low",
+        "chip enable port name": "CEB",
+        "chip enable port polarity": "active low",
+        "output port name": "O",
+        "output port polarity": "active high",
+        "input port name": "I",
+        "input port polarity": "active high"
+      }
+    ]
+  },
+  {
+    "type": "sram",
+    "name": "SRAM2RW64x32",
+    "width": 32,
+    "depth": 64,
+    "ports": [
+      {
+        "address port name": "A1",
+        "address port polarity": "active high",
+        "clock port name": "CE1",
+        "clock port polarity": "positive edge",
+        "write enable port name": "WEB1",
+        "write enable port polarity": "active low",
+        "read enable port name": "OEB1",
+        "read enable port polarity": "active low",
+        "chip enable port name": "CEB1",
+        "chip enable port polarity": "active low",
+        "output port name": "O1",
+        "output port polarity": "active high",
+        "input port name": "I1",
+        "input port polarity": "active high"
+      },
+      {
+        "address port name": "A2",
+        "address port polarity": "active high",
+        "clock port name": "CE2",
+        "clock port polarity": "positive edge",
+        "write enable port name": "WEB2",
+        "write enable port polarity": "active low",
+        "read enable port name": "OEB2",
+        "read enable port polarity": "active low",
+        "chip enable port name": "CEB2",
+        "chip enable port polarity": "active low",
+        "output port name": "O2",
+        "output port polarity": "active high",
+        "input port name": "I2",
+        "input port polarity": "active high"
+      }
+    ]
+  }
+]
--- a/macros/src/test/resources/rocketchip.json
+++ b/macros/src/test/resources/rocketchip.json
@@ -0,0 +1,76 @@
+[
+  {
+    "type": "sram",
+    "name": "tag_array_ext",
+    "depth": 64,
+    "width": 80,
+    "ports": [
+      {
+        "clock port name": "RW0_clk",
+        "mask granularity": 20,
+        "output port name": "RW0_rdata",
+        "input port name": "RW0_wdata",
+        "address port name": "RW0_addr",
+        "mask port name": "RW0_wmask",
+        "chip enable port name": "RW0_en",
+        "write enable port name": "RW0_wmode"
+      }
+    ]
+  },
+  {
+    "type": "sram",
+    "name": "T_1090_ext",
+    "depth": 512,
+    "width": 64,
+    "ports": [
+      {
+        "clock port name": "RW0_clk",
+        "output port name": "RW0_rdata",
+        "input port name": "RW0_wdata",
+        "address port name": "RW0_addr",
+        "chip enable port name": "RW0_en",
+        "write enable port name": "RW0_wmode"
+      }
+    ]
+  },
+  {
+    "type": "sram",
+    "name": "T_406_ext",
+    "depth": 512,
+    "width": 64,
+    "ports": [
+      {
+        "clock port name": "RW0_clk",
+        "mask granularity": 8,
+        "output port name": "RW0_rdata",
+        "input port name": "RW0_wdata",
+        "address port name": "RW0_addr",
+        "mask port name": "RW0_wmask",
+        "chip enable port name": "RW0_en",
+        "write enable port name": "RW0_wmode"
+      }
+    ]
+  },
+  {
+    "type": "sram",
+    "name": "T_2172_ext",
+    "depth": 64,
+    "width": 88,
+    "ports": [
+      {
+        "clock port name": "W0_clk",
+        "mask granularity": 22,
+        "input port name": "W0_data",
+        "address port name": "W0_addr",
+        "chip enable port name": "W0_en",
+        "mask port name": "W0_mask"
+      },
+      {
+        "clock port name": "R0_clk",
+        "output port name": "R0_data",
+        "address port name": "R0_addr",
+        "chip enable port name": "R0_en"
+      }
+    ]
+  }
+]
--- a/macros/src/test/scala/MacroCompilerSpec.scala
+++ b/macros/src/test/scala/MacroCompilerSpec.scala
@@ -0,0 +1,381 @@
+package barstools.macros
+
+import firrtl.ir.{Circuit, NoInfo}
+import firrtl.passes.RemoveEmpty
+import firrtl.Parser.parse
+import java.io.{File, StringWriter}
+
+// TODO: we should think of a less brittle way to run these tests.
+
+abstract class MacroCompilerSpec extends org.scalatest.FlatSpec with org.scalatest.Matchers {
+  val macroDir: String = "tapeout/src/test/resources/macros"
+  val testDir: String = "test_run_dir/macros"
+  new File(testDir).mkdirs // Make sure the testDir exists
+
+  // Override these to change the prefixing of macroDir and testDir
+  val memPrefix: String = macroDir
+  val libPrefix: String = macroDir
+  val vPrefix: String = testDir
+
+  private def args(mem: String, lib: Option[String], v: String, synflops: Boolean) =
+    List("-m", mem.toString, "-v", v) ++
+    (lib match { case None => Nil case Some(l) => List("-l", l.toString) }) ++
+    (if (synflops) List("--syn-flops") else Nil)
+
+  // Run the full compiler as if from the command line interface.
+  // Generates the Verilog; useful in testing since an error will throw an
+  // exception.
+  def compile(mem: String, lib: String, v: String, synflops: Boolean) {
+    compile(mem, Some(lib), v, synflops)
+  }
+  def compile(mem: String, lib: Option[String], v: String, synflops: Boolean) {
+    var mem_full = concat(memPrefix, mem)
+    var lib_full = concat(libPrefix, lib)
+    var v_full = concat(vPrefix, v)
+
+    MacroCompiler.run(args(mem_full, lib_full, v_full, synflops))
+  }
+
+  // Helper functions to write macro libraries to the given files.
+  def writeToLib(lib: String, libs: Seq[mdf.macrolib.Macro]) = {
+    mdf.macrolib.Utils.writeMDFToPath(Some(concat(libPrefix, lib)), libs)
+  }
+
+  def writeToMem(mem: String, mems: Seq[mdf.macrolib.Macro]) = {
+    mdf.macrolib.Utils.writeMDFToPath(Some(concat(memPrefix, mem)), mems)
+  }
+
+  // Execute the macro compiler and compare FIRRTL outputs.
+  // TODO: think of a less brittle way to test this?
+  def execute(memFile: String, libFile: String, synflops: Boolean, output: String): Unit = {
+    execute(Some(memFile), Some(libFile), synflops, output)
+  }
+  def execute(memFile: Option[String], libFile: Option[String], synflops: Boolean, output: String): Unit = {
+    var mem_full = concat(memPrefix, memFile)
+    var lib_full = concat(libPrefix, libFile)
+
+    require(memFile.isDefined)
+    val mems: Seq[Macro] = Utils.filterForSRAM(mdf.macrolib.Utils.readMDFFromPath(mem_full)).get map (new Macro(_))
+    val libs: Option[Seq[Macro]] = Utils.filterForSRAM(mdf.macrolib.Utils.readMDFFromPath(lib_full)) match {
+      case Some(x) => Some(x map (new Macro(_)))
+      case None => None
+    }
+    val macros = mems map (_.blackbox)
+    val circuit = Circuit(NoInfo, macros, macros.last.name)
+    val passes = Seq(
+      new MacroCompilerPass(Some(mems), libs),
+      new SynFlopsPass(synflops, libs getOrElse mems),
+      RemoveEmpty)
+    val result = (passes foldLeft circuit)((c, pass) => pass run c)
+    val gold = RemoveEmpty run parse(output)
+    (result.serialize) should be (gold.serialize)
+  }
+
+  // Helper method to deal with String + Option[String]
+  private def concat(a: String, b: String): String = {a + "/" + b}
+  private def concat(a: String, b: Option[String]): Option[String] = {
+    b match {
+      case Some(b2:String) => Some(a + "/" + b2)
+      case _ => None
+    }
+  }
+}
+
+trait HasSRAMGenerator {
+  import mdf.macrolib._
+
+  // Generate a "simple" SRAM (active high/positive edge, 1 read-write port).
+  def generateSRAM(name: String, prefix: String, width: Int, depth: Int, maskGran: Option[Int] = None, extraPorts: Seq[MacroExtraPort] = List()): SRAMMacro = {
+    val realPrefix = prefix + "_"
+    SRAMMacro(
+      macroType=SRAM,
+      name=name,
+      width=width,
+      depth=depth,
+      family="1rw",
+      ports=Seq(MacroPort(
+        address=PolarizedPort(name=realPrefix + "addr", polarity=ActiveHigh),
+        clock=PolarizedPort(name=realPrefix + "clk", polarity=PositiveEdge),
+
+        writeEnable=Some(PolarizedPort(name=realPrefix + "write_en", polarity=ActiveHigh)),
+
+        output=Some(PolarizedPort(name=realPrefix + "dout", polarity=ActiveHigh)),
+        input=Some(PolarizedPort(name=realPrefix + "din", polarity=ActiveHigh)),
+
+        maskPort=maskGran match {
+          case Some(x:Int) => Some(PolarizedPort(name=realPrefix + "mask", polarity=ActiveHigh))
+          case _ => None
+        },
+        maskGran=maskGran,
+
+        width=width, depth=depth // These numbers don't matter here.
+      )),
+      extraPorts=extraPorts
+    )
+  }
+}
+
+//~ class RocketChipTest extends MacroCompilerSpec {
+  //~ val mem = new File(macroDir, "rocketchip.json")
+  //~ val lib = new File(macroDir, "mylib.json")
+  //~ val v = new File(testDir, "rocketchip.macro.v")
+  //~ val output = // TODO: check correctness...
+//~ """
+//~ circuit T_2172_ext :
+  //~ module tag_array_ext :
+    //~ input RW0_clk : Clock
+    //~ input RW0_addr : UInt<6>
+    //~ input RW0_wdata : UInt<80>
+    //~ output RW0_rdata : UInt<80>
+    //~ input RW0_en : UInt<1>
+    //~ input RW0_wmode : UInt<1>
+    //~ input RW0_wmask : UInt<4>
+
+    //~ inst mem_0_0 of SRAM1RW64x32
+    //~ inst mem_0_1 of SRAM1RW64x32
+    //~ inst mem_0_2 of SRAM1RW64x32
+    //~ inst mem_0_3 of SRAM1RW64x32
+    //~ mem_0_0.CE <= RW0_clk
+    //~ mem_0_0.A <= RW0_addr
+    //~ node RW0_rdata_0_0 = bits(mem_0_0.O, 19, 0)
+    //~ mem_0_0.I <= bits(RW0_wdata, 19, 0)
+    //~ mem_0_0.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
+    //~ mem_0_0.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 0, 0)), UInt<1>("h1")))
+    //~ mem_0_0.CEB <= not(and(RW0_en, UInt<1>("h1")))
+    //~ mem_0_1.CE <= RW0_clk
+    //~ mem_0_1.A <= RW0_addr
+    //~ node RW0_rdata_0_1 = bits(mem_0_1.O, 19, 0)
+    //~ mem_0_1.I <= bits(RW0_wdata, 39, 20)
+    //~ mem_0_1.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
+    //~ mem_0_1.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 1, 1)), UInt<1>("h1")))
+    //~ mem_0_1.CEB <= not(and(RW0_en, UInt<1>("h1")))
+    //~ mem_0_2.CE <= RW0_clk
+    //~ mem_0_2.A <= RW0_addr
+    //~ node RW0_rdata_0_2 = bits(mem_0_2.O, 19, 0)
+    //~ mem_0_2.I <= bits(RW0_wdata, 59, 40)
+    //~ mem_0_2.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
+    //~ mem_0_2.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 2, 2)), UInt<1>("h1")))
+    //~ mem_0_2.CEB <= not(and(RW0_en, UInt<1>("h1")))
+    //~ mem_0_3.CE <= RW0_clk
+    //~ mem_0_3.A <= RW0_addr
+    //~ node RW0_rdata_0_3 = bits(mem_0_3.O, 19, 0)
+    //~ mem_0_3.I <= bits(RW0_wdata, 79, 60)
+    //~ mem_0_3.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
+    //~ mem_0_3.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 3, 3)), UInt<1>("h1")))
+    //~ mem_0_3.CEB <= not(and(RW0_en, UInt<1>("h1")))
+    //~ node RW0_rdata_0 = cat(RW0_rdata_0_3, cat(RW0_rdata_0_2, cat(RW0_rdata_0_1, RW0_rdata_0_0)))
+    //~ RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0"))
+
+  //~ extmodule SRAM1RW64x32 :
+    //~ input CE : Clock
+    //~ input A : UInt<6>
+    //~ input I : UInt<32>
+    //~ output O : UInt<32>
+    //~ input CEB : UInt<1>
+    //~ input OEB : UInt<1>
+    //~ input WEB : UInt<1>
+
+    //~ defname = SRAM1RW64x32
+
+
+  //~ module T_1090_ext :
+    //~ input RW0_clk : Clock
+    //~ input RW0_addr : UInt<9>
+    //~ input RW0_wdata : UInt<64>
+    //~ output RW0_rdata : UInt<64>
+    //~ input RW0_en : UInt<1>
+    //~ input RW0_wmode : UInt<1>
+
+    //~ inst mem_0_0 of SRAM1RW512x32
+    //~ inst mem_0_1 of SRAM1RW512x32
+    //~ mem_0_0.CE <= RW0_clk
+    //~ mem_0_0.A <= RW0_addr
+    //~ node RW0_rdata_0_0 = bits(mem_0_0.O, 31, 0)
+    //~ mem_0_0.I <= bits(RW0_wdata, 31, 0)
+    //~ mem_0_0.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
+    //~ mem_0_0.WEB <= not(and(and(RW0_wmode, UInt<1>("h1")), UInt<1>("h1")))
+    //~ mem_0_0.CEB <= not(and(RW0_en, UInt<1>("h1")))
+    //~ mem_0_1.CE <= RW0_clk
+    //~ mem_0_1.A <= RW0_addr
+    //~ node RW0_rdata_0_1 = bits(mem_0_1.O, 31, 0)
+    //~ mem_0_1.I <= bits(RW0_wdata, 63, 32)
+    //~ mem_0_1.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
+    //~ mem_0_1.WEB <= not(and(and(RW0_wmode, UInt<1>("h1")), UInt<1>("h1")))
+    //~ mem_0_1.CEB <= not(and(RW0_en, UInt<1>("h1")))
+    //~ node RW0_rdata_0 = cat(RW0_rdata_0_1, RW0_rdata_0_0)
+    //~ RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0"))
+
+  //~ module T_406_ext :
+    //~ input RW0_clk : Clock
+    //~ input RW0_addr : UInt<9>
+    //~ input RW0_wdata : UInt<64>
+    //~ output RW0_rdata : UInt<64>
+    //~ input RW0_en : UInt<1>
+    //~ input RW0_wmode : UInt<1>
+    //~ input RW0_wmask : UInt<8>
+
+    //~ inst mem_0_0 of SRAM1RW512x32
+    //~ inst mem_0_1 of SRAM1RW512x32
+    //~ inst mem_0_2 of SRAM1RW512x32
+    //~ inst mem_0_3 of SRAM1RW512x32
+    //~ inst mem_0_4 of SRAM1RW512x32
+    //~ inst mem_0_5 of SRAM1RW512x32
+    //~ inst mem_0_6 of SRAM1RW512x32
+    //~ inst mem_0_7 of SRAM1RW512x32
+    //~ mem_0_0.CE <= RW0_clk
+    //~ mem_0_0.A <= RW0_addr
+    //~ node RW0_rdata_0_0 = bits(mem_0_0.O, 7, 0)
+    //~ mem_0_0.I <= bits(RW0_wdata, 7, 0)
+    //~ mem_0_0.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
+    //~ mem_0_0.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 0, 0)), UInt<1>("h1")))
+    //~ mem_0_0.CEB <= not(and(RW0_en, UInt<1>("h1")))
+    //~ mem_0_1.CE <= RW0_clk
+    //~ mem_0_1.A <= RW0_addr
+    //~ node RW0_rdata_0_1 = bits(mem_0_1.O, 7, 0)
+    //~ mem_0_1.I <= bits(RW0_wdata, 15, 8)
+    //~ mem_0_1.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
+    //~ mem_0_1.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 1, 1)), UInt<1>("h1")))
+    //~ mem_0_1.CEB <= not(and(RW0_en, UInt<1>("h1")))
+    //~ mem_0_2.CE <= RW0_clk
+    //~ mem_0_2.A <= RW0_addr
+    //~ node RW0_rdata_0_2 = bits(mem_0_2.O, 7, 0)
+    //~ mem_0_2.I <= bits(RW0_wdata, 23, 16)
+    //~ mem_0_2.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
+    //~ mem_0_2.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 2, 2)), UInt<1>("h1")))
+    //~ mem_0_2.CEB <= not(and(RW0_en, UInt<1>("h1")))
+    //~ mem_0_3.CE <= RW0_clk
+    //~ mem_0_3.A <= RW0_addr
+    //~ node RW0_rdata_0_3 = bits(mem_0_3.O, 7, 0)
+    //~ mem_0_3.I <= bits(RW0_wdata, 31, 24)
+    //~ mem_0_3.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
+    //~ mem_0_3.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 3, 3)), UInt<1>("h1")))
+    //~ mem_0_3.CEB <= not(and(RW0_en, UInt<1>("h1")))
+    //~ mem_0_4.CE <= RW0_clk
+    //~ mem_0_4.A <= RW0_addr
+    //~ node RW0_rdata_0_4 = bits(mem_0_4.O, 7, 0)
+    //~ mem_0_4.I <= bits(RW0_wdata, 39, 32)
+    //~ mem_0_4.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
+    //~ mem_0_4.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 4, 4)), UInt<1>("h1")))
+    //~ mem_0_4.CEB <= not(and(RW0_en, UInt<1>("h1")))
+    //~ mem_0_5.CE <= RW0_clk
+    //~ mem_0_5.A <= RW0_addr
+    //~ node RW0_rdata_0_5 = bits(mem_0_5.O, 7, 0)
+    //~ mem_0_5.I <= bits(RW0_wdata, 47, 40)
+    //~ mem_0_5.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
+    //~ mem_0_5.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 5, 5)), UInt<1>("h1")))
+    //~ mem_0_5.CEB <= not(and(RW0_en, UInt<1>("h1")))
+    //~ mem_0_6.CE <= RW0_clk
+    //~ mem_0_6.A <= RW0_addr
+    //~ node RW0_rdata_0_6 = bits(mem_0_6.O, 7, 0)
+    //~ mem_0_6.I <= bits(RW0_wdata, 55, 48)
+    //~ mem_0_6.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
+    //~ mem_0_6.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 6, 6)), UInt<1>("h1")))
+    //~ mem_0_6.CEB <= not(and(RW0_en, UInt<1>("h1")))
+    //~ mem_0_7.CE <= RW0_clk
+    //~ mem_0_7.A <= RW0_addr
+    //~ node RW0_rdata_0_7 = bits(mem_0_7.O, 7, 0)
+    //~ mem_0_7.I <= bits(RW0_wdata, 63, 56)
+    //~ mem_0_7.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
+    //~ mem_0_7.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 7, 7)), UInt<1>("h1")))
+    //~ mem_0_7.CEB <= not(and(RW0_en, UInt<1>("h1")))
+    //~ node RW0_rdata_0 = cat(RW0_rdata_0_7, cat(RW0_rdata_0_6, cat(RW0_rdata_0_5, cat(RW0_rdata_0_4, cat(RW0_rdata_0_3, cat(RW0_rdata_0_2, cat(RW0_rdata_0_1, RW0_rdata_0_0)))))))
+    //~ RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0"))
+
+  //~ extmodule SRAM1RW512x32 :
+    //~ input CE : Clock
+    //~ input A : UInt<9>
+    //~ input I : UInt<32>
+    //~ output O : UInt<32>
+    //~ input CEB : UInt<1>
+    //~ input OEB : UInt<1>
+    //~ input WEB : UInt<1>
+
+    //~ defname = SRAM1RW512x32
+
+
+  //~ module T_2172_ext :
+    //~ input W0_clk : Clock
+    //~ input W0_addr : UInt<6>
+    //~ input W0_data : UInt<88>
+    //~ input W0_en : UInt<1>
+    //~ input W0_mask : UInt<4>
+    //~ input R0_clk : Clock
+    //~ input R0_addr : UInt<6>
+    //~ output R0_data : UInt<88>
+    //~ input R0_en : UInt<1>
+
+    //~ inst mem_0_0 of SRAM2RW64x32
+    //~ inst mem_0_1 of SRAM2RW64x32
+    //~ inst mem_0_2 of SRAM2RW64x32
+    //~ inst mem_0_3 of SRAM2RW64x32
+    //~ mem_0_0.CE1 <= W0_clk
+    //~ mem_0_0.A1 <= W0_addr
+    //~ mem_0_0.I1 <= bits(W0_data, 21, 0)
+    //~ mem_0_0.OEB1 <= not(and(not(UInt<1>("h1")), UInt<1>("h1")))
+    //~ mem_0_0.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 0, 0)), UInt<1>("h1")))
+    //~ mem_0_0.CEB1 <= not(and(W0_en, UInt<1>("h1")))
+    //~ mem_0_1.CE1 <= W0_clk
+    //~ mem_0_1.A1 <= W0_addr
+    //~ mem_0_1.I1 <= bits(W0_data, 43, 22)
+    //~ mem_0_1.OEB1 <= not(and(not(UInt<1>("h1")), UInt<1>("h1")))
+    //~ mem_0_1.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 1, 1)), UInt<1>("h1")))
+    //~ mem_0_1.CEB1 <= not(and(W0_en, UInt<1>("h1")))
+    //~ mem_0_2.CE1 <= W0_clk
+    //~ mem_0_2.A1 <= W0_addr
+    //~ mem_0_2.I1 <= bits(W0_data, 65, 44)
+    //~ mem_0_2.OEB1 <= not(and(not(UInt<1>("h1")), UInt<1>("h1")))
+    //~ mem_0_2.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 2, 2)), UInt<1>("h1")))
+    //~ mem_0_2.CEB1 <= not(and(W0_en, UInt<1>("h1")))
+    //~ mem_0_3.CE1 <= W0_clk
+    //~ mem_0_3.A1 <= W0_addr
+    //~ mem_0_3.I1 <= bits(W0_data, 87, 66)
+    //~ mem_0_3.OEB1 <= not(and(not(UInt<1>("h1")), UInt<1>("h1")))
+    //~ mem_0_3.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 3, 3)), UInt<1>("h1")))
+    //~ mem_0_3.CEB1 <= not(and(W0_en, UInt<1>("h1")))
+    //~ mem_0_0.CE2 <= R0_clk
+    //~ mem_0_0.A2 <= R0_addr
+    //~ node R0_data_0_0 = bits(mem_0_0.O2, 21, 0)
+    //~ mem_0_0.OEB2 <= not(and(not(UInt<1>("h0")), UInt<1>("h1")))
+    //~ mem_0_0.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), UInt<1>("h1")))
+    //~ mem_0_0.CEB2 <= not(and(R0_en, UInt<1>("h1")))
+    //~ mem_0_1.CE2 <= R0_clk
+    //~ mem_0_1.A2 <= R0_addr
+    //~ node R0_data_0_1 = bits(mem_0_1.O2, 21, 0)
+    //~ mem_0_1.OEB2 <= not(and(not(UInt<1>("h0")), UInt<1>("h1")))
+    //~ mem_0_1.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), UInt<1>("h1")))
+    //~ mem_0_1.CEB2 <= not(and(R0_en, UInt<1>("h1")))
+    //~ mem_0_2.CE2 <= R0_clk
+    //~ mem_0_2.A2 <= R0_addr
+    //~ node R0_data_0_2 = bits(mem_0_2.O2, 21, 0)
+    //~ mem_0_2.OEB2 <= not(and(not(UInt<1>("h0")), UInt<1>("h1")))
+    //~ mem_0_2.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), UInt<1>("h1")))
+    //~ mem_0_2.CEB2 <= not(and(R0_en, UInt<1>("h1")))
+    //~ mem_0_3.CE2 <= R0_clk
+    //~ mem_0_3.A2 <= R0_addr
+    //~ node R0_data_0_3 = bits(mem_0_3.O2, 21, 0)
+    //~ mem_0_3.OEB2 <= not(and(not(UInt<1>("h0")), UInt<1>("h1")))
+    //~ mem_0_3.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), UInt<1>("h1")))
+    //~ mem_0_3.CEB2 <= not(and(R0_en, UInt<1>("h1")))
+    //~ node R0_data_0 = cat(R0_data_0_3, cat(R0_data_0_2, cat(R0_data_0_1, R0_data_0_0)))
+    //~ R0_data <= mux(UInt<1>("h1"), R0_data_0, UInt<1>("h0"))
+
+  //~ extmodule SRAM2RW64x32 :
+    //~ input CE1 : Clock
+    //~ input A1 : UInt<6>
+    //~ input I1 : UInt<32>
+    //~ output O1 : UInt<32>
+    //~ input CEB1 : UInt<1>
+    //~ input OEB1 : UInt<1>
+    //~ input WEB1 : UInt<1>
+    //~ input CE2 : Clock
+    //~ input A2 : UInt<6>
+    //~ input I2 : UInt<32>
+    //~ output O2 : UInt<32>
+    //~ input CEB2 : UInt<1>
+    //~ input OEB2 : UInt<1>
+    //~ input WEB2 : UInt<1>
+
+    //~ defname = SRAM2RW64x32
+//~ """
+  //~ compile(mem, Some(lib), v, false)
+//~ }
--- a/macros/src/test/scala/SimpleSplitDepth.scala
+++ b/macros/src/test/scala/SimpleSplitDepth.scala
@@ -0,0 +1,451 @@
+package barstools.macros
+
+import firrtl.Utils.ceilLog2
+import mdf.macrolib._
+
+// Test the depth splitting aspect of the memory compiler.
+// This file is for simple tests: one read-write port, powers of two sizes, etc.
+// For example, implementing a 4096x32 memory using four 1024x32 memories.
+
+trait HasSimpleDepthTestGenerator {
+  this: MacroCompilerSpec with HasSRAMGenerator =>
+    // Override these with "override lazy val".
+    // Why lazy? These are used in the constructor here so overriding non-lazily
+    // would be too late.
+    def width: Int
+    def mem_depth: Int
+    def lib_depth: Int
+    def mem_maskGran: Option[Int] = None
+    def lib_maskGran: Option[Int] = None
+    def extraPorts: Seq[mdf.macrolib.MacroExtraPort] = List()
+
+    require (mem_depth >= lib_depth)
+
+    override val memPrefix = testDir
+    override val libPrefix = testDir
+
+    // Convenience variables to check if a mask exists.
+    val memHasMask = mem_maskGran != None
+    val libHasMask = lib_maskGran != None
+    // We need to figure out how many mask bits there are in the mem.
+    val memMaskBits = if (memHasMask) width / mem_maskGran.get else 0
+    val libMaskBits = if (libHasMask) width / lib_maskGran.get else 0
+    // Generate "mrw" vs "rw" tags.
+    val memTag = (if (memHasMask) "m" else "") + "rw"
+    val libTag = (if (libHasMask) "m" else "") + "rw"
+
+    val mem = s"mem-${mem_depth}x${width}-${memTag}.json"
+    val lib = s"lib-${lib_depth}x${width}-${libTag}.json"
+    val v = s"split_depth_${mem_depth}x${width}_${memTag}.v"
+
+    val mem_name = "target_memory"
+    val mem_addr_width = ceilLog2(mem_depth)
+
+    val lib_name = "awesome_lib_mem"
+    val lib_addr_width = ceilLog2(lib_depth)
+
+    writeToLib(lib, Seq(generateSRAM(lib_name, "lib", width, lib_depth, lib_maskGran, extraPorts)))
+    writeToMem(mem, Seq(generateSRAM(mem_name, "outer", width, mem_depth, mem_maskGran)))
+
+    // Number of lib instances needed to hold the mem.
+    // Round up (e.g. 1.5 instances = effectively 2 instances)
+    val expectedInstances = math.ceil(mem_depth.toFloat / lib_depth).toInt
+    val selectBits = mem_addr_width - lib_addr_width
+
+    val headerMask = if (memHasMask) s"input outer_mask : UInt<${memMaskBits}>" else ""
+    val header = s"""
+circuit $mem_name :
+  module $mem_name :
+    input outer_clk : Clock
+    input outer_addr : UInt<$mem_addr_width>
+    input outer_din : UInt<$width>
+    output outer_dout : UInt<$width>
+    input outer_write_en : UInt<1>
+    ${headerMask}
+"""
+
+    val footerMask = if (libHasMask) s"input lib_mask : UInt<${libMaskBits}>" else ""
+    val footer = s"""
+  extmodule $lib_name :
+    input lib_clk : Clock
+    input lib_addr : UInt<$lib_addr_width>
+    input lib_din : UInt<$width>
+    output lib_dout : UInt<$width>
+    input lib_write_en : UInt<1>
+    ${footerMask}
+
+    defname = $lib_name
+"""
+
+    var output = header
+
+    if (selectBits > 0) {
+      output +=
+s"""
+    node outer_addr_sel = bits(outer_addr, ${mem_addr_width - 1}, $lib_addr_width)
+"""
+    }
+
+    for (i <- 0 to expectedInstances - 1) {
+      // We only support simple masks for now (either libMask == memMask or libMask == 1)
+      val maskStatement = if (libHasMask) {
+        if (lib_maskGran.get == mem_maskGran.get) {
+          s"""mem_${i}_0.lib_mask <= bits(outer_mask, 0, 0)"""
+        } else if (lib_maskGran.get == 1) {
+          // Construct a mask string.
+          // Each bit gets the # of bits specified in maskGran.
+          // Specify in descending order (MSB first)
+
+          // This builds an array like m[1], m[1], m[0], m[0]
+          val maskBitsArr: Seq[String] = ((memMaskBits - 1 to 0 by -1) flatMap (maskBit => {
+            ((0 to mem_maskGran.get - 1) map (_ => s"bits(outer_mask, ${maskBit}, ${maskBit})"))
+          }))
+          // Now build it into a recursive string like
+          // cat(m[1], cat(m[1], cat(m[0], m[0])))
+          val maskBitsStr: String = maskBitsArr.reverse.tail.foldLeft(maskBitsArr.reverse.head)((prev: String, next: String) => s"cat(${next}, ${prev})")
+          s"""mem_${i}_0.lib_mask <= ${maskBitsStr}"""
+        } else "" // TODO: implement when non-bitmasked memories are supported
+      } else "" // No mask
+
+      val enableIdentifier = if (selectBits > 0) s"""eq(outer_addr_sel, UInt<${selectBits}>("h${i.toHexString}"))""" else "UInt<1>(\"h1\")"
+      output +=
+s"""
+    inst mem_${i}_0 of awesome_lib_mem
+    mem_${i}_0.lib_clk <= outer_clk
+    mem_${i}_0.lib_addr <= outer_addr
+    node outer_dout_${i}_0 = bits(mem_${i}_0.lib_dout, ${width - 1}, 0)
+    mem_${i}_0.lib_din <= bits(outer_din, ${width - 1}, 0)
+    ${maskStatement}
+    mem_${i}_0.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), ${enableIdentifier})
+    node outer_dout_${i} = outer_dout_${i}_0
+"""
+    }
+    def generate_outer_dout_tree(i:Int, expectedInstances: Int): String = {
+      if (i > expectedInstances - 1) {
+        "UInt<1>(\"h0\")"
+      } else {
+        "mux(eq(outer_addr_sel, UInt<%d>(\"h%s\")), outer_dout_%d, %s)".format(
+          selectBits, i.toHexString, i, generate_outer_dout_tree(i + 1, expectedInstances)
+        )
+      }
+    }
+    output += "    outer_dout <= "
+    if (selectBits > 0) {
+      output += generate_outer_dout_tree(0, expectedInstances)
+    } else {
+      output += """mux(UInt<1>("h1"), outer_dout_0, UInt<1>("h0"))"""
+    }
+
+    output += footer
+}
+
+// Try different widths
+class SplitDepth4096x32_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
+  override lazy val width = 32
+  override lazy val mem_depth = 4096
+  override lazy val lib_depth = 1024
+
+  compile(mem, lib, v, false)
+  execute(mem, lib, false, output)
+}
+
+class SplitDepth4096x16_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
+  override lazy val width = 16
+  override lazy val mem_depth = 4096
+  override lazy val lib_depth = 1024
+
+  compile(mem, lib, v, false)
+  execute(mem, lib, false, output)
+}
+
+class SplitDepth32768x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
+  override lazy val width = 8
+  override lazy val mem_depth = 32768
+  override lazy val lib_depth = 1024
+
+  compile(mem, lib, v, false)
+  execute(mem, lib, false, output)
+}
+
+class SplitDepth4096x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
+  override lazy val width = 8
+  override lazy val mem_depth = 4096
+  override lazy val lib_depth = 1024
+
+  compile(mem, lib, v, false)
+  execute(mem, lib, false, output)
+}
+
+class SplitDepth2048x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
+  override lazy val width = 8
+  override lazy val mem_depth = 2048
+  override lazy val lib_depth = 1024
+
+  compile(mem, lib, v, false)
+  execute(mem, lib, false, output)
+}
+
+class SplitDepth1024x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
+  override lazy val width = 8
+  override lazy val mem_depth = 1024
+  override lazy val lib_depth = 1024
+
+  compile(mem, lib, v, false)
+  execute(mem, lib, false, output)
+}
+
+// Non power of two
+class SplitDepth2000x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
+  override lazy val width = 8
+  override lazy val mem_depth = 2000
+  override lazy val lib_depth = 1024
+
+  compile(mem, lib, v, false)
+  execute(mem, lib, false, output)
+}
+
+class SplitDepth2049x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
+  override lazy val width = 8
+  override lazy val mem_depth = 2049
+  override lazy val lib_depth = 1024
+
+  compile(mem, lib, v, false)
+  execute(mem, lib, false, output)
+}
+
+// Masked RAMs
+
+// Test for mem mask == lib mask (i.e. mask is a write enable bit)
+class SplitDepth2048x32_mrw_lib32 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
+  override lazy val width = 32
+  override lazy val mem_depth = 2048
+  override lazy val lib_depth = 1024
+  override lazy val mem_maskGran = Some(32)
+  override lazy val lib_maskGran = Some(32)
+
+  compile(mem, lib, v, false)
+  execute(mem, lib, false, output)
+}
+
+class SplitDepth2048x8_mrw_lib8 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
+  override lazy val width = 8
+  override lazy val mem_depth = 2048
+  override lazy val lib_depth = 1024
+  override lazy val mem_maskGran = Some(8)
+  override lazy val lib_maskGran = Some(8)
+
+  compile(mem, lib, v, false)
+  execute(mem, lib, false, output)
+}
+
+// Non-bit level mask
+class SplitDepth2048x64_mrw_mem32_lib8 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
+  override lazy val width = 64
+  override lazy val mem_depth = 2048
+  override lazy val lib_depth = 1024
+  override lazy val mem_maskGran = Some(32)
+  override lazy val lib_maskGran = Some(8)
+
+  it should "be enabled when non-bitmasked memories are supported" is (pending)
+  //compile(mem, lib, v, false)
+  //execute(mem, lib, false, output)
+}
+
+// Bit level mask
+class SplitDepth2048x32_mrw_mem16_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
+  override lazy val width = 32
+  override lazy val mem_depth = 2048
+  override lazy val lib_depth = 1024
+  override lazy val mem_maskGran = Some(16)
+  override lazy val lib_maskGran = Some(1)
+
+  compile(mem, lib, v, false)
+  execute(mem, lib, false, output)
+}
+
+class SplitDepth2048x32_mrw_mem8_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
+  override lazy val width = 32
+  override lazy val mem_depth = 2048
+  override lazy val lib_depth = 1024
+  override lazy val mem_maskGran = Some(8)
+  override lazy val lib_maskGran = Some(1)
+
+  compile(mem, lib, v, false)
+  execute(mem, lib, false, output)
+}
+
+class SplitDepth2048x32_mrw_mem4_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
+  override lazy val width = 32
+  override lazy val mem_depth = 2048
+  override lazy val lib_depth = 1024
+  override lazy val mem_maskGran = Some(4)
+  override lazy val lib_maskGran = Some(1)
+
+  compile(mem, lib, v, false)
+  execute(mem, lib, false, output)
+}
+
+class SplitDepth2048x32_mrw_mem2_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
+  override lazy val width = 32
+  override lazy val mem_depth = 2048
+  override lazy val lib_depth = 1024
+  override lazy val mem_maskGran = Some(2)
+  override lazy val lib_maskGran = Some(1)
+
+  compile(mem, lib, v, false)
+  execute(mem, lib, false, output)
+}
+
+// Non-powers of 2 mask sizes
+class SplitDepth2048x32_mrw_mem3_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
+  override lazy val width = 32
+  override lazy val mem_depth = 2048
+  override lazy val lib_depth = 1024
+  override lazy val mem_maskGran = Some(3)
+  override lazy val lib_maskGran = Some(1)
+
+  it should "be enabled when non-power of two masks are supported" is (pending)
+  //compile(mem, lib, v, false)
+  //execute(mem, lib, false, output)
+}
+
+class SplitDepth2048x32_mrw_mem7_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
+  override lazy val width = 32
+  override lazy val mem_depth = 2048
+  override lazy val lib_depth = 1024
+  override lazy val mem_maskGran = Some(7)
+  override lazy val lib_maskGran = Some(1)
+
+  it should "be enabled when non-power of two masks are supported" is (pending)
+  //compile(mem, lib, v, false)
+  //execute(mem, lib, false, output)
+}
+
+class SplitDepth2048x32_mrw_mem9_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
+  override lazy val width = 32
+  override lazy val mem_depth = 2048
+  override lazy val lib_depth = 1024
+  override lazy val mem_maskGran = Some(9)
+  override lazy val lib_maskGran = Some(1)
+
+  it should "be enabled when non-power of two masks are supported" is (pending)
+  //compile(mem, lib, v, false)
+  //execute(mem, lib, false, output)
+}
+
+//~ class SplitDepth2048x8_r_mw extends MacroCompilerSpec {
+  //~ val mem = new File(macroDir, "mem-2048x8-r-mw.json")
+  //~ val lib = new File(macroDir, "lib-1024x8-r-mw.json")
+  //~ val v = new File(testDir, "split_depth_2048x8_r_mw.v")
+  //~ val output =
+//~ """
+//~ circuit name_of_sram_module :
+  //~ module name_of_sram_module :
+    //~ input clock : Clock
+    //~ input W0A : UInt<11>
+    //~ input W0I : UInt<8>
+    //~ input W0E : UInt<1>
+    //~ input W0M : UInt<1>
+    //~ input clock : Clock
+    //~ input R0A : UInt<11>
+    //~ output R0O : UInt<8>
+
+    //~ node W0A_sel = bits(W0A, 10, 10)
+    //~ node R0A_sel = bits(R0A, 10, 10)
+    //~ inst mem_0_0 of vendor_sram
+    //~ mem_0_0.clock <= clock
+    //~ mem_0_0.W0A <= W0A
+    //~ mem_0_0.W0I <= bits(W0I, 7, 0)
+    //~ mem_0_0.W0M <= bits(W0M, 0, 0)
+    //~ mem_0_0.W0W <= and(UInt<1>("h1"), eq(W0A_sel, UInt<1>("h0")))
+    //~ mem_0_0.W0E <= and(W0E, eq(W0A_sel, UInt<1>("h0")))
+    //~ mem_0_0.clock <= clock
+    //~ mem_0_0.R0A <= R0A
+    //~ node R0O_0_0 = bits(mem_0_0.R0O, 7, 0)
+    //~ node R0O_0 = R0O_0_0
+    //~ inst mem_1_0 of vendor_sram
+    //~ mem_1_0.clock <= clock
+    //~ mem_1_0.W0A <= W0A
+    //~ mem_1_0.W0I <= bits(W0I, 7, 0)
+    //~ mem_1_0.W0M <= bits(W0M, 0, 0)
+    //~ mem_1_0.W0W <= and(UInt<1>("h1"), eq(W0A_sel, UInt<1>("h1")))
+    //~ mem_1_0.W0E <= and(W0E, eq(W0A_sel, UInt<1>("h1")))
+    //~ mem_1_0.clock <= clock
+    //~ mem_1_0.R0A <= R0A
+    //~ node R0O_1_0 = bits(mem_1_0.R0O, 7, 0)
+    //~ node R0O_1 = R0O_1_0
+    //~ R0O <= mux(eq(R0A_sel, UInt<1>("h0")), R0O_0, mux(eq(R0A_sel, UInt<1>("h1")), R0O_1, UInt<1>("h0")))
+
+  //~ extmodule vendor_sram :
+    //~ input clock : Clock
+    //~ input R0A : UInt<10>
+    //~ output R0O : UInt<8>
+    //~ input clock : Clock
+    //~ input W0A : UInt<10>
+    //~ input W0I : UInt<8>
+    //~ input W0E : UInt<1>
+    //~ input W0W : UInt<1>
+    //~ input W0M : UInt<1>
+
+    //~ defname = vendor_sram
+//~ """
+  //~ compile(mem, lib, v, false)
+  //~ execute(mem, lib, false, output)
+//~ }
+
+// Try an extra port
+class SplitDepth2048x8_extraPort extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
+  import mdf.macrolib._
+
+  override lazy val width = 8
+  override lazy val mem_depth = 2048
+  override lazy val lib_depth = 1024
+  override lazy val extraPorts = List(
+    MacroExtraPort(name="extra_port", width=8, portType=Constant, value=0xff)
+  )
+
+  val outputCustom =
+"""
+circuit target_memory :
+  module target_memory :
+    input outer_clk : Clock
+    input outer_addr : UInt<11>
+    input outer_din : UInt<8>
+    output outer_dout : UInt<8>
+    input outer_write_en : UInt<1>
+
+    node outer_addr_sel = bits(outer_addr, 10, 10)
+
+    inst mem_0_0 of awesome_lib_mem
+    mem_0_0.extra_port <= UInt<8>("hff")
+    mem_0_0.lib_clk <= outer_clk
+    mem_0_0.lib_addr <= outer_addr
+    node outer_dout_0_0 = bits(mem_0_0.lib_dout, 7, 0)
+    mem_0_0.lib_din <= bits(outer_din, 7, 0)
+
+    mem_0_0.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), eq(outer_addr_sel, UInt<1>("h0")))
+    node outer_dout_0 = outer_dout_0_0
+
+    inst mem_1_0 of awesome_lib_mem
+    mem_1_0.extra_port <= UInt<8>("hff")
+    mem_1_0.lib_clk <= outer_clk
+    mem_1_0.lib_addr <= outer_addr
+    node outer_dout_1_0 = bits(mem_1_0.lib_dout, 7, 0)
+    mem_1_0.lib_din <= bits(outer_din, 7, 0)
+
+    mem_1_0.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), eq(outer_addr_sel, UInt<1>("h1")))
+    node outer_dout_1 = outer_dout_1_0
+    outer_dout <= mux(eq(outer_addr_sel, UInt<1>("h0")), outer_dout_0, mux(eq(outer_addr_sel, UInt<1>("h1")), outer_dout_1, UInt<1>("h0")))
+  extmodule awesome_lib_mem :
+    input lib_clk : Clock
+    input lib_addr : UInt<10>
+    input lib_din : UInt<8>
+    output lib_dout : UInt<8>
+    input lib_write_en : UInt<1>
+    input extra_port : UInt<8>
+
+    defname = awesome_lib_mem
+  """
+  compile(mem, lib, v, false)
+  execute(mem, lib, false, outputCustom)
+}
--- a/macros/src/test/scala/SimpleSplitWidth.scala
+++ b/macros/src/test/scala/SimpleSplitWidth.scala
@@ -0,0 +1,468 @@
+//~ package barstools.macros
+
+//~ import java.io.File
+
+//~ class SplitWidth2048x16_mrw extends MacroCompilerSpec {
+  //~ val mem = new File(macroDir, "mem-2048x16-mrw.json")
+  //~ val lib = new File(macroDir, "lib-2048x8-mrw.json")
+  //~ val v = new File(testDir, "split_width_2048x16_mrw.v")
+  //~ val output =
+//~ """
+//~ circuit name_of_sram_module :
+  //~ module name_of_sram_module :
+    //~ input clock : Clock
+    //~ input RW0A : UInt<11>
+    //~ input RW0I : UInt<16>
+    //~ output RW0O : UInt<16>
+    //~ input RW0E : UInt<1>
+    //~ input RW0W : UInt<1>
+    //~ input RW0M : UInt<2>
+
+    //~ inst mem_0_0 of vendor_sram
+    //~ inst mem_0_1 of vendor_sram
+    //~ mem_0_0.clock <= clock
+    //~ mem_0_0.RW0A <= RW0A
+    //~ node RW0O_0_0 = bits(mem_0_0.RW0O, 7, 0)
+    //~ mem_0_0.RW0I <= bits(RW0I, 7, 0)
+    //~ mem_0_0.RW0M <= bits(RW0M, 0, 0)
+    //~ mem_0_0.RW0W <= and(RW0W, UInt<1>("h1"))
+    //~ mem_0_0.RW0E <= and(RW0E, UInt<1>("h1"))
+    //~ mem_0_1.clock <= clock
+    //~ mem_0_1.RW0A <= RW0A
+    //~ node RW0O_0_1 = bits(mem_0_1.RW0O, 7, 0)
+    //~ mem_0_1.RW0I <= bits(RW0I, 15, 8)
+    //~ mem_0_1.RW0M <= bits(RW0M, 1, 1)
+    //~ mem_0_1.RW0W <= and(RW0W, UInt<1>("h1"))
+    //~ mem_0_1.RW0E <= and(RW0E, UInt<1>("h1"))
+    //~ node RW0O_0 = cat(RW0O_0_1, RW0O_0_0)
+    //~ RW0O <= mux(UInt<1>("h1"), RW0O_0, UInt<1>("h0"))
+
+  //~ extmodule vendor_sram :
+    //~ input clock : Clock
+    //~ input RW0A : UInt<11>
+    //~ input RW0I : UInt<8>
+    //~ output RW0O : UInt<8>
+    //~ input RW0E : UInt<1>
+    //~ input RW0W : UInt<1>
+    //~ input RW0M : UInt<1>
+
+    //~ defname = vendor_sram
+//~ """
+  //~ compile(mem, Some(lib), v, false)
+  //~ execute(Some(mem), Some(lib), false, output)
+//~ }
+
+//~ class SplitWidth2048x16_mrw_Uneven extends MacroCompilerSpec {
+  //~ val mem = new File(macroDir, "mem-2048x16-mrw.json")
+  //~ val lib = new File(macroDir, "lib-2048x10-rw.json")
+  //~ val v = new File(testDir, "split_width_2048x16_mrw_uneven.v")
+  //~ val output =
+//~ """
+//~ circuit name_of_sram_module :
+  //~ module name_of_sram_module :
+    //~ input clock : Clock
+    //~ input RW0A : UInt<11>
+    //~ input RW0I : UInt<16>
+    //~ output RW0O : UInt<16>
+    //~ input RW0E : UInt<1>
+    //~ input RW0W : UInt<1>
+    //~ input RW0M : UInt<2>
+
+    //~ inst mem_0_0 of vendor_sram
+    //~ inst mem_0_1 of vendor_sram
+    //~ mem_0_0.clock <= clock
+    //~ mem_0_0.RW0A <= RW0A
+    //~ node RW0O_0_0 = bits(mem_0_0.RW0O, 7, 0)
+    //~ mem_0_0.RW0I <= bits(RW0I, 7, 0)
+    //~ mem_0_0.RW0W <= and(and(RW0W, bits(RW0M, 0, 0)), UInt<1>("h1"))
+    //~ mem_0_0.RW0E <= and(RW0E, UInt<1>("h1"))
+    //~ mem_0_1.clock <= clock
+    //~ mem_0_1.RW0A <= RW0A
+    //~ node RW0O_0_1 = bits(mem_0_1.RW0O, 7, 0)
+    //~ mem_0_1.RW0I <= bits(RW0I, 15, 8)
+    //~ mem_0_1.RW0W <= and(and(RW0W, bits(RW0M, 1, 1)), UInt<1>("h1"))
+    //~ mem_0_1.RW0E <= and(RW0E, UInt<1>("h1"))
+    //~ node RW0O_0 = cat(RW0O_0_1, RW0O_0_0)
+    //~ RW0O <= mux(UInt<1>("h1"), RW0O_0, UInt<1>("h0"))
+
+  //~ extmodule vendor_sram :
+    //~ input clock : Clock
+    //~ input RW0A : UInt<11>
+    //~ input RW0I : UInt<10>
+    //~ output RW0O : UInt<10>
+    //~ input RW0E : UInt<1>
+    //~ input RW0W : UInt<1>
+
+    //~ defname = vendor_sram
+//~ """
+  //~ compile(mem, Some(lib), v, false)
+  //~ execute(Some(mem), Some(lib), false, output)
+//~ }
+
+//~ class SplitWidth2048x16_mrw_VeryUneven extends MacroCompilerSpec {
+  //~ val mem = new File(macroDir, "mem-2048x16-mrw-2.json")
+  //~ val lib = new File(macroDir, "lib-2048x10-rw.json")
+  //~ val v = new File(testDir, "split_width_2048x16_mrw_very_uneven.v")
+  //~ val output =
+//~ """
+//~ circuit name_of_sram_module :
+  //~ module name_of_sram_module :
+    //~ input clock : Clock
+    //~ input RW0A : UInt<11>
+    //~ input RW0I : UInt<16>
+    //~ output RW0O : UInt<16>
+    //~ input RW0E : UInt<1>
+    //~ input RW0W : UInt<1>
+    //~ input RW0M : UInt<8>
+
+    //~ inst mem_0_0 of vendor_sram
+    //~ inst mem_0_1 of vendor_sram
+    //~ inst mem_0_2 of vendor_sram
+    //~ inst mem_0_3 of vendor_sram
+    //~ inst mem_0_4 of vendor_sram
+    //~ inst mem_0_5 of vendor_sram
+    //~ inst mem_0_6 of vendor_sram
+    //~ inst mem_0_7 of vendor_sram
+    //~ mem_0_0.clock <= clock
+    //~ mem_0_0.RW0A <= RW0A
+    //~ node RW0O_0_0 = bits(mem_0_0.RW0O, 1, 0)
+    //~ mem_0_0.RW0I <= bits(RW0I, 1, 0)
+    //~ mem_0_0.RW0W <= and(and(RW0W, bits(RW0M, 0, 0)), UInt<1>("h1"))
+    //~ mem_0_0.RW0E <= and(RW0E, UInt<1>("h1"))
+    //~ mem_0_1.clock <= clock
+    //~ mem_0_1.RW0A <= RW0A
+    //~ node RW0O_0_1 = bits(mem_0_1.RW0O, 1, 0)
+    //~ mem_0_1.RW0I <= bits(RW0I, 3, 2)
+    //~ mem_0_1.RW0W <= and(and(RW0W, bits(RW0M, 1, 1)), UInt<1>("h1"))
+    //~ mem_0_1.RW0E <= and(RW0E, UInt<1>("h1"))
+    //~ mem_0_2.clock <= clock
+    //~ mem_0_2.RW0A <= RW0A
+    //~ node RW0O_0_2 = bits(mem_0_2.RW0O, 1, 0)
+    //~ mem_0_2.RW0I <= bits(RW0I, 5, 4)
+    //~ mem_0_2.RW0W <= and(and(RW0W, bits(RW0M, 2, 2)), UInt<1>("h1"))
+    //~ mem_0_2.RW0E <= and(RW0E, UInt<1>("h1"))
+    //~ mem_0_3.clock <= clock
+    //~ mem_0_3.RW0A <= RW0A
+    //~ node RW0O_0_3 = bits(mem_0_3.RW0O, 1, 0)
+    //~ mem_0_3.RW0I <= bits(RW0I, 7, 6)
+    //~ mem_0_3.RW0W <= and(and(RW0W, bits(RW0M, 3, 3)), UInt<1>("h1"))
+    //~ mem_0_3.RW0E <= and(RW0E, UInt<1>("h1"))
+    //~ mem_0_4.clock <= clock
+    //~ mem_0_4.RW0A <= RW0A
+    //~ node RW0O_0_4 = bits(mem_0_4.RW0O, 1, 0)
+    //~ mem_0_4.RW0I <= bits(RW0I, 9, 8)
+    //~ mem_0_4.RW0W <= and(and(RW0W, bits(RW0M, 4, 4)), UInt<1>("h1"))
+    //~ mem_0_4.RW0E <= and(RW0E, UInt<1>("h1"))
+    //~ mem_0_5.clock <= clock
+    //~ mem_0_5.RW0A <= RW0A
+    //~ node RW0O_0_5 = bits(mem_0_5.RW0O, 1, 0)
+    //~ mem_0_5.RW0I <= bits(RW0I, 11, 10)
+    //~ mem_0_5.RW0W <= and(and(RW0W, bits(RW0M, 5, 5)), UInt<1>("h1"))
+    //~ mem_0_5.RW0E <= and(RW0E, UInt<1>("h1"))
+    //~ mem_0_6.clock <= clock
+    //~ mem_0_6.RW0A <= RW0A
+    //~ node RW0O_0_6 = bits(mem_0_6.RW0O, 1, 0)
+    //~ mem_0_6.RW0I <= bits(RW0I, 13, 12)
+    //~ mem_0_6.RW0W <= and(and(RW0W, bits(RW0M, 6, 6)), UInt<1>("h1"))
+    //~ mem_0_6.RW0E <= and(RW0E, UInt<1>("h1"))
+    //~ mem_0_7.clock <= clock
+    //~ mem_0_7.RW0A <= RW0A
+    //~ node RW0O_0_7 = bits(mem_0_7.RW0O, 1, 0)
+    //~ mem_0_7.RW0I <= bits(RW0I, 15, 14)
+    //~ mem_0_7.RW0W <= and(and(RW0W, bits(RW0M, 7, 7)), UInt<1>("h1"))
+    //~ mem_0_7.RW0E <= and(RW0E, UInt<1>("h1"))
+    //~ node RW0O_0 = cat(RW0O_0_7, cat(RW0O_0_6, cat(RW0O_0_5, cat(RW0O_0_4, cat(RW0O_0_3, cat(RW0O_0_2, cat(RW0O_0_1, RW0O_0_0)))))))
+    //~ RW0O <= mux(UInt<1>("h1"), RW0O_0, UInt<1>("h0"))
+
+  //~ extmodule vendor_sram :
+    //~ input clock : Clock
+    //~ input RW0A : UInt<11>
+    //~ input RW0I : UInt<10>
+    //~ output RW0O : UInt<10>
+    //~ input RW0E : UInt<1>
+    //~ input RW0W : UInt<1>
+
+    //~ defname = vendor_sram
+//~ """
+  //~ compile(mem, Some(lib), v, false)
+  //~ execute(Some(mem), Some(lib), false, output)
+//~ }
+
+//~ class SplitWidth2048x16_mrw_ReadEnable extends MacroCompilerSpec {
+  //~ val mem = new File(macroDir, "mem-2048x16-mrw.json")
+  //~ val lib = new File(macroDir, "lib-2048x8-mrw-re.json")
+  //~ val v = new File(testDir, "split_width_2048x16_mrw_read_enable.v")
+  //~ val output =
+//~ """
+//~ circuit name_of_sram_module :
+  //~ module name_of_sram_module :
+    //~ input clock : Clock
+    //~ input RW0A : UInt<11>
+    //~ input RW0I : UInt<16>
+    //~ output RW0O : UInt<16>
+    //~ input RW0E : UInt<1>
+    //~ input RW0W : UInt<1>
+    //~ input RW0M : UInt<2>
+
+    //~ inst mem_0_0 of vendor_sram
+    //~ inst mem_0_1 of vendor_sram
+    //~ mem_0_0.clock <= clock
+    //~ mem_0_0.RW0A <= RW0A
+    //~ node RW0O_0_0 = bits(mem_0_0.RW0O, 7, 0)
+    //~ mem_0_0.RW0I <= bits(RW0I, 7, 0)
+    //~ mem_0_0.RW0R <= not(and(not(RW0W), UInt<1>("h1")))
+    //~ mem_0_0.RW0M <= bits(RW0M, 0, 0)
+    //~ mem_0_0.RW0W <= and(RW0W, UInt<1>("h1"))
+    //~ mem_0_0.RW0E <= and(RW0E, UInt<1>("h1"))
+    //~ mem_0_1.clock <= clock
+    //~ mem_0_1.RW0A <= RW0A
+    //~ node RW0O_0_1 = bits(mem_0_1.RW0O, 7, 0)
+    //~ mem_0_1.RW0I <= bits(RW0I, 15, 8)
+    //~ mem_0_1.RW0R <= not(and(not(RW0W), UInt<1>("h1")))
+    //~ mem_0_1.RW0M <= bits(RW0M, 1, 1)
+    //~ mem_0_1.RW0W <= and(RW0W, UInt<1>("h1"))
+    //~ mem_0_1.RW0E <= and(RW0E, UInt<1>("h1"))
+    //~ node RW0O_0 = cat(RW0O_0_1, RW0O_0_0)
+    //~ RW0O <= mux(UInt<1>("h1"), RW0O_0, UInt<1>("h0"))
+
+  //~ extmodule vendor_sram :
+    //~ input clock : Clock
+    //~ input RW0A : UInt<11>
+    //~ input RW0I : UInt<8>
+    //~ output RW0O : UInt<8>
+    //~ input RW0E : UInt<1>
+    //~ input RW0R : UInt<1>
+    //~ input RW0W : UInt<1>
+    //~ input RW0M : UInt<1>
+
+    //~ defname = vendor_sram
+//~ """
+  //~ compile(mem, Some(lib), v, false)
+  //~ execute(Some(mem), Some(lib), false, output)
+//~ }
+
+//~ class SplitWidth2048x16_n28 extends MacroCompilerSpec {
+  //~ val mem = new File(macroDir, "mem-2048x16-mrw.json")
+  //~ val lib = new File(macroDir, "lib-2048x16-n28.json")
+  //~ val v = new File(testDir, "split_width_2048x16_n28.v")
+  //~ val output =
+//~ """
+//~ circuit name_of_sram_module :
+  //~ module name_of_sram_module :
+    //~ input clock : Clock
+    //~ input RW0A : UInt<11>
+    //~ input RW0I : UInt<16>
+    //~ output RW0O : UInt<16>
+    //~ input RW0E : UInt<1>
+    //~ input RW0W : UInt<1>
+    //~ input RW0M : UInt<2>
+
+    //~ inst mem_0_0 of vendor_sram_16
+    //~ mem_0_0.clock <= clock
+    //~ mem_0_0.RW0A <= RW0A
+    //~ node RW0O_0_0 = bits(mem_0_0.RW0O, 15, 0)
+    //~ mem_0_0.RW0I <= bits(RW0I, 15, 0)
+    //~ mem_0_0.RW0M <= cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), bits(RW0M, 0, 0))))))))))))))))
+    //~ mem_0_0.RW0W <= and(RW0W, UInt<1>("h1"))
+    //~ mem_0_0.RW0E <= and(RW0E, UInt<1>("h1"))
+    //~ node RW0O_0 = RW0O_0_0
+    //~ RW0O <= mux(UInt<1>("h1"), RW0O_0, UInt<1>("h0"))
+
+  //~ extmodule vendor_sram_16 :
+    //~ input clock : Clock
+    //~ input RW0A : UInt<11>
+    //~ input RW0I : UInt<16>
+    //~ output RW0O : UInt<16>
+    //~ input RW0E : UInt<1>
+    //~ input RW0W : UInt<1>
+    //~ input RW0M : UInt<16>
+
+    //~ defname = vendor_sram_16
+//~ """
+  //~ compile(mem, Some(lib), v, false)
+  //~ execute(Some(mem), Some(lib), false, output)
+//~ }
+
+//~ class SplitWidth2048x20_mrw_UnevenMask extends MacroCompilerSpec {
+  //~ val mem = new File(macroDir, "mem-2048x20-mrw.json")
+  //~ val lib = new File(macroDir, "lib-2048x8-mrw.json")
+  //~ val v = new File(testDir, "split_width_2048x20_mrw_uneven_mask.v")
+  //~ val output =
+//~ """
+//~ circuit name_of_sram_module :
+  //~ module name_of_sram_module :
+    //~ input clock : Clock
+    //~ input RW0A : UInt<11>
+    //~ input RW0I : UInt<20>
+    //~ output RW0O : UInt<20>
+    //~ input RW0E : UInt<1>
+    //~ input RW0W : UInt<1>
+    //~ input RW0M : UInt<2>
+
+    //~ inst mem_0_0 of vendor_sram
+    //~ inst mem_0_1 of vendor_sram
+    //~ inst mem_0_2 of vendor_sram
+    //~ inst mem_0_3 of vendor_sram
+    //~ mem_0_0.clock <= clock
+    //~ mem_0_0.RW0A <= RW0A
+    //~ node RW0O_0_0 = bits(mem_0_0.RW0O, 7, 0)
+    //~ mem_0_0.RW0I <= bits(RW0I, 7, 0)
+    //~ mem_0_0.RW0M <= bits(RW0M, 0, 0)
+    //~ mem_0_0.RW0W <= and(RW0W, UInt<1>("h1"))
+    //~ mem_0_0.RW0E <= and(RW0E, UInt<1>("h1"))
+    //~ mem_0_1.clock <= clock
+    //~ mem_0_1.RW0A <= RW0A
+    //~ node RW0O_0_1 = bits(mem_0_1.RW0O, 1, 0)
+    //~ mem_0_1.RW0I <= bits(RW0I, 9, 8)
+    //~ mem_0_1.RW0M <= bits(RW0M, 0, 0)
+    //~ mem_0_1.RW0W <= and(RW0W, UInt<1>("h1"))
+    //~ mem_0_1.RW0E <= and(RW0E, UInt<1>("h1"))
+    //~ mem_0_2.clock <= clock
+    //~ mem_0_2.RW0A <= RW0A
+    //~ node RW0O_0_2 = bits(mem_0_2.RW0O, 7, 0)
+    //~ mem_0_2.RW0I <= bits(RW0I, 17, 10)
+    //~ mem_0_2.RW0M <= bits(RW0M, 1, 1)
+    //~ mem_0_2.RW0W <= and(RW0W, UInt<1>("h1"))
+    //~ mem_0_2.RW0E <= and(RW0E, UInt<1>("h1"))
+    //~ mem_0_3.clock <= clock
+    //~ mem_0_3.RW0A <= RW0A
+    //~ node RW0O_0_3 = bits(mem_0_3.RW0O, 1, 0)
+    //~ mem_0_3.RW0I <= bits(RW0I, 19, 18)
+    //~ mem_0_3.RW0M <= bits(RW0M, 1, 1)
+    //~ mem_0_3.RW0W <= and(RW0W, UInt<1>("h1"))
+    //~ mem_0_3.RW0E <= and(RW0E, UInt<1>("h1"))
+    //~ node RW0O_0 = cat(RW0O_0_3, cat(RW0O_0_2, cat(RW0O_0_1, RW0O_0_0)))
+    //~ RW0O <= mux(UInt<1>("h1"), RW0O_0, UInt<1>("h0"))
+
+  //~ extmodule vendor_sram :
+    //~ input clock : Clock
+    //~ input RW0A : UInt<11>
+    //~ input RW0I : UInt<8>
+    //~ output RW0O : UInt<8>
+    //~ input RW0E : UInt<1>
+    //~ input RW0W : UInt<1>
+    //~ input RW0M : UInt<1>
+
+    //~ defname = vendor_sram
+//~ """
+  //~ compile(mem, Some(lib), v, false)
+  //~ execute(Some(mem), Some(lib), false, output)
+//~ }
+
+//~ class SplitWidth24x52 extends MacroCompilerSpec {
+  //~ val mem = new File(macroDir, "mem-24x52-r-w.json")
+  //~ val lib = new File(macroDir, "lib-32x32-2rw.json")
+  //~ val v = new File(testDir, "split_width_24x52.v")
+  //~ val output =
+//~ """
+//~ circuit entries_info_ext :
+  //~ module entries_info_ext :
+    //~ input R0_clk : Clock
+    //~ input R0_addr : UInt<5>
+    //~ output R0_data : UInt<52>
+    //~ input R0_en : UInt<1>
+    //~ input W0_clk : Clock
+    //~ input W0_addr : UInt<5>
+    //~ input W0_data : UInt<52>
+    //~ input W0_en : UInt<1>
+
+    //~ inst mem_0_0 of SRAM2RW32x32
+    //~ inst mem_0_1 of SRAM2RW32x32
+    //~ mem_0_0.CE1 <= W0_clk
+    //~ mem_0_0.A1 <= W0_addr
+    //~ mem_0_0.I1 <= bits(W0_data, 31, 0)
+    //~ mem_0_0.OEB1 <= not(and(not(UInt<1>("h1")), UInt<1>("h1")))
+    //~ mem_0_0.WEB1 <= not(and(and(UInt<1>("h1"), UInt<1>("h1")), UInt<1>("h1")))
+    //~ mem_0_0.CSB1 <= not(and(W0_en, UInt<1>("h1")))
+    //~ mem_0_1.CE1 <= W0_clk
+    //~ mem_0_1.A1 <= W0_addr
+    //~ mem_0_1.I1 <= bits(W0_data, 51, 32)
+    //~ mem_0_1.OEB1 <= not(and(not(UInt<1>("h1")), UInt<1>("h1")))
+    //~ mem_0_1.WEB1 <= not(and(and(UInt<1>("h1"), UInt<1>("h1")), UInt<1>("h1")))
+    //~ mem_0_1.CSB1 <= not(and(W0_en, UInt<1>("h1")))
+    //~ mem_0_0.CE2 <= R0_clk
+    //~ mem_0_0.A2 <= R0_addr
+    //~ node R0_data_0_0 = bits(mem_0_0.O2, 31, 0)
+    //~ mem_0_0.OEB2 <= not(and(not(UInt<1>("h0")), UInt<1>("h1")))
+    //~ mem_0_0.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), UInt<1>("h1")))
+    //~ mem_0_0.CSB2 <= not(and(R0_en, UInt<1>("h1")))
+    //~ mem_0_1.CE2 <= R0_clk
+    //~ mem_0_1.A2 <= R0_addr
+    //~ node R0_data_0_1 = bits(mem_0_1.O2, 19, 0)
+    //~ mem_0_1.OEB2 <= not(and(not(UInt<1>("h0")), UInt<1>("h1")))
+    //~ mem_0_1.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), UInt<1>("h1")))
+    //~ mem_0_1.CSB2 <= not(and(R0_en, UInt<1>("h1")))
+    //~ node R0_data_0 = cat(R0_data_0_1, R0_data_0_0)
+    //~ R0_data <= mux(UInt<1>("h1"), R0_data_0, UInt<1>("h0"))
+
+  //~ extmodule SRAM2RW32x32 :
+    //~ input CE1 : Clock
+    //~ input A1 : UInt<5>
+    //~ input I1 : UInt<32>
+    //~ output O1 : UInt<32>
+    //~ input CSB1 : UInt<1>
+    //~ input OEB1 : UInt<1>
+    //~ input WEB1 : UInt<1>
+    //~ input CE2 : Clock
+    //~ input A2 : UInt<5>
+    //~ input I2 : UInt<32>
+    //~ output O2 : UInt<32>
+    //~ input CSB2 : UInt<1>
+    //~ input OEB2 : UInt<1>
+    //~ input WEB2 : UInt<1>
+
+    //~ defname = SRAM2RW32x32
+//~ """
+  //~ compile(mem, Some(lib), v, false)
+  //~ execute(Some(mem), Some(lib), false, output)
+//~ }
+
+//~ class SplitWidth32x160 extends MacroCompilerSpec {
+  //~ val mem = new File(macroDir, "mem-32x160-mrw.json")
+  //~ val lib = new File(macroDir, "lib-32x80-mrw.json")
+  //~ val v = new File(testDir, "split_width_32x160.v")
+  //~ val output =
+//~ """
+//~ circuit name_of_sram_module :
+  //~ module name_of_sram_module :
+    //~ input clock : Clock
+    //~ input RW0A : UInt<5>
+    //~ input RW0I : UInt<160>
+    //~ output RW0O : UInt<160>
+    //~ input RW0E : UInt<1>
+    //~ input RW0W : UInt<1>
+    //~ input RW0M : UInt<8>
+
+    //~ inst mem_0_0 of vendor_sram
+    //~ inst mem_0_1 of vendor_sram
+    //~ mem_0_0.clock <= clock
+    //~ mem_0_0.RW0A <= RW0A
+    //~ node RW0O_0_0 = bits(mem_0_0.RW0O, 79, 0)
+    //~ mem_0_0.RW0I <= bits(RW0I, 79, 0)
+    //~ mem_0_0.RW0M <= cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), bits(RW0M, 0, 0))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))
+    //~ mem_0_0.RW0W <= and(RW0W, UInt<1>("h1"))
+    //~ mem_0_0.RW0E <= and(RW0E, UInt<1>("h1"))
+    //~ mem_0_1.clock <= clock
+    //~ mem_0_1.RW0A <= RW0A
+    //~ node RW0O_0_1 = bits(mem_0_1.RW0O, 79, 0)
+    //~ mem_0_1.RW0I <= bits(RW0I, 159, 80)
+    //~ mem_0_1.RW0M <= cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), bits(RW0M, 4, 4))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))
+    //~ mem_0_1.RW0W <= and(RW0W, UInt<1>("h1"))
+    //~ mem_0_1.RW0E <= and(RW0E, UInt<1>("h1"))
+    //~ node RW0O_0 = cat(RW0O_0_1, RW0O_0_0)
+    //~ RW0O <= mux(UInt<1>("h1"), RW0O_0, UInt<1>("h0"))
+
+  //~ extmodule vendor_sram :
+    //~ input clock : Clock
+    //~ input RW0A : UInt<5>
+    //~ input RW0I : UInt<80>
+    //~ output RW0O : UInt<80>
+    //~ input RW0E : UInt<1>
+    //~ input RW0W : UInt<1>
+    //~ input RW0M : UInt<80>
+
+    //~ defname = vendor_sram
+//~ """
+  //~ compile(mem, Some(lib), v, false)
+  //~ execute(Some(mem), Some(lib), false, output)
+//~ }
--- a/macros/src/test/scala/SynFlops.scala
+++ b/macros/src/test/scala/SynFlops.scala
@@ -0,0 +1,333 @@
+//~ package barstools.tapeout.transforms.macros
+
+//~ import java.io.File
+
+//~ class Synflops2048x16_mrw extends MacroCompilerSpec {
+  //~ val mem = new File(macroDir, "mem-2048x16-mrw.json")
+  //~ val v = new File(testDir, "syn_flops_2048x16_mrw.v")
+  //~ val output =
+//~ """
+//~ circuit name_of_sram_module :
+  //~ module name_of_sram_module :
+    //~ input clock : Clock
+    //~ input RW0A : UInt<11>
+    //~ input RW0I : UInt<16>
+    //~ output RW0O : UInt<16>
+    //~ input RW0E : UInt<1>
+    //~ input RW0W : UInt<1>
+    //~ input RW0M : UInt<2>
+
+    //~ mem ram :
+      //~ data-type => UInt<8>[2]
+      //~ depth => 2048
+      //~ read-latency => 0
+      //~ write-latency => 1
+      //~ reader => R_0
+      //~ writer => W_0
+      //~ read-under-write => undefined
+    //~ reg R_0_addr_reg : UInt<11>, clock with :
+      //~ reset => (UInt<1>("h0"), R_0_addr_reg)
+    //~ ram.R_0.clk <= clock
+    //~ ram.R_0.addr <= R_0_addr_reg
+    //~ ram.R_0.en <= RW0E
+    //~ RW0O <= cat(ram.R_0.data[1], ram.R_0.data[0])
+    //~ R_0_addr_reg <= mux(RW0E, RW0A, R_0_addr_reg)
+    //~ ram.W_0.clk <= clock
+    //~ ram.W_0.addr <= RW0A
+    //~ ram.W_0.en <= and(RW0E, RW0W)
+    //~ ram.W_0.data[0] <= bits(RW0I, 7, 0)
+    //~ ram.W_0.data[1] <= bits(RW0I, 15, 8)
+    //~ ram.W_0.mask[0] <= bits(RW0M, 0, 0)
+    //~ ram.W_0.mask[1] <= bits(RW0M, 1, 1)
+//~ """
+  //~ compile(mem, None, v, true)
+  //~ execute(Some(mem), None, true, output)
+//~ }
+
+//~ class Synflops2048x8_r_mw extends MacroCompilerSpec {
+  //~ val mem = new File(macroDir, "mem-2048x8-r-mw.json")
+  //~ val v = new File(testDir, "syn_flops_2048x8_r_mw.v")
+  //~ val output =
+//~ """
+//~ circuit name_of_sram_module :
+  //~ module name_of_sram_module :
+    //~ input clock : Clock
+    //~ input W0A : UInt<11>
+    //~ input W0I : UInt<8>
+    //~ input W0E : UInt<1>
+    //~ input W0M : UInt<1>
+    //~ input clock : Clock
+    //~ input R0A : UInt<11>
+    //~ output R0O : UInt<8>
+
+    //~ mem ram :
+      //~ data-type => UInt<8>[1]
+      //~ depth => 2048
+      //~ read-latency => 0
+      //~ write-latency => 1
+      //~ reader => R_0
+      //~ writer => W_0
+      //~ read-under-write => undefined
+    //~ reg R_0_addr_reg : UInt<11>, clock with :
+      //~ reset => (UInt<1>("h0"), R_0_addr_reg)
+    //~ ram.R_0.clk <= clock
+    //~ ram.R_0.addr <= R_0_addr_reg
+    //~ ram.R_0.en <= UInt<1>("h1")
+    //~ R0O <= ram.R_0.data[0]
+    //~ R_0_addr_reg <= mux(UInt<1>("h1"), R0A, R_0_addr_reg)
+    //~ ram.W_0.clk <= clock
+    //~ ram.W_0.addr <= W0A
+    //~ ram.W_0.en <= W0E
+    //~ ram.W_0.data[0] <= bits(W0I, 7, 0)
+    //~ ram.W_0.mask[0] <= bits(W0M, 0, 0)
+//~ """
+  //~ compile(mem, None, v, true)
+  //~ execute(Some(mem), None, true, output)
+//~ }
+
+//~ class Synflops2048x10_rw extends MacroCompilerSpec {
+  //~ val mem = new File(macroDir, "lib-2048x10-rw.json")
+  //~ val v = new File(testDir, "syn_flops_2048x10_rw.v")
+  //~ val output =
+//~ """
+//~ circuit vendor_sram :
+  //~ module vendor_sram :
+    //~ input clock : Clock
+    //~ input RW0A : UInt<11>
+    //~ input RW0I : UInt<10>
+    //~ output RW0O : UInt<10>
+    //~ input RW0E : UInt<1>
+    //~ input RW0W : UInt<1>
+
+    //~ mem ram :
+      //~ data-type => UInt<10>
+      //~ depth => 2048
+      //~ read-latency => 0
+      //~ write-latency => 1
+      //~ reader => R_0
+      //~ writer => W_0
+      //~ read-under-write => undefined
+    //~ reg R_0_addr_reg : UInt<11>, clock with :
+      //~ reset => (UInt<1>("h0"), R_0_addr_reg)
+    //~ ram.R_0.clk <= clock
+    //~ ram.R_0.addr <= R_0_addr_reg
+    //~ ram.R_0.en <= RW0E
+    //~ RW0O <= ram.R_0.data
+    //~ R_0_addr_reg <= mux(RW0E, RW0A, R_0_addr_reg)
+    //~ ram.W_0.clk <= clock
+    //~ ram.W_0.addr <= RW0A
+    //~ ram.W_0.en <= and(RW0E, RW0W)
+    //~ ram.W_0.data <= RW0I
+    //~ ram.W_0.mask <= UInt<1>("h1")
+//~ """
+  //~ compile(mem, None, v, true)
+  //~ execute(Some(mem), None, true, output)
+//~ }
+
+//~ class Synflops2048x8_mrw_re extends MacroCompilerSpec {
+  //~ val mem = new File(macroDir, "lib-2048x8-mrw-re.json")
+  //~ val v = new File(testDir, "syn_flops_2048x8_mrw_re.v")
+  //~ val output =
+//~ """
+//~ circuit vendor_sram :
+  //~ module vendor_sram :
+    //~ input clock : Clock
+    //~ input RW0A : UInt<11>
+    //~ input RW0I : UInt<8>
+    //~ output RW0O : UInt<8>
+    //~ input RW0E : UInt<1>
+    //~ input RW0R : UInt<1>
+    //~ input RW0W : UInt<1>
+    //~ input RW0M : UInt<1>
+
+    //~ mem ram :
+      //~ data-type => UInt<8>[1]
+      //~ depth => 2048
+      //~ read-latency => 0
+      //~ write-latency => 1
+      //~ reader => R_0
+      //~ writer => W_0
+      //~ read-under-write => undefined
+    //~ reg R_0_addr_reg : UInt<11>, clock with :
+      //~ reset => (UInt<1>("h0"), R_0_addr_reg)
+    //~ ram.R_0.clk <= clock
+    //~ ram.R_0.addr <= R_0_addr_reg
+    //~ ram.R_0.en <= and(RW0E, not(RW0R))
+    //~ RW0O <= ram.R_0.data[0]
+    //~ R_0_addr_reg <= mux(and(RW0E, not(RW0R)), RW0A, R_0_addr_reg)
+    //~ ram.W_0.clk <= clock
+    //~ ram.W_0.addr <= RW0A
+    //~ ram.W_0.en <= and(RW0E, RW0W)
+    //~ ram.W_0.data[0] <= bits(RW0I, 7, 0)
+    //~ ram.W_0.mask[0] <= bits(RW0M, 0, 0)
+//~ """
+  //~ compile(mem, None, v, true)
+  //~ execute(Some(mem), None, true, output)
+//~ }
+
+//~ class Synflops2048x16_n28 extends MacroCompilerSpec {
+  //~ val mem = new File(macroDir, "lib-2048x16-n28.json")
+  //~ val v = new File(testDir, "syn_flops_2048x16_n28.v")
+  //~ val output =
+//~ """
+//~ circuit vendor_sram_4 :
+  //~ module vendor_sram_16 :
+    //~ input clock : Clock
+    //~ input RW0A : UInt<11>
+    //~ input RW0I : UInt<16>
+    //~ output RW0O : UInt<16>
+    //~ input RW0E : UInt<1>
+    //~ input RW0W : UInt<1>
+    //~ input RW0M : UInt<16>
+
+    //~ mem ram :
+      //~ data-type => UInt<1>[16]
+      //~ depth => 2048
+      //~ read-latency => 0
+      //~ write-latency => 1
+      //~ reader => R_0
+      //~ writer => W_0
+      //~ read-under-write => undefined
+    //~ reg R_0_addr_reg : UInt<11>, clock with :
+      //~ reset => (UInt<1>("h0"), R_0_addr_reg)
+    //~ ram.R_0.clk <= clock
+    //~ ram.R_0.addr <= R_0_addr_reg
+    //~ ram.R_0.en <= RW0E
+    //~ RW0O <= cat(ram.R_0.data[15], cat(ram.R_0.data[14], cat(ram.R_0.data[13], cat(ram.R_0.data[12], cat(ram.R_0.data[11], cat(ram.R_0.data[10], cat(ram.R_0.data[9], cat(ram.R_0.data[8], cat(ram.R_0.data[7], cat(ram.R_0.data[6], cat(ram.R_0.data[5], cat(ram.R_0.data[4], cat(ram.R_0.data[3], cat(ram.R_0.data[2], cat(ram.R_0.data[1], ram.R_0.data[0])))))))))))))))
+    //~ R_0_addr_reg <= mux(RW0E, RW0A, R_0_addr_reg)
+    //~ ram.W_0.clk <= clock
+    //~ ram.W_0.addr <= RW0A
+    //~ ram.W_0.en <= and(RW0E, RW0W)
+    //~ ram.W_0.data[0] <= bits(RW0I, 0, 0)
+    //~ ram.W_0.data[1] <= bits(RW0I, 1, 1)
+    //~ ram.W_0.data[2] <= bits(RW0I, 2, 2)
+    //~ ram.W_0.data[3] <= bits(RW0I, 3, 3)
+    //~ ram.W_0.data[4] <= bits(RW0I, 4, 4)
+    //~ ram.W_0.data[5] <= bits(RW0I, 5, 5)
+    //~ ram.W_0.data[6] <= bits(RW0I, 6, 6)
+    //~ ram.W_0.data[7] <= bits(RW0I, 7, 7)
+    //~ ram.W_0.data[8] <= bits(RW0I, 8, 8)
+    //~ ram.W_0.data[9] <= bits(RW0I, 9, 9)
+    //~ ram.W_0.data[10] <= bits(RW0I, 10, 10)
+    //~ ram.W_0.data[11] <= bits(RW0I, 11, 11)
+    //~ ram.W_0.data[12] <= bits(RW0I, 12, 12)
+    //~ ram.W_0.data[13] <= bits(RW0I, 13, 13)
+    //~ ram.W_0.data[14] <= bits(RW0I, 14, 14)
+    //~ ram.W_0.data[15] <= bits(RW0I, 15, 15)
+    //~ ram.W_0.mask[0] <= bits(RW0M, 0, 0)
+    //~ ram.W_0.mask[1] <= bits(RW0M, 1, 1)
+    //~ ram.W_0.mask[2] <= bits(RW0M, 2, 2)
+    //~ ram.W_0.mask[3] <= bits(RW0M, 3, 3)
+    //~ ram.W_0.mask[4] <= bits(RW0M, 4, 4)
+    //~ ram.W_0.mask[5] <= bits(RW0M, 5, 5)
+    //~ ram.W_0.mask[6] <= bits(RW0M, 6, 6)
+    //~ ram.W_0.mask[7] <= bits(RW0M, 7, 7)
+    //~ ram.W_0.mask[8] <= bits(RW0M, 8, 8)
+    //~ ram.W_0.mask[9] <= bits(RW0M, 9, 9)
+    //~ ram.W_0.mask[10] <= bits(RW0M, 10, 10)
+    //~ ram.W_0.mask[11] <= bits(RW0M, 11, 11)
+    //~ ram.W_0.mask[12] <= bits(RW0M, 12, 12)
+    //~ ram.W_0.mask[13] <= bits(RW0M, 13, 13)
+    //~ ram.W_0.mask[14] <= bits(RW0M, 14, 14)
+    //~ ram.W_0.mask[15] <= bits(RW0M, 15, 15)
+
+  //~ module vendor_sram_4 :
+    //~ input clock : Clock
+    //~ input RW0A : UInt<11>
+    //~ input RW0I : UInt<4>
+    //~ output RW0O : UInt<4>
+    //~ input RW0E : UInt<1>
+    //~ input RW0W : UInt<1>
+    //~ input RW0M : UInt<4>
+
+    //~ mem ram :
+      //~ data-type => UInt<1>[4]
+      //~ depth => 2048
+      //~ read-latency => 0
+      //~ write-latency => 1
+      //~ reader => R_0
+      //~ writer => W_0
+      //~ read-under-write => undefined
+    //~ reg R_0_addr_reg : UInt<11>, clock with :
+      //~ reset => (UInt<1>("h0"), R_0_addr_reg)
+    //~ ram.R_0.clk <= clock
+    //~ ram.R_0.addr <= R_0_addr_reg
+    //~ ram.R_0.en <= RW0E
+    //~ RW0O <= cat(ram.R_0.data[3], cat(ram.R_0.data[2], cat(ram.R_0.data[1], ram.R_0.data[0])))
+    //~ R_0_addr_reg <= mux(RW0E, RW0A, R_0_addr_reg)
+    //~ ram.W_0.clk <= clock
+    //~ ram.W_0.addr <= RW0A
+    //~ ram.W_0.en <= and(RW0E, RW0W)
+    //~ ram.W_0.data[0] <= bits(RW0I, 0, 0)
+    //~ ram.W_0.data[1] <= bits(RW0I, 1, 1)
+    //~ ram.W_0.data[2] <= bits(RW0I, 2, 2)
+    //~ ram.W_0.data[3] <= bits(RW0I, 3, 3)
+    //~ ram.W_0.mask[0] <= bits(RW0M, 0, 0)
+    //~ ram.W_0.mask[1] <= bits(RW0M, 1, 1)
+    //~ ram.W_0.mask[2] <= bits(RW0M, 2, 2)
+    //~ ram.W_0.mask[3] <= bits(RW0M, 3, 3)
+//~ """
+  //~ compile(mem, None, v, true)
+  //~ execute(Some(mem), None, true, output)
+//~ }
+
+//~ class Synflops32x32_2rw extends MacroCompilerSpec {
+  //~ val mem = new File(macroDir, "lib-32x32-2rw.json")
+  //~ val v = new File(testDir, "syn_flops_32x32_2rw.v")
+  //~ val output =
+//~ """
+//~ circuit SRAM2RW32x32 :
+  //~ module SRAM2RW32x32 :
+    //~ input CE1 : Clock
+    //~ input A1 : UInt<5>
+    //~ input I1 : UInt<32>
+    //~ output O1 : UInt<32>
+    //~ input CSB1 : UInt<1>
+    //~ input OEB1 : UInt<1>
+    //~ input WEB1 : UInt<1>
+    //~ input CE2 : Clock
+    //~ input A2 : UInt<5>
+    //~ input I2 : UInt<32>
+    //~ output O2 : UInt<32>
+    //~ input CSB2 : UInt<1>
+    //~ input OEB2 : UInt<1>
+    //~ input WEB2 : UInt<1>
+
+    //~ mem ram :
+      //~ data-type => UInt<32>
+      //~ depth => 32
+      //~ read-latency => 0
+      //~ write-latency => 1
+      //~ reader => R_0
+      //~ reader => R_1
+      //~ writer => W_0
+      //~ writer => W_1
+      //~ read-under-write => undefined
+    //~ reg R_0_addr_reg : UInt<5>, CE1 with :
+      //~ reset => (UInt<1>("h0"), R_0_addr_reg)
+    //~ ram.R_0.clk <= CE1
+    //~ ram.R_0.addr <= R_0_addr_reg
+    //~ ram.R_0.en <= and(not(CSB1), not(OEB1))
+    //~ O1 <= ram.R_0.data
+    //~ R_0_addr_reg <= mux(and(not(CSB1), not(OEB1)), A1, R_0_addr_reg)
+    //~ reg R_1_addr_reg : UInt<5>, CE2 with :
+      //~ reset => (UInt<1>("h0"), R_1_addr_reg)
+    //~ ram.R_1.clk <= CE2
+    //~ ram.R_1.addr <= R_1_addr_reg
+    //~ ram.R_1.en <= and(not(CSB2), not(OEB2))
+    //~ O2 <= ram.R_1.data
+    //~ R_1_addr_reg <= mux(and(not(CSB2), not(OEB2)), A2, R_1_addr_reg)
+    //~ ram.W_0.clk <= CE1
+    //~ ram.W_0.addr <= A1
+    //~ ram.W_0.en <= and(not(CSB1), not(WEB1))
+    //~ ram.W_0.data <= I1
+    //~ ram.W_0.mask <= UInt<1>("h1")
+    //~ ram.W_1.clk <= CE2
+    //~ ram.W_1.addr <= A2
+    //~ ram.W_1.en <= and(not(CSB2), not(WEB2))
+    //~ ram.W_1.data <= I2
+    //~ ram.W_1.mask <= UInt<1>("h1")
+//~ """
+  //~ compile(mem, None, v, true)
+  //~ execute(Some(mem), None, true, output)
+//~ }