100 lines
3.8 KiB
Scala
100 lines
3.8 KiB
Scala
// See LICENSE for license details.
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package barstools.macros
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import firrtl._
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import firrtl.ir._
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import firrtl.PrimOps
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import firrtl.Utils.{ceilLog2, BoolType}
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import mdf.macrolib.{Constant, MacroPort, SRAMMacro}
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import mdf.macrolib.{PolarizedPort, PortPolarity, ActiveLow, ActiveHigh, NegativeEdge, PositiveEdge}
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import java.io.File
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import scala.language.implicitConversions
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class FirrtlMacroPort(port: MacroPort) {
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val src = port
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val isReader = !port.readEnable.isEmpty && port.writeEnable.isEmpty
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val isWriter = !port.writeEnable.isEmpty && port.readEnable.isEmpty
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val isReadWriter = !port.writeEnable.isEmpty && !port.readEnable.isEmpty
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val addrType = UIntType(IntWidth(ceilLog2(port.depth) max 1))
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val dataType = UIntType(IntWidth(port.width))
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val maskType = UIntType(IntWidth(port.width / port.effectiveMaskGran))
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// Bundle representing this macro port.
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val tpe = BundleType(Seq(
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Field(port.clock.name, Flip, ClockType),
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Field(port.address.name, Flip, addrType)) ++
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(port.input map (p => Field(p.name, Flip, dataType))) ++
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(port.output map (p => Field(p.name, Default, dataType))) ++
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(port.chipEnable map (p => Field(p.name, Flip, BoolType))) ++
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(port.readEnable map (p => Field(p.name, Flip, BoolType))) ++
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(port.writeEnable map (p => Field(p.name, Flip, BoolType))) ++
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(port.maskPort map (p => Field(p.name, Flip, maskType)))
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)
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val ports = tpe.fields map (f => Port(
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NoInfo, f.name, f.flip match { case Default => Output case Flip => Input }, f.tpe))
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}
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// Reads an SRAMMacro and generates firrtl blackboxes.
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class Macro(srcMacro: SRAMMacro) {
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val src = srcMacro
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val firrtlPorts = srcMacro.ports map { new FirrtlMacroPort(_) }
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val writers = firrtlPorts filter (p => p.isReader)
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val readers = firrtlPorts filter (p => p.isWriter)
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val readwriters = firrtlPorts filter (p => p.isReadWriter)
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val sortedPorts = writers ++ readers ++ readwriters
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val extraPorts = srcMacro.extraPorts map { p =>
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assert(p.portType == Constant) // TODO: release it?
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val name = p.name
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val width = BigInt(p.width.toLong)
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val value = BigInt(p.value.toLong)
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(name -> UIntLiteral(value, IntWidth(width)))
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}
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// Bundle representing this memory blackbox
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val tpe = BundleType(firrtlPorts flatMap (_.tpe.fields))
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private val modPorts = (firrtlPorts flatMap (_.ports)) ++
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(extraPorts map { case (name, value) => Port(NoInfo, name, Input, value.tpe) })
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val blackbox = ExtModule(NoInfo, srcMacro.name, modPorts, srcMacro.name, Nil)
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def module(body: Statement) = Module(NoInfo, srcMacro.name, modPorts, body)
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}
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object Utils {
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def filterForSRAM(s: Option[Seq[mdf.macrolib.Macro]]): Option[Seq[mdf.macrolib.SRAMMacro]] = {
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s match {
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case Some(l:Seq[mdf.macrolib.Macro]) => Some(l filter { _.macroType == mdf.macrolib.SRAM } map { m => m.asInstanceOf[mdf.macrolib.SRAMMacro] })
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case _ => None
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}
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}
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def and(e1: Expression, e2: Expression) =
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DoPrim(PrimOps.And, Seq(e1, e2), Nil, e1.tpe)
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def bits(e: Expression, high: BigInt, low: BigInt): Expression =
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DoPrim(PrimOps.Bits, Seq(e), Seq(high, low), UIntType(IntWidth(high-low+1)))
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def bits(e: Expression, idx: BigInt): Expression = bits(e, idx, idx)
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def cat(es: Seq[Expression]): Expression =
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if (es.size == 1) es.head
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else DoPrim(PrimOps.Cat, Seq(es.head, cat(es.tail)), Nil, UnknownType)
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def not(e: Expression) =
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DoPrim(PrimOps.Not, Seq(e), Nil, e.tpe)
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// Convert a port to a FIRRTL expression, handling polarity along the way.
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def portToExpression(pp: PolarizedPort): Expression =
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portToExpression(WRef(pp.name), Some(pp.polarity))
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def portToExpression(exp: Expression, polarity: Option[PortPolarity]): Expression =
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polarity match {
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case Some(ActiveLow) | Some(NegativeEdge) => not(exp)
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case _ => exp
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}
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// Check if a number is a power of two
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def isPowerOfTwo(x: Int): Boolean = (x & (x - 1)) == 0
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}
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