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Have PRCI control registers be clocked by the bus they hang off of (#1109)

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This was technically correct before if the CBUS clock was the implicit clock. but this change makes it correct when that is not the case
This commit is contained in:
Jerry Zhao
2022-02-08 11:03:55 -08:00
committed by GitHub
parent ef9c5b42ba
commit 9588d7536c
1 changed files with 2 additions and 2 deletions
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4
generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
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@@ -72,8 +72,8 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
:= ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey), p(DefaultClockFrequencyKey))
:= ClockGroupCombiner()
:= ClockGroupResetSynchronizer()
:= TileClockGater(prciParams.baseAddress + 0x00000, tlbus, prciParams.enableTileClockGating)
:= TileResetSetter(prciParams.baseAddress + 0x10000, tlbus, tile_prci_domains.map(_.tile_reset_domain.clockNode.portParams(0).name.get), Nil)
:= prci_ctrl_domain { TileClockGater(prciParams.baseAddress + 0x00000, tlbus, prciParams.enableTileClockGating) }
:= prci_ctrl_domain { TileResetSetter(prciParams.baseAddress + 0x10000, tlbus, tile_prci_domains.map(_.tile_reset_domain.clockNode.portParams(0).name.get), Nil) }
:= allClockGroupsNode)
}