From 9588d7536c3ea20170d0a3768b99af6fc28d98ca Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 8 Feb 2022 11:03:55 -0800 Subject: [PATCH] Have PRCI control registers be clocked by the bus they hang off of (#1109) This was technically correct before if the CBUS clock was the implicit clock. but this change makes it correct when that is not the case --- .../chipyard/src/main/scala/clocking/HasChipyardPRCI.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala index 30a29bcb..8c2a7365 100644 --- a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala +++ b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala @@ -72,8 +72,8 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles => := ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey), p(DefaultClockFrequencyKey)) := ClockGroupCombiner() := ClockGroupResetSynchronizer() - := TileClockGater(prciParams.baseAddress + 0x00000, tlbus, prciParams.enableTileClockGating) - := TileResetSetter(prciParams.baseAddress + 0x10000, tlbus, tile_prci_domains.map(_.tile_reset_domain.clockNode.portParams(0).name.get), Nil) + := prci_ctrl_domain { TileClockGater(prciParams.baseAddress + 0x00000, tlbus, prciParams.enableTileClockGating) } + := prci_ctrl_domain { TileResetSetter(prciParams.baseAddress + 0x10000, tlbus, tile_prci_domains.map(_.tile_reset_domain.clockNode.portParams(0).name.get), Nil) } := allClockGroupsNode) }