Reformat all scala files in iocells
- Mostly this reformat comments and large argument lists to classes and methods
This commit is contained in:
chick
@@ -6,8 +6,10 @@ import chisel3._
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import chisel3.util.{HasBlackBoxResource}
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import chisel3.experimental.{Analog, IntParam}
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class AnalogConst(value: Int, width: Int = 1) extends BlackBox(Map("CONST" -> IntParam(value), "WIDTH" -> IntParam(width))) with HasBlackBoxResource{
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val io = IO(new Bundle {val io = Analog(width.W) } )
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class AnalogConst(value: Int, width: Int = 1)
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extends BlackBox(Map("CONST" -> IntParam(value), "WIDTH" -> IntParam(width)))
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with HasBlackBoxResource {
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val io = IO(new Bundle { val io = Analog(width.W) })
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addResource("/barstools/iocell/vsrc/Analog.v")
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}
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@@ -4,7 +4,7 @@ package barstools.iocell.chisel
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import chisel3._
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import chisel3.util.{Cat, HasBlackBoxResource}
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import chisel3.experimental.{Analog, DataMirror, IO, BaseModule}
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import chisel3.experimental.{Analog, BaseModule, DataMirror, IO}
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// The following four IO cell bundle types are bare-minimum functional connections
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// for modeling 4 different IO cell scenarios. The intention is that the user
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@@ -13,24 +13,22 @@ import chisel3.experimental.{Analog, DataMirror, IO, BaseModule}
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// (https://github.com/sifive/sifive-blocks/blob/master/src/main/scala/devices/pinctrl/PinCtrl.scala),
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// but we want to avoid a dependency on an external libraries.
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/**
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* The base IO bundle for an analog signal (typically something with no digital buffers inside)
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* pad: off-chip (external) connection
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* core: internal connection
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*/
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/** The base IO bundle for an analog signal (typically something with no digital buffers inside)
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* pad: off-chip (external) connection
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* core: internal connection
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*/
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class AnalogIOCellBundle extends Bundle {
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val pad = Analog(1.W) // Pad/bump signal (off-chip)
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val core = Analog(1.W) // core signal (on-chip)
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val pad = Analog(1.W) // Pad/bump signal (off-chip)
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val core = Analog(1.W) // core signal (on-chip)
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}
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/**
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* The base IO bundle for a signal with runtime-controllable direction
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* pad: off-chip (external) connection
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* i: input to chip logic (output from IO cell)
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* ie: enable signal for i
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* o: output from chip logic (input to IO cell)
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* oe: enable signal for o
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*/
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/** The base IO bundle for a signal with runtime-controllable direction
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* pad: off-chip (external) connection
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* i: input to chip logic (output from IO cell)
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* ie: enable signal for i
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* o: output from chip logic (input to IO cell)
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* oe: enable signal for o
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*/
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class DigitalGPIOCellBundle extends Bundle {
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val pad = Analog(1.W)
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val i = Output(Bool())
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@@ -39,24 +37,22 @@ class DigitalGPIOCellBundle extends Bundle {
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val oe = Input(Bool())
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}
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/**
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* The base IO bundle for a digital output signal
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* pad: off-chip (external) connection
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* o: output from chip logic (input to IO cell)
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* oe: enable signal for o
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*/
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/** The base IO bundle for a digital output signal
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* pad: off-chip (external) connection
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* o: output from chip logic (input to IO cell)
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* oe: enable signal for o
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*/
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class DigitalOutIOCellBundle extends Bundle {
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val pad = Output(Bool())
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val o = Input(Bool())
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val oe = Input(Bool())
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}
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/**
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* The base IO bundle for a digital input signal
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* pad: off-chip (external) connection
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* i: input to chip logic (output from IO cell)
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* ie: enable signal for i
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*/
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/** The base IO bundle for a digital input signal
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* pad: off-chip (external) connection
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* i: input to chip logic (output from IO cell)
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* ie: enable signal for i
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*/
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class DigitalInIOCellBundle extends Bundle {
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val pad = Input(Bool())
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val i = Output(Bool())
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@@ -102,11 +98,10 @@ class GenericDigitalOutIOCell extends GenericIOCell with DigitalOutIOCell {
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val io = IO(new DigitalOutIOCellBundle)
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}
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trait IOCellTypeParams {
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def analog(): AnalogIOCell
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def gpio(): DigitalGPIOCell
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def input(): DigitalInIOCell
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def gpio(): DigitalGPIOCell
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def input(): DigitalInIOCell
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def output(): DigitalOutIOCell
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}
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@@ -118,47 +113,49 @@ case class GenericIOCellParams() extends IOCellTypeParams {
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}
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object IOCell {
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/**
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* From within a RawModule or MultiIOModule context, generate new module IOs from a given
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* signal and return the new IO and a Seq containing all generated IO cells.
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* @param coreSignal The signal onto which to add IO cells
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* @param name An optional name or name prefix to use for naming IO cells
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* @param abstractResetAsAsync When set, will coerce abstract resets to
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* AsyncReset, and otherwise to Bool (sync reset)
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* @return A tuple of (the generated IO data node, a Seq of all generated IO cell instances)
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*/
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def generateIOFromSignal[T <: Data](coreSignal: T, name: String,
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typeParams: IOCellTypeParams = GenericIOCellParams(),
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abstractResetAsAsync: Boolean = false): (T, Seq[IOCell]) =
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{
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/** From within a RawModule or MultiIOModule context, generate new module IOs from a given
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* signal and return the new IO and a Seq containing all generated IO cells.
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* @param coreSignal The signal onto which to add IO cells
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* @param name An optional name or name prefix to use for naming IO cells
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* @param abstractResetAsAsync When set, will coerce abstract resets to
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* AsyncReset, and otherwise to Bool (sync reset)
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* @return A tuple of (the generated IO data node, a Seq of all generated IO cell instances)
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*/
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def generateIOFromSignal[T <: Data](
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coreSignal: T,
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name: String,
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typeParams: IOCellTypeParams = GenericIOCellParams(),
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abstractResetAsAsync: Boolean = false
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): (T, Seq[IOCell]) = {
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val padSignal = IO(DataMirror.internal.chiselTypeClone[T](coreSignal)).suggestName(name)
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val resetFn = if (abstractResetAsAsync) toAsyncReset else toSyncReset
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val iocells = IOCell.generateFromSignal(coreSignal, padSignal, Some(s"iocell_$name"), typeParams, resetFn)
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(padSignal, iocells)
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}
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/**
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* Connect two identical signals together by adding IO cells between them and return a Seq
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* containing all generated IO cells.
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* @param coreSignal The core-side (internal) signal onto which to connect/add IO cells
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* @param padSignal The pad-side (external) signal onto which to connect IO cells
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* @param name An optional name or name prefix to use for naming IO cells
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* @return A Seq of all generated IO cell instances
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*/
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val toSyncReset: (Reset) => Bool = _.toBool
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/** Connect two identical signals together by adding IO cells between them and return a Seq
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* containing all generated IO cells.
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* @param coreSignal The core-side (internal) signal onto which to connect/add IO cells
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* @param padSignal The pad-side (external) signal onto which to connect IO cells
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* @param name An optional name or name prefix to use for naming IO cells
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* @return A Seq of all generated IO cell instances
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*/
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val toSyncReset: (Reset) => Bool = _.toBool
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val toAsyncReset: (Reset) => AsyncReset = _.asAsyncReset
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def generateFromSignal[T <: Data, R <: Reset](
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coreSignal: T,
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padSignal: T,
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name: Option[String] = None,
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typeParams: IOCellTypeParams = GenericIOCellParams(),
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concretizeResetFn : (Reset) => R = toSyncReset): Seq[IOCell] =
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{
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coreSignal: T,
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padSignal: T,
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name: Option[String] = None,
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typeParams: IOCellTypeParams = GenericIOCellParams(),
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concretizeResetFn: (Reset) => R = toSyncReset
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): Seq[IOCell] = {
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def genCell[T <: Data](
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castToBool: (T) => Bool,
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castFromBool: (Bool) => T)(
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coreSignal: T,
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padSignal: T): Seq[IOCell] = {
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castToBool: (T) => Bool,
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castFromBool: (Bool) => T
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)(coreSignal: T,
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padSignal: T
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): Seq[IOCell] = {
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DataMirror.directionOf(coreSignal) match {
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case ActualDirection.Input => {
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val iocell = typeParams.input()
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@@ -188,7 +185,10 @@ object IOCell {
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if (coreSignal.getWidth == 0) {
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Seq()
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} else {
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require(coreSignal.getWidth == 1, "Analogs wider than 1 bit are not supported because we can't bit-select Analogs (https://github.com/freechipsproject/chisel3/issues/536)")
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require(
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coreSignal.getWidth == 1,
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"Analogs wider than 1 bit are not supported because we can't bit-select Analogs (https://github.com/freechipsproject/chisel3/issues/536)"
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)
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val iocell = typeParams.analog()
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name.foreach(n => iocell.suggestName(n))
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iocell.io.core <> coreSignal
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@@ -204,7 +204,7 @@ object IOCell {
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// This dummy assignment will prevent invalid firrtl from being emitted
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DataMirror.directionOf(coreSignal) match {
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case ActualDirection.Input => coreSignal := 0.U
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case _ => {}
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case _ => {}
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}
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Seq()
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} else {
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