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remove functionality from clkgen pass due to compatibility issue with latest firrtl

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Angie
2017-04-02 04:34:38 -07:00
parent 7c0e6c89d2
commit 9305dd08eb
1 changed files with 2 additions and 1 deletions
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3
tapeout/src/main/scala/transforms/clkgen/CreateClkConstraints.scala
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@@ -24,7 +24,7 @@ class CreateClkConstraints(
// TODO: Are annotations only valid on ports? // TODO: Are annotations only valid on ports?
def run(c: Circuit): Circuit = { def run(c: Circuit): Circuit = {
/*
val top = c.main val top = c.main
// Remove everything from the circuit, unless it has a clock type // Remove everything from the circuit, unless it has a clock type
@@ -146,6 +146,7 @@ class CreateClkConstraints(
clkSrcs.foreach { x => println(s"gen clk: $x")} clkSrcs.foreach { x => println(s"gen clk: $x")}
clkModSinkToSourceMap.foreach { x => println(s"sink -> src: $x")} clkModSinkToSourceMap.foreach { x => println(s"sink -> src: $x")}
clkModSourceToSinkMap.foreach { x => println(s"src -> dependent sinks: $x")} clkModSourceToSinkMap.foreach { x => println(s"src -> dependent sinks: $x")}
*/
c c
} }
} }